JPS6223063A - Electronic counter control system for copying machine - Google Patents

Abstract

PURPOSE:To eliminate an inconvenience for suffering a disadvantage when viewed from a user side, by inhibiting a reset of the second time by a zero exponent detecting signal or a reset end holding signal. CONSTITUTION:A zero exponent is detected by using a microcomputer 12, and also a fact that a reset has been ended is recorded and held. The titled system has a single reset function for inhibiting a reset of the second time by these signals. In this way, a user can execute a zero reset exactly at the time of delivery, and an inconvenience for suffering a disadvantage when it has been seen from the user side can be eliminated.

Description

[Detailed description of the invention] (Technical field) The present invention relates to an electronic counter control system for a copying machine.

(Prior art) Office machines such as copying machines, facsimile machines, line printers, etc. are equipped with a total counter that counts the number of times the device is used, such as the number of copies, and charges are calculated and maintained based on the number of times the device is used. , often manages parts replacement, etc. Therefore, it is necessary to ensure that the counter display accurately matches the actual usage frequency of the device.

By the way, when copying machines and the like are delivered to the user's site, the f! approved and handed over. Naturally, the supplier must pay for the number of copies required for this confirmation.

Therefore, in the past, the counter value was set with a certain amount of the number of pages confirmed to be operating normally, and after installation the counter value was set to the user's starting value (for example, in the case of a 7-digit counter, the counter value was set between 9.997,000 and 9.997,000 before delivery. 995,0
00, and after making 3,000 to 5,000 confirmation copies, each digit was reset to zero).

However, the conventional reset mechanism is mechanical and has a complex combination of number wheel protrusions, pushbutton cams, levers, grooves, etc., and also has the disadvantage of a large operating force and a high rate of misresets. there were.

(Purpose) The present invention solves the drawbacks of the conventional example, and solves the problem when the index is a value before zero, that is, when the index is delivered to the manufacturer as described above, such as 9,997,000 or 9,995.000. The object of the present invention is to provide an electronic counter control method that can be reset only when the value of .

(Configuration) For this purpose, the present invention utilizes a microcomputer,
This device is characterized by having a single reset function that detects a zero index, records that it has been reset, and prohibits a second reset using these signals.

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a schematic perspective view of an electronic copy counter of the present invention, and FIG. 2 is a block diagram thereof.

Symbol 12 is a one-chip μCPU that controls this counter and holds count data, etc. For example, NEC's μPD7501G is suitable.

μcpu12 is a liquid crystal numeric display 13 (hereinafter referred to as LCD)
The well-known CMOS One consists of 24 segment outputs, 4 common outputs, and 24 individual output lines that can directly drive the ROM, ROM that stores the flow control program shown in Figure 4, and RAM that stores counters, operation flags, etc. It is a chip μCPU.

LCD13 is segment output 30-3 of μcpu12
23, is connected to the common output coMO~2, and its timing pulse is generated by the oscillation circuit 14 in a well-known dynamic lighting system.

The control line 15 from the output terminal P60 of μcpu12 is LC
When D13 is off, the oscillation circuit 14 is controlled to be stopped, reducing the consumption of the battery 16.

The battery 16 is a power source for holding the data of the counter 10 and driving all the circuits, and a lithium battery is suitable. According to experiments, μcpu12 described later
It can maintain functionality for about 5 years with 3V15QmAh in standby mode.

The switch 17 is a switch that sets the conditions for the answer signal of the counter, and is connected to the input terminal P40- of the μcpu 12.
Each switch is connected to P43 with a pull-up resistor, and the L and 61) r levels are active, and the number, length, etc. of answer signals for checking can be controlled by the combination of switches for each copying machine model. Set conditions. ? ! The structure is such that it is sealed with a cover when installed in the photocopier.

The switch 1 is a display switch for displaying the LCD 13 only when necessary, and when this switch is activated, the LCD 13 is displayed for 30 seconds. This switch is connected to the input terminal P11 of the μCPU 12, and is activated at a low level by a pull-up resistor.

The switch 19 is a single reset switch,
Normally, the copy counter of a copier is zero at the time of delivery, minus 3.
It is set to a value between 000 and 5000. A rental contract or maintenance service contract becomes valid when the indicated value of the counter starts from zero, and a single reset function is required to set it to zero when the contract is established. That is, when the most significant digit changes from 9 to 0, a flag for disabling the switch is stored in the RAM of the μcpu 12, and the flag is checked to enable or disable the function of the switch 19.

The switch 19 is connected to the input terminal P12 of μcp and u12, and the I and OW levels are activated through a pull-up resistor.

The photocoupler 20 is an interface circuit that receives and takes count-up signals from a PPC (plain paper copying machine).
It is electrically isolated from the PC. The signal from the PPC lights up the LED2OA, the light switches the off-off transistor 20B, and the output is sent to the μcpu1.
The count-up signal is input to the second input terminal P50.

The photocoupler 21 is an interface for an answerback signal that detects the count-up signal and sends it back to the PPC, and drives the transistor 22 with the output signal from the output terminal P30 of the μcpul 2, turns on the LED 21A, and outputs the signal via the phototransistor 21B. and supplies it to PPC. This interface circuit is also electrically isolated from the PPC.

These signals are connected to the PPC via a connector 23.

In standby mode, the internal functions of the μCPU 12 are stopped to save power consumption. For example, NEC's μP
In the D7501G, when the 5TOP instruction is executed, the standby mode is entered, and by applying a signal to the interrupt terminal, the standby mode is canceled and μcpul 2 is activated. To release the standby mode, either the count signal A1 display 5W1B activation signal B or the single reset switch SW19 activation signal C connected to the circuit shown in Figure 2 is activated, and the input of the NAND gate 26 goes low level. When it comes to N
The output of the AND gate becomes High level, and the μcpu
12 interrupt pin INTO for canceling standby mode
is activated and released.

Next, the operation of this counter 10 will be explained using the flows shown in FIGS. 3 to 6.

Step 100: This is an initial setting routine that is executed only when power from the battery 16 is applied to this counter.

This routine is executed only once, and its contents are as follows: (1) Resets the RAM content counter and flags of the ucpu 12.

■ Turn off the display and set each input/output setting condition, such as the input/output setting of the I10 boat, to the initial condition.

Step 101: This is a routine for setting the μCPU 12 to standby mode after each operation in order to minimize consumption of the battery 16.

Its execution is based on standby mode instructions such as the 5TOP instruction.

The μPD7501G of the μCPU 12 in the embodiment enters standby mode when the 5TOP instruction is executed.

It is released when each of the following external signals is active.

■When the display switch 18 is pressed, Step 102 ■When the single reset switch 19 is pressed, Step 1
03 ■When the count-up signal (Co) 200 comes from the copying machine, step 104 step 102
; When the display switch 18 is pressed, as shown in the circuit diagram of FIG. 2, the potential at the input point C of the connected NAND gate 26 becomes LOW level, the output becomes H4gh level, and the connected μCPU 12 Since the interrupt input for canceling standby mode becomes active, standby mode is canceled.

The process then proceeds to step 105 of the display processing routine.

Step 103: When the single reset switch 19 is pressed, the connected N A N D gate 2 is activated as shown in the circuit diagram of FIG.
The potential of the input point B of 6 becomes Low level, and the output goes High.
Since the interrupt input for canceling the standby mode of the connected μCPU 12 becomes active at the gh level, the standby mode is canceled.

The process then proceeds to step 106 of the single reset processing routine.

Step 104: As shown in the circuit diagram of FIG. 2, a count signal (Co) 200 from the copying machine is applied to turn on the photocoupler 20A through the connector 23, and the phototransistor 20B is connected to ONL. The potential at the input point A of the NAND gate 26 becomes LOW level, and the output becomes HIGH.
When it reaches the h level, the interrupt input for canceling the standby mode of the connected μCPU 12 becomes active, and the standby mode is canceled.

The process then proceeds to step 107 of the answerback countup processing routine.

Step 105: Display processing routine, the operation flow of which is shown in FIG.

When the display switch 18 is pressed, the standby mode is canceled in step 102, and a display time of 30 seconds is set and started using the built-in timer of the μCPU 12 (step 1).
05A) System? 11 line 15 to High level to start oscillation of the display timing pulse oscillation circuit 14 (Step 105B) The counter data stored in the RAM of the μCPU 12 is output to the LCD 13 and displayed (Step 105G) Display. If a count-up signal arrives during the count-up signal, it cannot be counted, so check it (step 105D).Next, check the overtime of the 30-second timer (
Step 105E): If the time is not over, the display continues, but if the time is over, the display on the LCD 13 is turned off.Step 105F): The control a line 15 is output to the LOW level and the display timing pulse oscillation circuit 14 is stopped. (Step 1'05G) Return to standby mode (step 102) and enter standby mode.

Step 106: Single reset processing routine, the operation flow of which is shown in FIG.

When the single reset switch 19 is pressed, step 102
The standby mode is released, and in the step 10 full routine, it is determined whether the counter contents are zero each time the count up (step 107G), and when it becomes zero, a flag is set in the RAM of the μCPU 12 to disable the single reset function. Therefore, first, it is checked whether or not this flag is set (step 106A).

If it is not set, set it and reset the counter (step 106B).Of course, if it is set, this single reset function is invalid, so step 1
Proceed to 02.

Step 107: Answer back count up processing routine,
The operation flow is shown in FIG.

Count-up signal (CO) 20 from the copying machine in Figure 7
When 0 comes to the connector 23, the μCPU 12 detects the count signal via the interface circuit 20 of FIG.

The μcpu 12 first checks whether the counter has overflowed (meaning 9,999.999 in a 7-digit counter) (step 107A). If the counter has overflowed, the display of 9,999,999 remains constant. The process ends without outputting an answer signal by blinking the time (steps 107B and 107C).

If the counter does not overflow, step 10
Proceed to step 70 and send the answer signal (AK) 201 in FIG.
The rcpu 12 outputs to the copying machine via the interface circuit 21 shown in FIG.

In the embodiment, as shown in FIG. 7, the count-up signal (Go) 200 from the copying machine is Looms, and the answer signal (AK) 201 outputs two 1-ms pulses after a 30-ms delay time.

' Note that T indicates the count-up timing.

That is, an answer signal is processed and output in response to a count up signal (counter step signal).

FIG. 8 shows an embodiment of a power supply circuit for controlling operation and non-operation of a copying machine.

The commercial power supply of AClooV is connected to the control power supply circuit 150 via the power switch, and then the relay switch (contact) S
Power is supplied to the driving power supply circuit 151 via R.

A control power supply circuit 150 supplies DC power to the μCPU 152, various sensors, etc., while a drive power supply circuit 151 supplies a drive motor 153 for a photoreceptor drum, etc., a halogen lamp 154 for exposure, etc. AC power is supplied to the heater of the fixing device 155, etc.

Main relay RA is controlled by μcpu152. When the energization is released, turn off the relay switch SR.
Then, the power to the drive power supply circuit 151 is cut off, and the copying machine becomes in a state in which copying is disabled.

The μCPU 152 of the copying machine outputs the count-up signal CO from the connector 23 in FIG.
The values of both signals at the timing of tl are determined, and if both signals CO and AK are output as shown in the correspondence diagram shown in FIG. 9, the answer signal is 39ms with respect to the counter signal.
Since a predetermined number of outputs are being output due to the delay, it is determined to be normal, and main relay RA is kept on, and counter step signal 200 is maintained for the time indicated by the solid line in FIG.

If both signals Co and AK are not output as shown in Fig. 9, it is determined that there is an abnormality, and the main relay RA is turned off and the relay switch SR is turned off to make the copy impossible, and the count-up signal ( Co) 200 is immediately dropped as shown in the dotted line in Figure 7.

In step 107D, the count up signal is checked and the counter is incremented by one (step 107E), and in step 107G, it is determined whether the initial setting value has gone from minus to zero, and a single reset flag is set.

Then, the process returns to step 102 and waits.

This check program is the control μCpu152 of the copying machine.
is stored in.

(Effects) The present invention is as described above, and according to the present invention, it is possible to accurately reset to zero at the time of delivery to the user, so there is no disadvantage of incurring disadvantages from the user's perspective. I can do it.

[Brief explanation of drawings]

FIG. 1 is an external perspective view of an electronic counter according to the present invention, FIG. 2 is a block diagram thereof, and FIGS. 3 and 4. 5 and 6 are flowcharts showing the control operation,
FIG. 7 is a timing chart of the count-up signal and answer signal, FIG. 8 is a power supply circuit diagram of the copying machine, and FIG. 9 is a diagram showing the correspondence between each signal in FIG. 7 and the signal at a predetermined timing. . 10...Electronic counter, 12...μC for counter
pu, 152...μcpu for copying machine・1发Fig. 1 19 12:5 Fig. 4 Fig. 5 Rei 7 Fig. 9

Claims (1)

[Claims] A total number of copies counter of a copying machine controlled by a microcomputer includes means for counting the number of copies from the copying machine one by one, means for detecting a zero index, means for resetting the counter, and having been reset. 1. An electronic counter control method for a copying machine, characterized in that a second reset is prohibited by a zero index detection signal or a reset hold signal.