JPS62230059A - Formation of semiconductor storage device - Google Patents
Formation of semiconductor storage deviceInfo
- Publication number
- JPS62230059A JPS62230059A JP7374586A JP7374586A JPS62230059A JP S62230059 A JPS62230059 A JP S62230059A JP 7374586 A JP7374586 A JP 7374586A JP 7374586 A JP7374586 A JP 7374586A JP S62230059 A JPS62230059 A JP S62230059A
- Authority
- JP
- Japan
- Prior art keywords
- film
- dielectric film
- semiconductor
- layer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 230000015572 biosynthetic process Effects 0.000 title description 7
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000006243 chemical reaction Methods 0.000 claims abstract description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000010408 film Substances 0.000 claims description 49
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 230000000903 blocking effect Effects 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 5
- 230000003287 optical effect Effects 0.000 abstract description 5
- 230000006798 recombination Effects 0.000 abstract description 2
- 238000005215 recombination Methods 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 229910021529 ammonia Inorganic materials 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 5
- 229910052753 mercury Inorganic materials 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- GVGCUCJTUSOZKP-UHFFFAOYSA-N nitrogen trifluoride Chemical compound FN(F)F GVGCUCJTUSOZKP-UHFFFAOYSA-N 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000006552 photochemical reaction Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- -1 GaAs and InP Chemical class 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000012265 solid product Substances 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
「発明の利用分野」
本発明は、絶縁ゲイト型電界効果半導体メモリ装置(I
GFという)であって、ゲイト絶縁膜を構成する第1の
誘電体膜とその上側の電荷捕獲中心を光化学反応を用い
たCVO<気相反応)方法により形成する作製方法に関
する。DETAILED DESCRIPTION OF THE INVENTION Field of Application of the Invention The present invention relates to an insulated gate field effect semiconductor memory device (I
The present invention relates to a manufacturing method for forming a first dielectric film constituting a gate insulating film and a charge trapping center above the dielectric film by a CVO method using a photochemical reaction (referred to as GF).
「従来の技術」
IGFを用いて不揮発性メモリを作らんとするとMNO
S (ゲイト電極−窒化珪素一酸化珪素一シリコン半導
体基板) 、 MMCO3(ゲイト電極−窒化珪素膜一
半導体のクラスタまたは膜−酸化珪素膜−シリコン半導
体基板) 、 MNCNOS (ゲイト電極−窒化珪素
膜′−半導体のクラスタまたは膜−窒化珪素一酸化珪素
一シリコン半導体基板)等の多くの基板が知られている
。さらにこのシリコン半導体上に薄く形成する酸化珪素
膜を劣化の少ない塩酸酸化法で形成する方法が知られて
いる。それらの代表例は、本発明人の特許[半導体メモ
リ装置 特公昭5〇−36955J又本発明人の論文に
なるCeramic BulletinVo164.
No、12(1985)1585−1589 rMe
tal−Insulator−3emiconduct
or(Fulrath Award Paper)jに
示されている。"Conventional technology" When trying to create non-volatile memory using IGF, MNO
S (gate electrode-silicon nitride silicon monoxide-silicon semiconductor substrate), MMCO3 (gate electrode-silicon nitride film-semiconductor cluster or film-silicon oxide film-silicon semiconductor substrate), MNCNOS (gate electrode-silicon nitride film'- Many substrates are known, such as clusters or films of semiconductors (silicon nitride, silicon monoxide, silicon semiconductor substrates). Furthermore, a method is known in which a thin silicon oxide film is formed on this silicon semiconductor using a hydrochloric acid oxidation method that causes less deterioration. Typical examples thereof include the inventor's patent [Semiconductor Memory Device, Japanese Patent Publication No. 50-36955J, and the inventor's paper Ceramic Bulletin Vol. 164.
No. 12 (1985) 1585-1589 rMe
tal-Insulator-3emiconduct
or (Fulrath Award Paper)j.
「発明が解決しようとする問題点」
しかし、かかる不揮発性メモリにおいて、ICカードへ
の応用を目的とし、その書き換え回数の改良が求められ
ていた。しかしこの書き換え回数はlXIO3〜3Xl
O”回までであり、それ以上とする手段がこれまで見出
されていなかった。しかしICカード等においては10
’回以上の書き換えが可能であることが求められていた
。``Problems to be Solved by the Invention'' However, there has been a demand for an improvement in the number of rewrites of such nonvolatile memories for the purpose of application to IC cards. However, this number of rewrites is lXIO3~3Xl
Up to O" times, and no means have been found so far to increase the number beyond that. However, for IC cards etc.
It was required to be able to be rewritten more than 'times.
初期値に対する変化率を10%以内である場合を「良」
とした基準において、この書き換え回数を多くする方法
として、半導体基板に密接する酸化珪素膜をアンモニア
中で1150〜1200℃の高温で窒化珪素に変成させ
る方法が知られている。また半一 導体基板をそれ自
体を同様の温度で直接窒化して窒化珪素膜20〜100
人の厚さに形成する方法が知られている。するとこの窒
化珪素を用いることにより、MMCNO3,MNCNS
の構造を得ることができる。“Good” if the rate of change from the initial value is within 10%
Based on this standard, a known method for increasing the number of rewrites is to transform a silicon oxide film in close contact with a semiconductor substrate into silicon nitride in ammonia at a high temperature of 1150 to 1200°C. Alternatively, a silicon nitride film of 20 to 100% can be formed by directly nitriding the semiconductor substrate itself at a similar temperature.
A method of forming it to the thickness of a person is known. Then, by using this silicon nitride, MMCNO3, MNCNS
structure can be obtained.
しかし、かかる高温処理は基板内に設けられた接合部に
スタッキングフォルトを誘発し・また不純物の再拡散を
促し、結果として基板材料の劣化をもたらし、超LSI
において不十分といわざるを得ない。However, such high-temperature treatment induces stacking faults in the junctions provided in the substrate and promotes re-diffusion of impurities, resulting in deterioration of the substrate material and
It must be said that this is insufficient.
r問題を解決するための手段」
本発明はこれらの問題を解決するため、下地の酸化珪素
膜またはシリコン半導体基板にまったく損傷を与えるこ
とない安定な第1の誘電体被膜を光CVD法で形成せし
めたものである。さらにこの第1の誘電体膜は10〜5
0人ときわめて薄いため、さらにこの上に積層して設け
られる電荷捕獲中心層(以下トラップレイヤー即ちTL
ともいう)をも光CVD法で形成せんとするものである
。そしてこの上に第2の誘電体被膜をプラズマCVD法
、光CVD法等の手段好ましくは光CVD法により形成
することにより、MIzTLI+S(ゲイト電極−第2
の誘電体膜−電荷捕獲中心層一第1の誘電体膜−半導体
基板)構造を得んとするものである。そしてItTLh
の積層構造によりフローティング電荷捕獲中心層(以下
FTLという)を得るものである。またこのTLはシリ
コン半導体等の半導体のクラスタまたは薄膜さらにまた
は半導体の不対結合手を有する層よりなる。また、特に
その第1の誘電体膜は窒化珪素よりなり、これらを半導
体基板上またはこの半導体上に予め形成されたブロッキ
ング層例えば5〜20人の厚さの酸化珪素股上に二層膜
(I 、 −TL)を形成させんとしたものである。In order to solve these problems, the present invention uses a photo-CVD method to form a stable first dielectric film that does not cause any damage to the underlying silicon oxide film or silicon semiconductor substrate. It was forced upon me. Furthermore, this first dielectric film has a 10 to 5
Since it is extremely thin, the charge trapping center layer (hereinafter referred to as trap layer, TL) is further laminated on top of this layer.
) is also intended to be formed by the photo-CVD method. Then, by forming a second dielectric film on this by a plasma CVD method, a photo CVD method, etc., preferably a photo CVD method, MIzTLI+S (gate electrode - second dielectric film) is formed.
The present invention aims to obtain a structure (dielectric film-charge trapping center layer-first dielectric film-semiconductor substrate). And ItTLh
A floating charge trapping center layer (hereinafter referred to as FTL) is obtained by the laminated structure. Further, this TL is made of a cluster or thin film of a semiconductor such as a silicon semiconductor, or a layer having a semiconductor dangling bond. In particular, the first dielectric film is made of silicon nitride, and these are coated on a semiconductor substrate or on a blocking layer previously formed on this semiconductor, such as a two-layer film (I , -TL).
「作用」
この第1の誘電体膜およびTLを光CVO法で作ること
により、この形成温度を700℃以下一般には300〜
500℃とすることができ、形成された被膜内にシリコ
ンのクラスタを有さず、化学量論的に不対結合手が殆ど
ない窒化物を作ることができる。"Function" By making this first dielectric film and TL using the optical CVO method, the formation temperature can be reduced to 700°C or less, generally 300 to 300°C.
The temperature can be set at 500° C., and a nitride having no silicon clusters in the formed film and having almost no dangling bonds stoichiometrically can be produced.
また下地の基板およびその内部に設けられている接合に
損傷を与えない、さらに低温で作られる良質の絶縁膜を
第1の誘電体膜とするため、残留歪を半導体基板との界
面に与えない。結果として、かかる応力集中のおきやす
い領域での再結合部の生成による書きええ回数の低下を
防ぐことができる。In addition, since the first dielectric film is a high-quality insulating film that does not damage the underlying substrate or the bonding provided inside it, and is made at low temperatures, no residual strain is imparted to the interface with the semiconductor substrate. . As a result, it is possible to prevent a decrease in the number of write operations due to the generation of recombination portions in areas where such stress concentration is likely to occur.
これらの特性のため、書き換え回数が10h回までも耐
えることが可能となった。さらにかかる積層構造はチャ
ネル長が1μまたはそれ以下のショートチャネルMIS
、Fl!Tにおいても超LSIのパターニングを何等の
問題な(処理することができる。Because of these characteristics, it has become possible to withstand up to 10 hours of rewriting. Furthermore, such a stacked structure is a short channel MIS with a channel length of 1μ or less.
, Fl! Even in T, patterning of VLSI can be handled without any problems.
実施例1 第1図に本発明のIGFの縦断面図を示す。Example 1 FIG. 1 shows a longitudinal cross-sectional view of the IGF of the present invention.
図面において、基板(1)、フィールド絶縁物(2)。In the drawing: substrate (1), field insulator (2).
第1の誘電体膜(3−1> 、 TL (3−2) 、
第2の誘電体膜(3−3)よりなるFTL (3)をゲ
イト絶縁物として有する。First dielectric film (3-1>, TL (3-2),
It has an FTL (3) made of a second dielectric film (3-3) as a gate insulator.
ゲイト電極(6)、ソース(7)、ドレイン(7”)、
チャネルカット(9)、チャネル形成領域(10)より
なっている。Gate electrode (6), source (7), drain (7”),
It consists of a channel cut (9) and a channel forming region (10).
図面はNチャネルIGFであり、基板(1)上にP(1
0)のチャネル形成領域を有し、チャネル長は1.5μ
チヤネル巾10μとした。ゲイト電極は珪化チタンとし
た。第1の誘電体膜(3−1)は窒化珪素膜よりなり、
その平均厚さは30人を有せしめた。この光CVD法に
よる窒化珪素を形成する前に、基板を300〜500°
Cとし酸素またはアンモニア雰囲気とし185nmの波
長の紫外光を照射し、表面の有機物等の汚物の除去を行
うとともに、きわめて薄い酸化珪素膜又は窒化珪素膜を
固相−気相の酸化または窒化で形成してブロッキング層
としてもよい。The drawing shows an N-channel IGF with P(1) on the substrate (1).
0), and the channel length is 1.5μ.
The channel width was 10μ. The gate electrode was made of titanium silicide. The first dielectric film (3-1) is made of a silicon nitride film,
Its average thickness had 30 people. Before forming silicon nitride using this photo-CVD method, the substrate is held at a temperature of 300 to 500°.
In an oxygen or ammonia atmosphere, ultraviolet light with a wavelength of 185 nm is irradiated to remove organic matter and other contaminants from the surface, and an extremely thin silicon oxide film or silicon nitride film is formed by solid-vapor phase oxidation or nitridation. It may also be used as a blocking layer.
さらにその上のTL(3−2)はシリコン半導体を光化
学反応により30〜2000人の平均厚さ例えば100
人の厚さに形成した。さらに上面を第2の誘電体膜(3
)を光CVD法により500〜1000人の厚さに形成
した。次にゲイト電極を形成し、更にその後、ソース(
7)、ドレイン(8)をN型低不純物濃度領域(7−1
)とN゛型型下不純物濃度領域7−2)とをセルファラ
イン法により作製した。Furthermore, the TL (3-2) above it is made of silicon semiconductor with an average thickness of 30 to 2000, for example, 100 by photochemical reaction.
Formed to the thickness of a person. Furthermore, the upper surface is coated with a second dielectric film (3
) was formed to a thickness of 500 to 1000 layers by photo-CVD. Next, a gate electrode is formed, and then a source (
7), the drain (8) is connected to the N-type low impurity concentration region (7-1
) and N-type lower impurity concentration region 7-2) were fabricated by the self-line method.
かかる構造において、ゲイト電圧を±25Vに100μ
秒のパルス巾を繰り返し書き替えを行った。するとスレ
ッシュホルド電圧が±7vを得ることができた。その値
は1×10h回行っても初期値に対し約7χの変化率し
かなく、これまでのIGFより10”〜10’倍も書き
換えの寿命が大きくなった。In such a structure, the gate voltage is set to ±25V by 100μ.
The pulse width of seconds was repeatedly rewritten. As a result, a threshold voltage of ±7v could be obtained. Even when the value was repeated 1×10 h, there was only a rate of change of about 7χ from the initial value, and the rewriting life was 10'' to 10' times longer than that of the conventional IGF.
実施例2
以下第2図に示した図面に基づき本発明の窒化珪素膜(
SiJ4)およびSiのクラスタまたは膜の製造の詳細
を記す。Example 2 The silicon nitride film of the present invention (
Details of the fabrication of SiJ4) and Si clusters or films are described.
第2図において、被形成面を有するシリコン基板(1)
はホルダ(1゛)に保持され、反応室(12)内のハロ
ゲンヒータ(13)(上面を水冷(31))に近接して
設けられている。反応室(12) 、紫外光源が配設さ
れた光源室(35)及びヒータ(13)が配設された加
熱室(30)は、それぞれの圧力を10torr以下の
概略同一の真空度に保持した。このために反応に支障の
ない気体(窒素、アルゴンまたはアンモニア)を(28
)より(36)に供給し、または(36”)より排気す
ることにより成就した。また透光性遮蔽板である石英窓
(40)により、光源室(35)と反応室(12)とが
仕切られている。この窓(40)の上側にはノズル(3
4)が設けられ、このノズルは光CVD法に用いるアン
モニア(NHi)、プラズマエッチに用いる弗化窒素(
NF3)用のノズル(34°゛)が噴出口を下向き(窓
向き”) (32)に5iJ4の作製に用いる5i2H
b+5iJb+5i3H,用のノズル(34°)が噴出
口を上向き(基板向き”) (33)に設けている。In FIG. 2, a silicon substrate (1) having a surface to be formed
is held in a holder (1') and provided close to a halogen heater (13) (the top surface of which is water-cooled (31)) in the reaction chamber (12). The reaction chamber (12), the light source chamber (35) in which the ultraviolet light source was disposed, and the heating chamber (30) in which the heater (13) was disposed were maintained at approximately the same degree of vacuum of 10 torr or less. . For this purpose, a gas (nitrogen, argon or ammonia) that does not interfere with the reaction (28
This was achieved by supplying air to (36) from ) or exhausting air from (36'').Also, the light source chamber (35) and reaction chamber (12) were There is a nozzle (3) on the upper side of this window (40).
4), and this nozzle is equipped with ammonia (NHi) used in the photo-CVD method and nitrogen fluoride (NHi) used in plasma etching.
The nozzle (34°) for NF3) is oriented downward (facing the window) (32) for 5i2H used in the production of 5iJ4.
b+5iJb+5i3H, the nozzle (34°) has its ejection port facing upward (towards the substrate) (33).
このノズル(34)は光CVD法で被膜を形成してしま
った後、窓(40)上に形成される不要物のプラズマエ
ッチ法による除去を行う際の高周波電源(15)(周波
数13.56MHz)の一方の電極となっている。This nozzle (34) uses a high frequency power source (15) (frequency: 13.56 MHz) to remove unnecessary materials formed on the window (40) by plasma etching after forming a film by photo-CVD. ) is one of the electrodes.
光源室の排気に際し逆流により反応性気体の光源室まで
の混入防止のためヒータ(29)を配設した。A heater (29) was provided to prevent reactive gas from entering the light source chamber due to backflow when the light source chamber was evacuated.
これにより反応性気体のうちの分解後固体となる成分を
トラップし気体のみの進入とさせた。This traps the components of the reactive gas that become solid after decomposition, allowing only the gas to enter.
移動に関し、圧力差が生じないようにしたロード・ロッ
ク方式を用いた。まず、予備室(14)にて基板(1)
、ホルダ(1゛)および基板および基板おさえ(1”)
(熱を効率よく基板に伝導させる)を挿入・配設し、真
空引きをした後、ゲート弁(16)を開とし、反応室(
12)に移し、またゲート弁(16)を閉として、反応
室(12)、予備室(14)を互いに仕切った。Regarding movement, a load-lock system was used to prevent pressure differences from occurring. First, the board (1) is placed in the preliminary room (14).
, holder (1゛), board and board support (1")
(to efficiently conduct heat to the substrate), and after evacuating, open the gate valve (16) and open the reaction chamber (
12), and the gate valve (16) was closed to partition the reaction chamber (12) and preliminary chamber (14) from each other.
ドーピング系(37)は、バルブ(22) 、流量計(
21)よりなり、反応後固体生成物を形成させる反応性
気体は(23) i (24)より、また反応抜気体生
成物は(25) 、 (26)より反応室(12)へ供
給させた。反応室の圧力制御は、コントロールバルブ(
17) 、コック(20)を経てターボ分子ポンプ(大
阪真空製PG550を使用) (1B) 、ロータリー
ポンプ(19)を経、排気させた。The doping system (37) includes a valve (22), a flow meter (
21), the reactive gas forming the solid product after the reaction was supplied to the reaction chamber (12) from (23) i (24), and the reaction gaseous products were supplied from (25) and (26) to the reaction chamber (12). . The pressure in the reaction chamber is controlled using a control valve (
17), a turbo molecular pump (PG550 manufactured by Osaka Vacuum Co., Ltd. was used) (1B), and a rotary pump (19) for exhaustion.
排気系(38)はコック(20)により予備室(14)
を真空引きをする際はそちら側を開とし、反応室(12
)側を閉とする。また反応室を真空引きする際は反応室
を開とし、予備室側を閉とした。The exhaust system (38) is connected to the preliminary chamber (14) by the cock (20).
When vacuuming the chamber, open that side and open the reaction chamber (12
) side is closed. Furthermore, when evacuating the reaction chamber, the reaction chamber was opened and the preliminary chamber side was closed.
か(して基板を反応室に図示の如く挿着した。Then, the substrate was inserted into the reaction chamber as shown.
この反応室の真空度は10− ’ torr以下とした
。この後(28)より窒素を導入しさらに反応性気体を
(37)より反応室に導入して被膜形成を行った。The degree of vacuum in this reaction chamber was set to 10-' torr or less. Thereafter, nitrogen was introduced from (28) and a reactive gas was further introduced into the reaction chamber from (37) to form a film.
反応用光源は低圧水銀灯(34)とし、水冷(31”)
を設けた。その紫外光源は、低圧水銀灯(185nm。The light source for the reaction was a low-pressure mercury lamp (34), water-cooled (31”).
has been established. The ultraviolet light source is a low-pressure mercury lamp (185 nm).
254nmの波長を発光する発光長40cm、照射強度
15mW/cm”、ランプ電力40W)ランプ数16本
である。There are 16 lamps (luminous length: 40 cm, irradiation intensity: 15 mW/cm", lamp power: 40 W) that emit light at a wavelength of 254 nm.
この紫外光は、透光性遮蔽板である石英(40)を経て
反応室(12)の基板(1)の被形成面(1)上を照射
する。This ultraviolet light passes through quartz (40), which is a transparent shielding plate, and irradiates onto the formation surface (1) of the substrate (1) in the reaction chamber (12).
ヒータ(13)は反応室の上側に位置した「ディボジソ
ション・アップ」方式とし、フレークが被形成面に付着
してピンホールの原因を作ることを避けた。The heater (13) was of the "deposition up" type and was located above the reaction chamber to avoid flakes from adhering to the surface to be formed and causing pinholes.
反応室はステンレスであり、光源室、加熱室(30)も
ともに真空引きをし、それぞれの圧力差を10torr
以下とした。その結果、従来例に示される如く、大面積
の照射用に石英板の面積を大きくすると圧力的に耐えら
れないという欠点を本発明は有していない。即ち、紫外
光源も真空下に保持された光源室と反応室とを囲んだス
テンレス容器内に真空に保持されている。このため、5
インチまたは6インチのウェハの大きさではなく 30
cm x 3ocmの大きさの基板をも何等の工業的な
問題もなく作ることができ得る。The reaction chamber is made of stainless steel, and both the light source chamber and heating chamber (30) are evacuated to maintain a pressure difference of 10 torr.
The following was made. As a result, the present invention does not have the disadvantage of not being able to withstand pressure when the area of the quartz plate is increased for irradiation of a large area, as shown in the conventional example. That is, the ultraviolet light source is also kept under vacuum in a stainless steel container surrounding a light source chamber and a reaction chamber that are kept under vacuum. For this reason, 5
inch or 6 inch wafer size instead of 30
Substrates as large as cm x 3 ocm can also be produced without any industrial problems.
図面の場合の被形成有効面積は30cm X 30cr
aであり、直径5インチの基板(1)5枚がホルダ(1
゛)に配設され得る構成とし、基板の温度はハロゲンヒ
ータ(13)により加熱し、室温〜500℃までの所定
の温度とした。In the case of the drawing, the effective area to be formed is 30cm x 30cr
a, and five boards (1) with a diameter of 5 inches are placed in a holder (1).
The substrate was heated by a halogen heater (13) to a predetermined temperature ranging from room temperature to 500°C.
以下にFTLの実験例を示す。 実験例Si2H6,5
izF6又はSt 38Bを(23)に連結し、3cc
/分で供給した。(25)よりアンモニアを30cc/
分で供給した。すると、これらは紫外光源(34)より
185nmの光を受けて水銀を用いることなく光分解し
、アンモニアと反応し、Si、N、被膜を基板(1)の
被形成面に形成させることができた。即ち、第1図に示
したごとき下地半導体上またはかがる半導体表面を処理
した後にこの上に窒化珪素を20〜200人代表的には
30〜50人の厚さで形成させることができた。An experimental example of FTL is shown below. Experimental example Si2H6,5
izF6 or St 38B was connected to (23) and 3cc
/min. 30cc/ of ammonia from (25)
Supplied in minutes. Then, they receive 185 nm light from the ultraviolet light source (34) and are photolyzed without using mercury, reacting with ammonia, and forming Si, N, and a coating on the surface of the substrate (1). Ta. That is, after processing the underlying semiconductor or the exposed semiconductor surface as shown in FIG. 1, silicon nitride could be formed thereon to a thickness of 20 to 200, typically 30 to 50. .
さらにこの上にTLを形成するためこれら全体を真空引
きした。Further, the entire structure was evacuated to form a TL thereon.
次に5izH,を(23)より5 cc/分で供給した
。すると、5izH6は光源室に水銀を用いることなく
分解し、シリコン半導体のクラスタ(平均膜厚3o〜1
00人においては島状にシリコンが形成され、クラスタ
構造となる)を形成させる。または平均厚さを200〜
2000人とした膜状となる。100〜200人の双方
の混合状態をも得るこたとができる。半導体の形成速度
は6人/分(圧力3torr、温度350℃)を得るこ
とができた。かくしてTL(第1図(3−2)を形成し
た。Next, 5izH was supplied from (23) at 5 cc/min. Then, 5izH6 decomposes without using mercury in the light source chamber and forms silicon semiconductor clusters (average film thickness 3o~1
00 people, silicon is formed in island shapes, forming a cluster structure). Or the average thickness is 200~
It becomes a membranous state with 2,000 people. It is also possible to obtain a mixture of 100 to 200 people. A semiconductor formation rate of 6 persons/min (pressure: 3 torr, temperature: 350° C.) was achieved. In this way, the TL (FIG. 1 (3-2)) was formed.
なお、この半導体は紫外光の吸収が大きいため、さらに
この上に同じ反応炉を用いて連続的に第2の誘電体膜(
第1図(3−2))を形成するためにはプラズマCVD
法で形成しなければならない。このためにはNH3/5
itHb≧50とし、13.56MHzの高周波プラズ
マを加えて所定の厚さを形成すればよい。Since this semiconductor has a high absorption of ultraviolet light, a second dielectric film (
In order to form Figure 1 (3-2)), plasma CVD is used.
It must be formed by law. For this, NH3/5
It is sufficient to set itHb≧50 and apply high frequency plasma of 13.56 MHz to form a predetermined thickness.
□この後実施例1に示したごとく、かかるFTLを用い
てIGFを作成した。□Thereafter, as shown in Example 1, IGF was prepared using this FTL.
被膜形成後、第2図に示した光CVO装置に関しては、
窓(40)のプラズマエツチングを(26)よりNF3
を供給しプラズマ反応を行った。かくして窓(4o)を
清浄にし、2回目のFTLの形成の作業を行うことがで
きる。After film formation, regarding the optical CVO device shown in FIG.
Plasma etching of window (40) from (26) with NF3
was supplied to perform a plasma reaction. The window (4o) is thus cleaned and the second FTL formation operation can be performed.
このFTL形成を10回繰り返しても、同じ膜厚を同一
条件で得ることができた。Even if this FTL formation was repeated 10 times, the same film thickness could be obtained under the same conditions.
r効果」
本発明は以上の説明より明らかなごとく、ゲイト絶縁膜
としてTLとその下側(基板側)の第1の誘電体膜を光
CVD法を用いて形成したものである。r effect" As is clear from the above description, in the present invention, the TL as a gate insulating film and the first dielectric film below it (on the substrate side) are formed using a photo-CVD method.
その結果、基板の損傷が少なく、また半導体表面より所
定の距離にTLを作ることができた。特にかかる窒化珪
素膜が300〜500℃の温度で作ったにもかかわらず
、5i−N結合が切れないため、書き換えに伴う劣化が
生じなくいという大きい特長を有する。As a result, there was little damage to the substrate, and the TL could be formed at a predetermined distance from the semiconductor surface. In particular, even though such a silicon nitride film is formed at a temperature of 300 to 500° C., the 5i-N bonds are not broken, so it has the great advantage that no deterioration occurs due to rewriting.
また本発明において、チャネル形成領域は珪素にあって
はゲイト絶縁物は酸化珪素および窒化物被膜の二層膜が
優れていた。しかしGaAs、 InP等のm−v化合
物にあっては、これらの半導体と酸化珪素とが高温動作
テストにおいて反応し劣化するため、Si+Naのみと
する方が好ましかった。即ち半導体にSi3N、を直接
密接させてゲイト電極の構造とせしめればよい。Further, in the present invention, when the channel forming region is made of silicon, a two-layer film of silicon oxide and a nitride film is excellent as the gate insulator. However, in the case of m-v compounds such as GaAs and InP, these semiconductors and silicon oxide react and deteriorate during high-temperature operation tests, so it was preferable to use only Si+Na. That is, Si3N may be directly brought into close contact with the semiconductor to form a gate electrode structure.
絶縁膜の絶縁耐圧は、光CVD法による窒化珪素の3.
5 X 10’V/cmはプラズマCVD法による窒化
珪素のI Xl06V/cmよりも3.5倍も高い耐圧
を有していた。The dielectric strength voltage of the insulating film is 3.3.
5.times.10'V/cm had a breakdown voltage 3.5 times higher than I.times.106V/cm of silicon nitride produced by plasma CVD.
さらに±3X10’ν/cn+の電界に相当する電圧を
加えても、スレッシュホールド電圧の変化は±0゜2ν
以下の範囲でしかドリフトをしなかった。Furthermore, even if a voltage corresponding to an electric field of ±3X10'ν/cn+ is applied, the change in threshold voltage is ±0°2ν.
I only drifted within the following range.
このことより、かかる窒化珪素膜を半導体基板とTLと
の間の第1の誘電体膜として用いるならばここでの不対
結合手が情報の書き換えに伴って発生せず、10’回ま
たはそれ以上の書き換えを期待できる。From this, if such a silicon nitride film is used as the first dielectric film between the semiconductor substrate and the TL, dangling bonds will not occur as a result of rewriting information, and 10' or more You can expect more rewrites.
本発明はかかる良質の窒化珪素膜が1cvo法では作る
ことができることを利用したものである。The present invention utilizes the fact that such a high quality silicon nitride film can be produced by the 1cvo method.
加えてかかる窒化珪素膜に対し損傷を与えないためにそ
の上のTLをも光CVD法で作成するものである。書く
の如く本発明方法によりこれまで不可能であった106
回またはそれ以上の書き換えが初めて可能となった。In addition, in order not to damage the silicon nitride film, the TL on top of it is also formed by photo-CVD. As described above, the method of the present invention has achieved 106 things that were previously impossible.
For the first time, it has become possible to rewrite data twice or more.
前記した実験例において、光CVD用の光源として低圧
水銀灯ではなくエキシマレーザ(波長100〜400n
m) 、アルゴンレーザ、窒素レーザ等を用いてもよい
ことはいうまでもない。In the experimental example described above, an excimer laser (wavelength: 100 to 400 nm) was used as the light source for optical CVD, instead of a low-pressure mercury lamp.
m) It goes without saying that an argon laser, a nitrogen laser, etc. may also be used.
第1図は本発明の絶縁ゲイト型電界効果半導体装置を示
す。
第2図は本発明を用いたCVO装置である。FIG. 1 shows an insulated gate field effect semiconductor device of the present invention. FIG. 2 shows a CVO device using the present invention.
Claims (1)
イト絶縁膜として第1の誘電体膜、電荷捕獲中心層、第
2の誘電体膜を積層して設けるフローティング電荷捕獲
中心層における第1の誘電体膜および電荷捕獲中心層を
光気相反応法により形成することを特徴とする半導体メ
モリ装置作製方法。 2、特許請求の範囲第1項において、半導体基板上にブ
ロッキング層と、該層上にフローティング電荷捕獲中心
層を形成することを特徴とする半導体メモリ装置作製方
法。 3、特許請求の範囲第1項において、第1の誘電体膜は
窒化珪素よりなることを特徴とする半導体メモリ装置作
成方法。 4、特許請求の範囲第1項において、電荷捕獲中心層は
半導体の薄膜またはクラスタよりなる層、または半導体
の不対結合手を含有する層よりなることを特徴とする半
導体メモリ装置作成方法。[Claims] 1. In a floating charge trapping center layer provided by laminating a first dielectric film, a charge trapping center layer, and a second dielectric film as a gate insulating film in an insulated gate field effect semiconductor memory device. A method for manufacturing a semiconductor memory device, comprising forming a first dielectric film and a charge trapping center layer by a photovapor phase reaction method. 2. A method for manufacturing a semiconductor memory device according to claim 1, characterized in that a blocking layer is formed on a semiconductor substrate, and a floating charge trapping center layer is formed on the blocking layer. 3. The method of manufacturing a semiconductor memory device according to claim 1, wherein the first dielectric film is made of silicon nitride. 4. A method for manufacturing a semiconductor memory device according to claim 1, wherein the charge trapping center layer is a layer made of a semiconductor thin film or cluster, or a layer containing semiconductor dangling bonds.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP61073745A JP2747556B2 (en) | 1986-03-31 | 1986-03-31 | Method for manufacturing insulated gate field effect semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61073745A JP2747556B2 (en) | 1986-03-31 | 1986-03-31 | Method for manufacturing insulated gate field effect semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62230059A true JPS62230059A (en) | 1987-10-08 |
JP2747556B2 JP2747556B2 (en) | 1998-05-06 |
Family
ID=13527084
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Application Number | Title | Priority Date | Filing Date |
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JP61073745A Expired - Lifetime JP2747556B2 (en) | 1986-03-31 | 1986-03-31 | Method for manufacturing insulated gate field effect semiconductor memory device |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5357771A (en) * | 1976-11-04 | 1978-05-25 | Sony Corp | Non-volatile memory transistor |
JPS5834978A (en) * | 1981-08-26 | 1983-03-01 | Matsushita Electronics Corp | Semiconductor memory unit |
JPS58182876A (en) * | 1982-04-21 | 1983-10-25 | Oki Electric Ind Co Ltd | Manufacture of semiconductor memory cell |
JPS60245172A (en) * | 1984-05-18 | 1985-12-04 | Semiconductor Energy Lab Co Ltd | Insulated gate type semiconductor device |
-
1986
- 1986-03-31 JP JP61073745A patent/JP2747556B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5357771A (en) * | 1976-11-04 | 1978-05-25 | Sony Corp | Non-volatile memory transistor |
JPS5834978A (en) * | 1981-08-26 | 1983-03-01 | Matsushita Electronics Corp | Semiconductor memory unit |
JPS58182876A (en) * | 1982-04-21 | 1983-10-25 | Oki Electric Ind Co Ltd | Manufacture of semiconductor memory cell |
JPS60245172A (en) * | 1984-05-18 | 1985-12-04 | Semiconductor Energy Lab Co Ltd | Insulated gate type semiconductor device |
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