JPS62228178A - Test system of logic circuit - Google Patents

Abstract

PURPOSE:To enable the testing of a specific function block, in a logic circuit equipped with a register having a state held therein tested as a train of chain- like shift registers, by dividing shift registers into groups to selectively operate the same. CONSTITUTION:The register group of a logical circuit having an addressable scanning clock is formed of a plurality of function blocks 16 divided corresponding to functions and, when a desired block 16 is selected on the basis of an X-Y address, a test scanning chain 18 is formed to the selected block 17 through scanning D-type FE19 and the block 17 is operated corresponding to scanning input as a shift register and the testing of the block 17 is performed on the basis of the quality of scanning output. Therefore, the testing of a specific function block is rapidly performed by a short shift register.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a testing method for logic circuits, and is particularly used to facilitate testing of the logic functions of a circuit.

(Prior art) As a conventional technology for testing general logic circuits (Figure 5), including sequential circuits, data is input/output using a single chain shift register when testing all internal register circuits. There is a method (scan path method, Figure 6). Figure 5,
In Figure 6, 1 is an input, 2 is an output, 4 is a combinational circuit (combinational logic circuit), 5 is a register, 6 is a clock signal, 7 is a selector, 8 is a control signal, 9 is a scan-in, and 10 is a scan act. be.

However, in the scan path technology, in which the internal registers are used as a series of shift registers to input and output data during testing, (a) as the number of registers increases, the length of the test pattern becomes longer than the length of the shift register. (b) Even if a part of the logic circuit's function fails, the entire logic circuit must be scanned; and (c) Even if part of the scan chain fails, the entire logic circuit cannot be scanned. The problem was that it wouldn't work.

(Problems to be Solved by the Invention) In view of the above-mentioned drawbacks (a) and e of the conventional technology, the present invention shortens the test pattern for scanning, and narrows the range of good cine parts through failure analysis. It is possible to test only the corresponding functional blocks, and conversely, even if a failure in one part of the circuit causes a failure in the entire circuit, it is possible to analyze the operation of the part that is operating normally. It also provides the means.

[Structure of the invention]

(Means and effects for solving the problems) While conventional scan technology creates long shift registers during testing, the present invention shortens the shift registers and creates a short shift register for each functional block that is meaningful for the circuit. The shift register chain is divided to create a closed loop (scan ring).

In order to operate these scan rings independently, address numbers are assigned to the rings, and only the clock of a specific scan ring is made to operate according to the address specification. A write/read control circuit is added to a part of the scan ring so that data can be read and written. By doing this, it is possible to specify an external seat address during testing and test a specific functional block.

(Example) An example of the present invention will be described below with reference to the drawings. A block diagram of the configuration of the same embodiment is shown in FIG. First, the circuit is
Although it is expressed by a combinational circuit 4 and a register group 15, in the present invention, an addressable scan clock is used to connect this register group 15 to a plurality of functional blocks 16.
(See Figure 2). K to make it addressable
In FIG. 1, an address input 11, a scan address register 12, an X decoder 14, and a Y decoder 13 are required. A scanning blade 9, 1o is also required. Figure 2 shows the register group 15 in more detail.The registers 19 are grouped together as a functional block, and the scan chain during testing is arranged in a ring 18 so as to be closed within the block.
is created.

Each scan ring has an XY address 17, and by inputting an external address, the scan clock of a selected specific functional block is activated and the contents of the shift register are shifted. At this time, data is sequentially written into the registers through the scan data line 22, and data can be sequentially read from the registers.

FIG. 3 shows a concrete example of one functional block. The scanning DW7 lip 7o tube 19 becomes a ring-shaped shift register as shown in FIG. 3 during testing. D
, C, q, and Tsukasa are data input, clock signal input, register output, and register inversion output during normal operation, respectively, and do not change during testing. On the other hand, S engineering, A, B, i
! ! 0 is the scan input, scan clock (A and B), and scan output during testing, respectively. Only the clock signal 6 selected by the X address 24 and Y address 25 activates a particular scan ring. And when the write signal 20 is 1",
Test data is written into the scan die cliff 70 knob 19 through the scan data line 22. Then, at the same time that the clock shifts the data to the next D-type flip-flop 70, the next data is again written to the D-type 7 flip-flop 191C. In this way, arbitrary data can be set in the registers on the scan ring from the outside. Conversely, when the wyit@1 signal is “0”, the read signal is
When the scan clock is started with a clock of 1", the data contents of all registers can be taken out through the scan data line 22 if the data goes around the scan ring once.

A well-known specific example of the scanning Dfi flip-flop 19 is shown in FIG.

Here, TXG26 is the transfer gate, INV
27 means an inverter.

By implementing the present invention, the total length of the shift register remains basically the same, but when there is a defect in the shift register chain, the speed of removing it becomes much faster. . For example, assume that the total number of registers is N. 0 where n is the average value of the total sum of registers in one block by implementing the present invention. Therefore, if m is the number of blocks, HXm
There is a relationship of =N. In the worst case scenario, if you try to check the contents of a register using the conventional scanning technique, you will need N clocks, whereas Kimoto's invention only requires n clocks.

To give a concrete numerical value, one logic circuit has N=100.
Suppose there are 0 registers and 10 types of functional blocks, then n=10Q, and N/n=10
You can search register contents 10 times faster with . This is very effective when testing circuits in which the cause of a failure must be determined. Also, without having to give a specific example, as is clear from the explanation of the example, even if a part of the functional block fails and stops working, the other normal parts can be used as they are using the test pattern prepared in advance. It is a testability system that can be tested and is resistant to circuit failures.

〔Effect of the invention〕

As explained above, according to the present invention, the test button for scanning can be shortened, and when the range of good cine parts is narrowed by failure analysis, it is possible to test only the corresponding functional blocks, and vice versa. Even if one part of the circuit breaks down, which means the entire circuit is out of order, it is possible to analyze the operation of the part that is operating normally.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIGS.
The figure is a detailed view of a part of the same configuration, FIG. 5 is a diagram generally expressing the logical ports and paths, and FIG. 6 is a BA diagram explaining the conventional test method using scan canvas. 4... Combinational circuit, 12... Scan address register, 13... Y decoder, 14... xf decoder 15... Register group with addressable scan clock, 16... Functional block, 18 ...Scan chain during testing, 19...Type 7 rig flop for scanning, 23...Selector.

Claims (1)

[Claims] A logic circuit that has functional blocks (registers) that hold internal states, and is scan tested by reconnecting the registers as a series of shift registers during testing.
It has an additional circuit that divides part or all of the shift register into groups corresponding to the functions within the circuit, selectively operates these groups as a shift register, and selects an address to operate as a shift register. A logic circuit testing method characterized by comprising a selection means.