JPS6222765U - - Google Patents

Info

Publication number
JPS6222765U
JPS6222765U JP11300785U JP11300785U JPS6222765U JP S6222765 U JPS6222765 U JP S6222765U JP 11300785 U JP11300785 U JP 11300785U JP 11300785 U JP11300785 U JP 11300785U JP S6222765 U JPS6222765 U JP S6222765U
Authority
JP
Japan
Prior art keywords
digital
circuit
emphasis
converted
recording device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11300785U
Other languages
Japanese (ja)
Other versions
JPH0351812Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11300785U priority Critical patent/JPH0351812Y2/ja
Publication of JPS6222765U publication Critical patent/JPS6222765U/ja
Application granted granted Critical
Publication of JPH0351812Y2 publication Critical patent/JPH0351812Y2/ja
Expired legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案によるデイジタル録音装置の一
実施例を示すブロツク図、第2図は従来のデイジ
タル録音装置の一例を示すブロツク図である。 1……ローパスフイルタ、2……プリエンフア
シス回路、3……サンプルホールド回路、4……
A/D変換器、5……デイジタルデイエンフアシ
ス回路、6……信号処理回路。
FIG. 1 is a block diagram showing an embodiment of a digital recording device according to the present invention, and FIG. 2 is a block diagram showing an example of a conventional digital recording device. 1...Low pass filter, 2...Pre-emphasis circuit, 3...Sample hold circuit, 4...
A/D converter, 5... digital de-emphasis circuit, 6... signal processing circuit.

Claims (1)

【実用新案登録請求の範囲】 アナログ信号を入力してプリエンフアシス回路
によりプリエンフアシスを施し、サンプルホール
ド回路により標本化し、A/D変換器によりA/
D変換したデイジタル信号を信号処理回路により
処理して録音するデイジタル録音装置において、 前記A/D変換器の出力側に、A/D変換した
デイジタル信号にデイエンフアシスを施すデイジ
タルデイエンフアシス回路を有することを特徴と
するデイジタル録音装置。
[Claims for Utility Model Registration] An analog signal is input, pre-emphasized by a pre-emphasis circuit, sampled by a sample-hold circuit, and A/D converted by an A/D converter.
A digital recording device that processes and records a D-converted digital signal by a signal processing circuit, comprising a digital de-emphasis circuit that performs de-emphasis on the A/D-converted digital signal on the output side of the A/D converter. A digital recording device characterized by:
JP11300785U 1985-07-25 1985-07-25 Expired JPH0351812Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11300785U JPH0351812Y2 (en) 1985-07-25 1985-07-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11300785U JPH0351812Y2 (en) 1985-07-25 1985-07-25

Publications (2)

Publication Number Publication Date
JPS6222765U true JPS6222765U (en) 1987-02-12
JPH0351812Y2 JPH0351812Y2 (en) 1991-11-07

Family

ID=30994400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11300785U Expired JPH0351812Y2 (en) 1985-07-25 1985-07-25

Country Status (1)

Country Link
JP (1) JPH0351812Y2 (en)

Also Published As

Publication number Publication date
JPH0351812Y2 (en) 1991-11-07

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