JPS62227196A - Liquid crystal driver - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a liquid crystal drive device used in a display section of electronic equipment such as a calculator, a personal computer, and various types of measuring instruments.

BACKGROUND ART A multiplex method has conventionally been adopted as an effective method for driving the liquid crystal display bag g1 (hereinafter referred to as LED) without increasing the number of drive signal lines as much as possible. In order to obtain good display quality, this method requires
There is a method of increasing the bias voltage by 4 to correctly set the effective values V on and V off of the applied voltage at the selection point (liquid crystal activation part) and half-selection point (inactivation part). requires a voltage with three or more values (in addition to the on/off levels of the power supply voltage, the intermediate level is one or more values).

For example, when using the above drive method for a battery-powered calculator,
It is driven with 1/3 duty and 1/3 bias or 1/4 duty and 1/3 bias with two intermediate levels, and in solar battery powered calculators, the power supply voltage from the solar cell and this power supply voltage are boosted. It was driven at 1/3 deity and 1/2 bias using a 3-value voltage (the intermediate level is 1 value) with the voltage doubled in the circuit.

By the way, in the case of the above-mentioned battery-powered calculator, the intermediate voltage is obtained by dividing it by the reader resistor, so although there is a good chance that the current consumption increases, there is a big problem with the LCD drive circuit. i! The circuit load of the leader resistor itself in an integrated circuit (hereinafter referred to as LSI) is small. On the other hand, in the case of a solar battery-powered calculator, the set current is less than 1/2 to 1/3 of the Briegmi current in the case of a battery-powered calculator, so an intermediate level voltage is obtained by the leader resistor. method cannot be adopted. Therefore, in solar-powered calculators, two capacitors were mounted outside the LSI to form a booster circuit, which formed the power supply.

Therefore, a method called a pulse control method has been developed to drive the LCD with binary values (i.e., a single power supply) on a duty basis without using a booster circuit like the above-mentioned drive method that requires a nosious voltage. has been done.

The waveforms in FIGS. 15(1) to 15(5) show this method in the case of 1/2 duty drive.
The first example shows the case of 1/3 duty drive.
6(1) to FIG. 16(7).

In the 1/2 duty drive shown in Figure 15, the voltages H1 and H2 applied to the two common electrodes are as shown in Figure 15 (1).
The waveform shown in FIG. 15 (2) is given, and in the waveform of the applied voltage H1, the section ri11h 1 is the selected section and the section 112 is the half-selected section, whereas in the waveform of the applied voltage H2, the section 112 is selected. section, section h1
is given as a half-selected interval. The applied voltage Seg(0
1) When the waveform (the waveform is shown in Fig. 15 (3)) becomes a waveform that can activate the liquid crystal, the applied voltage between the segment electrode and the common electrode (Fig. 15 (4) and Fig. 15 (5) shows the waveform) takes the effective value of Von, and conversely, when the voltage Seg (01) applied to the segment electrode t in the selected section has a waveform that deactivates the liquid crystal, the segment electrode - The voltage applied between the common electrodes takes an effective value Voff. Similarly, 1/
In the fjS16 diagram showing the waveform of 3-duty drive, section h1 is the selected section of the waveform of the applied voltage H1 for the common electrode, section 1+2 is the selected section of the waveform of the applied voltage 1 (2) for the common electrode, and section 113 is the selected section of the waveform of the applied voltage H1 for the common electrode. A selected section of the waveform of the applied voltage H3 is shown.

The operating margin α that represents the display quality in this method, that is, Vo / Vo
→1.3V Vorf= E −0,75V ri α
=Von/Vofr=,/“-3
"-"=1,73, and in the case of 1/3 duty drive, Von-E -1,22V, so ff=Von/Voff=5+1. 4
It is 1. Similarly, a waveform for 1/4 duty driving can be created, but the operating mannon α in this case has a small value of 1.29.

The contrast, that is, the display quality of an LCD is better as the operating margin α is larger, and in a calculator, it is usually +7=1.
Those with a score of 73 or higher are adopted.

On the other hand, in LCD duty driving, the larger the value of the duty denominator, for example, 1/2
/3. 1/4 requires less signal amount to drive the same LCD display element than 1/3, so
If the same display quality can be obtained, it is desirable to use duty drive with a denominator value as large as possible.

However, in the conventional pulse control method, as mentioned above, when used in a calculator, the value of the operating margin a is limited from the viewpoint of display quality (hunto last). Due to the duty limit, 1/3 duty could not be adopted.

On the other hand, the 1/3 duty, 1/2 bias LCD drive, which is commonly used in the past for solar-powered calculators, requires a total of 27 drive signal lines to drive an 8-digit LCD. If we try to perform this with 1/2 duty drive using the conventional pulse control method described above, 36 or more drive signal lines will be required, and the chip size of the LSI that makes up the drive circuit and the number of pins of the package will increase. This has the problem of increasing the number of units, leading to an increase in costs.

In particular, film carriers (T A B ; T ape A
LSI with auto-+aaLed Bonding)
When making a package, since the cost of a film made of lath epoxy resin accounts for a large proportion of the LSI manufacturing cost, there is a desire to keep the amount of film used as small as possible. The film used in this film carrier LSI has various terminals 1a and 1b obtained by etching the body foil as shown in Figure 1317.
, 1 c, 1 d are formed on the surface, while 1 of the LSI
An opening 3 through which the LSI chip is exposed is formed in each section L1 of the film 2 corresponding to each piece. Further, together with the terminals 1a, 1b, 1c, and ld, connection lines of the body foil connected to these terminals and extending beyond the periphery of the opening 3 are also formed at the same time. Then, as shown in FIG. 1118, the film 2 is stretched over the substrate 5 with the LSI chip 4 facing the opening 3, and each connection line 6 extending beyond the periphery of the opening 3 is connected by wire bonding. By connecting the LSI chips 41 (an LSI pancage is formed from the two). In the conventional film carrier LSI arrangement example shown in Figure tjt117, the terminals 1a for the LCD and numeric keypad, etc. are connected to the longitudinal sides of the film 2. The width of the LSI always matches the width of the film 2 (actually, the length is determined as the number of holes for the sprocket and the edge hole 2a). If the terminal pitch that can be arranged within a section of 1 inch is, for example, 0.9a++a, it would take a film length of 27.9ma+ (6 pitch holes 2&) to arrange 31 terminals for the drive signal line of the LCD. ) is required, and this length corresponds to 11 LSs. In other words,
An increase in the number of terminals causes the pitch size of the LSI to become thicker.

FIG. 13 shows an electrode connection diagram of the Japanese-shaped segment liquid crystal display element 7 which is applied when 1/4 duty driving is attempted using the conventional pulse control method. In this case, in order to display each display pattern shown in FIG. 14(1) to FIG. 14(10), segment electrodes 81 to S8 are required.
The drive signals ai and bi for the two groups must have the combination patterns shown in Table 1. The X mark in the table means that any value of 0.1 is acceptable. That is, the total number of types of patterns of the segment electrode drive signals ai and bi is 11 types as shown in Table 2.

(Margins below) ptSl Table The purpose of the present invention is to solve the problems in the above-mentioned conventional example,
A liquid crystal drive device that eliminates the need for external voltage circuits to apply bias voltages, and greatly reduces the number of drive signal lines, allowing for reductions in LSI chip size, number of bins, cost reductions, and miniaturization of the entire device. The goal is to provide the following.

Means for Solving the Problems The liquid crystal driving device of the present invention groups a plurality of segment electrodes, and the grouped segment electrodes are connected in common for each group and are opposed to the segment electrodes via the liquid crystal. A plurality of common electrodes are provided, and the common electrodes are also grouped, and the grouped common electrodes are commonly connected for each group so that each segment electrode group and each common electrode group have a duty of 1/n. A liquid crystal driving device that is driven by applying a binary voltage, includes a ring counter including 11+m cells, a flip-flop that derives a signal for each sequential count of the ring counter, and outputs from the ring counter and the flip-flop. a logic circuit that receives a pulse having a waveform of one level and sequentially applies a pulse having a waveform of one level to each group of common electrodes for each frame, and simultaneously applies a waveform of the other level to all groups of common electrodes. The present invention is characterized in that it includes a segment electrode driving electronic circuit that provides a signal to each group of segment electrodes so that a predetermined character can be obtained.

In the drive signal given to the common electrode from the operational logic circuit, within one frame interval, the level of the pulse sequentially given to each group from the common electrode and the waveform of the other level are common to each group. 'Due to the existence of the section simultaneously applied to the Ki poles, the voltage applied to the liquid crystal as a relative level difference between the waveform applied to the segment electrodes from the segment electrode driving electronic circuit and the waveform applied to the common electrode from the above logic circuit. When viewed over the entire frame, if the waveform applied to the segment electrodes corresponds to the waveform that activates the liquid crystal, it will have a high enough effective value for display, and if the waveform applied to the segment electrodes corresponds to the waveform that activates the liquid crystal. If it corresponds to the waveform to be activated, the effective value will be low enough to be hidden.

Embodiment m1 FIG. 1 shows a circuit diagram of a liquid crystal driving device of the present invention, and FIG. 2 shows an electrode connection diagram of a segment liquid crystal display element.

This example is? The sun-shaped segment liquid crystal display element 10 shown in Figure tS2 is driven with a 1/4 duty and binary voltage, and thereby
) shows an example of a configuration for displaying each display pattern. Of the liquid crystal display element 10, a first segment electrode S1 extends in the horizontal direction above the display area, and a second segment electrode S extends downward from the right end of the first segment electrode S1.
A first common electrode C1 is arranged opposite to the first common electrode C1.

Further, the second common electrode C2 is arranged to face the third segment electrode S3 extending downward from the lower end of the second segment electrode S2 and the fifth segment electrode S5 extending downward from the left end of the first segment electrode S1. There is. Also, the second
The lower end of segment electrode S2 and Pt55 segment electrode S
A third common electrode C3 is disposed opposite the seventh segment electrode S7 and the dot segment electrode S8 extending leftward across the lower end of the ms upper segment electrode S5, and further includes 16 segments extending downward from the lower end of the ms upper segment electrode S5. Electrode S
6 and a fourth segment electrode ff1s4 extending in the left-lateral direction from the lower end of the third segment electrode S3. Moreover, the f12 segment electrode S2, the third segment electrode S3, the dot segment electrode S8, and the fourth segment electrode S4 are connected in common and given one segment drive signal ai, while the first segment electrode S1, the fifth segment electrode The segment electrode S5 and the sixth segment electrode $6 are also separately connected in common,
It is configured to be provided with another segment drive signal bi. Then, by the combination of the common drive signal H1-H=1, which will be described later, and the segment drive signal ai+bi, which is applied to each of the common electrodes C1 to C4, the segment drive signal ai+bi is applied to the above-mentioned Japanese-shaped segment liquid crystal display element PIO as shown in ff13 (1).
- It is configured to display each display pattern shown in FIG. 3 (10). Segment drive signals ai, b corresponding to each display pattern of FIG. 3(1) to FIG. 3(10)
Table 3 shows the matching pattern of i. The X mark in the same display means that either 0 or 1 may be used.

In the circuit shown in FIG.
The ring counter 11 that outputs 1 to I+5 has five stages of flip-flops 12. ~12. The tarock signal φf obtained from the frequency divider 13b of the oscillation circuit section 13 is used as the shift pulse. The oscillation circuit section 13 is composed of a clock generator 13a that outputs clock signals φ1 and φ2 of the original oscillation frequency, and a frequency divider 13b that receives the clock signal φ2 and divides it into a clock signal φr of a predetermined frequency. has been done. Ring counter 1 above
The timing signal h1 outputted from the first stage of the T flip-flop 14 is received by the T flip-flop 14, and the inverted output FR of the T flip-flop 14 is received by the common driver 15 of the next stage. The common driver 15 is connected to each common electrode 01 of the liquid crystal display element 10 shown in the fjS2 diagram.
A circuit for providing common drive signals H1 to H4 to C4, which receives timing signals B2 to B115 output from the second and subsequent stages of the ring counter 11 at one input terminal, respectively. Two EX-OR dates 16. ~16. and these dates 161~1G,
The other input terminal of
4 inverted outputs FR are input, and the respective outputs are obtained as drive signals H1 to H4 for the respective common electrodes 01 to 04.

The inverted output FR of the T flip-flop 14 is logically ORed with the output from the memory unit 17 that generates the signal Q corresponding to each display pattern created by the liquid crystal display element 10.
-OR date 18, and the output of date 18 is input to the next stage segment shift register 19.

The memory section 17 includes a data address debug 17a that receives 5 bits of display data (DP, and a main ROM 17b which receives other address signals ai/bi, b1-115 and outputs a signal Q of a display pattern corresponding to the address signal. Each of the segment shift registers has a capacity of 17 bits, and is configured to operate using the clock signal φ1 outputted from the clock generator 13a as a shift pulse. A segment latch circuit 21 that receives the stored contents as a parallel signal is connected to this segment shift register 19, and the contents held in the latch circuit 21, that is, the segment drive signal, are outputted by the next stage segment driver 22, and the ttS2 The voltage is applied to each segment electrode group of the liquid crystal display element 10 shown in the figure.

Next, the operation of this device will be explained using the time charts of FIGS. 4 and 5.

The two clock signals φ1 and φ2 of the original oscillation frequency output from the clock generator 13a are out of phase with each other by 180 degrees as shown in FIG. 5(1) and FIG. 5(2), and are output from the frequency divider 13b. From FIG. 4 (1), the frequency of the clock signal φ2 is divided, that is, it is synchronized with the clock signal φ2.
A clock signal φr shown in is output. Therefore, the output of each stage of the ring counter 11 that receives this clock 7713 φr as a shift pulse, that is, the timing signal 1 + 1 - 1 + 5 (m 4 Figure (2) - Figure 4 (6)
(27f) 2 & (shape shown) and timing signal 11
Common drive signals H1 to H4 created based on signals 1 to b5
(The waveforms are shown in FIG. 4(8) to FIG. 4(11)) are also synchronized with the clock signal φr. The output F of the T flip-flop 14 is repeatedly inverted at the time the timing signal 111 falls, as shown in FIG. 4 (7), providing timing for an interval corresponding to one frame.

Drive signals H1 to H4 applied to each common electrode C1 to C4
The waveform is the output of each stage after the second stage of the ring counter 11, that is, the timing signal h2~! 15 and T7 lip 7
It is given as a signal obtained by exclusive ORing with the inverted output FR of the amplifier 14.

On the other hand, in the memory unit 17 for display pattern generation, data is input from the display data register 20 to the data address decoder 17a as shown in the truth table shown in Table 4 below (Bnr in the table means blank). 5 bit data (DP%X4-XI) and ebit data (ai/b1.111-11
Data accessed using 5) as an address signal is stored.

Table 4 For example, input data Xin from the display data register 20 to the data address decoder 17a is "G 451
This relates to the numerical display of 2,8J, and f indicates each output waveform in the interval of the timing signal b 1 at this time.
In the time chart of the jSs diagram, ai/bi=
At the timing of r I J (that is, the ai side of the truth table is accessed), the drive signal ai given to one segment electrode group of the first digit liquid crystal display element 10 is converted into a shift pulse by the segment shift register 19. It is sampled in synchronization with φ- (synchronized with clock signal φ1). For example, if the display pattern of the first digit is "8", from Table 4, Xi++ = 8, DP (signal regarding the presence or absence of cut) = "0", and the value of al-bl is rOJ, so rOJ is obtained as the output Q from the memory section 17. If the recurrent output FR of the T7 rip 70 tip t in this period of the timing signal 111 is rOJ, the first stage of the segment shift register 19 is rOJ.
is input. In the next interval ui/bi=ro j (i.e. the bi side of the truth table is accessed),
Since X1n=8, DP=[OJ, and the timing signal is hl, rlJ is accessed from Table 4, and "1" is input to the first stage of the segment shift register 19 at the timing of the next shift pulse φ-. The next memory content is 1bi
t shifted to the left.

Data address decoder 1 from display data register 20
Assuming that the content of the display pattern of the second digit (a2-b2) input next to 7a is "2.", similarly, from the main ROM 17b, ai/
bi” r I J (aigA), X in= 2, D
P = rl J, the rOJ corresponding to h 1 is then ai/bi = ro J (bi side), X in
= 2, D P = rl J, “0” corresponding to 111
is accessed, and similarly a3, b3...bl
, a8, b8, S and 8 digits and symbol 4't78 are sequentially accessed, and all 171+i of one shift register are accessed sequentially.
L is filled in.

On the other hand, the contents of the shift register 19 are the pulse signal φ1 synchronized with the falling edge of the timing signal b1-hS.
(The waveform is shown in FIG. 5 (7)), the signal is transmitted to the latch circuit 21 as a parallel 4B signal.

The transferred segment drive signals are sent via each buffer 23 of the segment driver 22 to al , bl , . . .
.

It is output from the a8, l+8, and S terminals and applied to the corresponding segment electrode group of the liquid crystal display element 10. That is, during the timing signal h1, the shift register 19
The display contents accumulated in the next timing signal 112
During this period, the segment driver 22 outputs the signal. This timing shift caused by the shift register 19 and latch circuit 21 is corrected by the common driver 15. That is, the common drive signal H1 is generated in the interval of the timing signal 112, the drive signal H2 is generated in the interval of the timing signal 113, the drive gJ signal H3 is generated in the interval of the timing signal II4, and the drive signal H4 is generated in the interval of the timing signal 115. Corrected by

Similarly to the above, in the period of the timing signal 112, the data Xin and D are sent to the data address decoder 17a.
P and input ai/bi, l+ to main ROM17b
2, the corresponding data in Table 4 is sequentially input from the memory section 17 to the shift register 19, and the displayed contents are transferred to the latch circuit by the pulse signal φ7 synchronized with the falling edge of the timing signal II2. 21 and displayed.

Thereafter, similar operations are performed up to the timing signal b5, and the process returns to the timing signal h1 section again.

After this, the operation is the same as the previous one until a predetermined output Q is obtained from the memory section 17, but since the inverted output FR of the T flip-flop 14 is "1" during the next one frame, the memory section The output Q from 17 is the EX-OR of the next stage.
It is inverted by date 18 and input to shift register 19.

On the other hand, in this one frame, the waveforms of the common drive signals H1 to H4 obtained from the common driver 15 are also inverted, so
The relationship between the applied voltages applied to the liquid crystal by the segment drive signal and the common drive signal is the same as in the case of the previous 17 frames.

Pt5a Figure (1) to Figure 6 (4) are respective waveform diagrams of the common drive signals H1 to H4 obtained by the above circuit, and i
ll'? Figures 7 (1) to 7 (12) show the steps for obtaining each display pattern using the common drive signals H1 to H4.
The waveforms of the segment drive signals ai and bi of 2ffi are shown, and the relationships between these waveforms and the common drive signals H1 to H4 are as shown in Table 5.

Table 5 Among these segment drive signals ai and bi, those corresponding to each display pattern in FIG. 3 are as shown in Table 6 below.
It is a kind.

6th fi The above common drive signals H1 to H4 and segment drive signal a
Depending on the combination of im and bi, the effective value of the voltage applied to the liquid crystal becomes, for example, as shown by diagonal lines in Fig. fj4B (1) to Fig. 8 (4). In the figure, the solid line represents the waveform of the common drive signal, and the broken line represents the segment (ffi!). I! In this example showing the waveforms of the II signals, a waveform (0011) in FIG. 7(2) is shown as the segment drive signal. The effective value of the applied voltage at this time is E=
Since the voltage is 1.5 V, the operating margin α is V on/V off=v/Ts 1.73, which is the same value as the conventional example of 1/2 duty drive shown in FIG. On the other hand, the effective value of the applied voltage is about 10% lower than that of the conventional example shown in FIG.
This can be compensated for by appropriately selecting the threshold value.

Note that the waveforms of Xin and DP in FIG. 5(9) represent the timing of data switching, and are synchronized with the clock signal φ2 of the original oscillation frequency of the clock generator 13a. The terminal S shown in Figure PIIJ1 is used to drive characters such as symbol digits other than the sun-shaped segment, and can be used within the range of waveform combinations of segment drive signals shown in Figure 7.

In this drive method, the waveforms of the common drive signals H1 to H4 do not have timing sections such as selection sections and half-selection sections as seen in the conventional waveforms shown in FIGS. 15 and 16. Throughout the entire system, the effective value of the voltage applied to the liquid crystal is V
It can be divided into n and Vo[ corresponding to the non-activated portion. In addition, despite the 1/4 duty drive, a timing of 51+iL can be obtained, and the existence of a period T in which there is no sequential pulse for each common electrode in Fig. 6 makes the above effective value valid. This means that it functions as an interval for adjusting to a certain value.

In addition, with this drive method, a sufficient operating manon α can be obtained even if the duty is set to 1/4 as in the example, so when used for a calculator with an 8-digit display, for example, the number of drive signal lines is 21. This can reduce the number of drives by 15 (less than 60%) compared to the case of 1/2 duty drive. This reduces the number of pads on the LSI chip and also reduces the chip size. Furthermore, since the number of pins on the package can be reduced, the cost of LSI can be reduced, and electronic devices can be made smaller. In particular, when making an LSI package using a film carrier, the terminal arrangement can be improved as described below, thereby reducing the amount of film used and contributing to lower material costs. That is, in this drive system, in the case of the above-mentioned 8-digit display, the number of terminals of the entire LSI including the drive signal line is 26, so the terminals arranged in the 35mu film 2 shown in the Pt517 diagram explained in the conventional example are 26. If the pitch of 1a is 0.91, the film length required for 11 LS is 23.4-m, which is compared to the conventional example mentioned above (27.9+*a+ film iL1 is required for 11 LS). It is sufficiently short (the effective length W of the film 2 in the width direction is 25.4 m.
Since the terminals 1a are n+, it is possible to arrange the terminals 1a in the width direction of the film 2 as shown in FIG. Therefore, the electric current r normally arranged in the width direction of the film 2
Even considering A terminals 1b, lc, component mounting pads, etc.
By adopting the above terminal arrangement method, the length L2 for 11 LS can be used as the number of pitch holes 2a for 2 to 3 holes (
9,5-14. ．． 25 + am). As a result, the number of pitches in the film 2 can be halved compared to the conventional example, resulting in significant material savings and cost reductions.

In addition, in this drive method, Fig. 7 (1) to Fig. 7 (12)
As can be seen from the segment drive signal shown in ttsG
Common drive signals H1 to +(4) in Figures (1) to (4)
All patterns (16 types) of combinations with are not included, and any one of the common drive signals H1 to H4 is on,
There are only 12 patterns excluding the 4 patterns in which the other 3 are off. On the other hand, the types of segment drive signals when displaying each pattern from O to 9 (including dots) on the conventional Japanese-shaped segment liquid crystal display element 7 of the electrode connection method shown in Figure Pt513 are shown in Table 2. As mentioned earlier, there are 11 possible combinations, and the patterns in Table 2 above include the pattern (1000) that is not shown in Figure 7, so the liquid crystal display element 7 using this conventional wiring method can be driven as is. cannot be used in the method. Therefore, in this embodiment, the liquid crystal display element 10 of the wire connection method shown in FIG. 2 is adopted as one that can be adapted to the second driving method. The details of the connection are as described above. Although the liquid crystal display element 10 of the mouth-shaped segment is shown here as an example, the present invention can be similarly applied to the display of other characters.

In the above embodiment, the case of 1/4 duty/binary voltage drive is shown, but it can be realized in the same way in the case of 1/3 duty/binary voltage drive, and the common drive signal H1 in that case is The waveform of ~H3 is the 91st jJ (1
) to FIG. 9(3), and the segment drive signals for this are, for example, FIG. 1.0(1) to 1st
It can be given as the waveform shown in Figure 0 (8). The relationship between the waveform and the common drive signals H1 to I(3) is as shown in Table 7.

Table 7 illustrates the segment drive signal (011) in this case,
The effective value of the voltage applied to the liquid crystal is shown in the shaded area in FIG. In FIG. 11 (1) to FIG. 11 (3),
The solid line shows the waveform of the common drive signal, and the broken line shows the waveform of the segment drive signal. As is clear from the figure, when E=1.5V in the figure, the effective value of the applied voltage corresponding to the activated part of the liquid crystal is the effective value of the applied voltage corresponding to the non-activated part, and in this case, It can be seen that the operating margin α is V on/V off = 7' = F1.73, and sufficient display quality is ensured.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, but can also be similarly applied to 1/n duty/binary voltage driving in which one frame is generally time-divided into 1/1.

Effects of the Invention As described above, according to the liquid crystal drive device of the present invention, even if the duty denominator increases to some extent, the operating margin does not decrease significantly, so the number of drive signal lines can be significantly reduced while maintaining good display quality. The number of terminals in the LSI can be reduced, the package can be made smaller, and costs can be reduced.

In addition, since it is possible to drive the LCD with a single power supply, there is no need for a step-up circuit like in conventional bias systems, and the drive voltage can be kept low, reducing power consumption in LSIs and LCDs, reducing the size of power supplies, In addition to reducing costs, it is also possible to simplify the internal circuit of the LSI.
Effects such as chip size reduction and cost reduction are further promoted.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the liquid crystal driving device of the present invention, and FIG. 2 is an electrode connection diagram of the liquid crystal display element 10 of FIG.
3 is a diagram of each display pattern by the liquid crystal display element 10 of this embodiment, FIG. 4 and f:A5 are a time chart of the above circuit, respectively, FIG. 6 is a waveform diagram of the common drive signal of the embodiment, and FIG. 7 8 is a waveform diagram showing an example of the applied voltage in the embodiment. FIG. 9 is a waveform diagram of the common drive signal when the present invention is applied to 173 duty drive. FIG. 10 is a waveform diagram of the segment drive signal, FIG. 11 is a waveform diagram showing an example of the effective value of the applied voltage, and FIG. 12 is an explanatory diagram showing an example of the terminal arrangement of a film carrier LSI to which the present invention is applied. ,
FIG. 13 is a diagram showing the electrode connection method of a sun-shaped segment liquid crystal display element used when performing 1/4 duty drive in the conventional method, and FIG. 14 is a diagram of each display pattern by the liquid crystal display element. Figure 15 is a waveform diagram showing the effective values of the drive signal and applied voltage when performing 1/2 duty drive using the conventional method.
17 is an explanatory diagram showing an example of the terminal arrangement of the film carrier 177LSI when the conventional method is applied; FIG. 1 is a vertical cross-sectional view schematically showing the mounting of a film carrier LSI. 11...Ring counter, 14...T7 limp 70
・Pump, 15...Common driver, 17...Memory section, 18...EX-〇R date, 19...Segment shift recorder, 20...Display data recorder,
21...Launch circuit for segment F, 22...Segment driver agent patent attorney number of strokes Keiichi (1), :. (3) Yo. (4) t-; (5)':I. (6) 6゜(7)Iyu(8)B. (9) Yu (io) (-1゜Figure 3Figure 5Figure 7 (2) -Day-!Shi- (3) -Go 1f-Shi''Figure 9Figure 10Figure 11Figure 13 (6), 5. (3) - Shego No. 14
Figure 15 Figure 16 Figure 18 Figure 17

Claims (1)

[Claims] A plurality of segment electrodes are grouped, and the grouped segment electrodes are connected in common for each group, and a plurality of common electrodes are provided opposite to the segment electrodes via a liquid crystal, and the common electrodes are connected in common to each group. are also grouped, and the grouped common electrodes are commonly connected for each group, and a liquid crystal drive is performed by applying a binary voltage of 1/n duty to each segment electrode group and each common electrode group. The device includes a ring counter including n+m cells, a flip-flop that derives a signal for each sequential count of the ring counter, and a common electrode that receives outputs from the ring counter and flip-flop for each frame. a logic circuit that sequentially applies a pulse having a waveform of one level to each group and simultaneously applies a waveform of the other level to all common electrode groups, A liquid crystal driving device comprising a segment electrode driving electronic circuit that provides a signal to obtain a character.