JPS61208094A - Integrated circuit for driving dot display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an integrated circuit for driving a dot matrix display device, and more particularly to an integrated circuit for driving a dot matrix display that serially captures display information.

(b) Conventional technology in general: For example, when displaying characters or figures on a dot matrix display device using liquid crystal, a large number of X-thin electrodes are sequentially selectively driven based on a well-known liquid crystal dynamic driving method. In the selected state, drive signals for selection or non-selection are applied to a large number of Y thin electrodes. Here, since the signal for driving the large number of Y thin electrodes is created based on display information indicating lighting and non-lighting of a large number of dots connected to the currently selected X thin electrode, the Y thin electrodes A memory circuit is provided for supplying the display information to the circuit driving the electrodes.

Conventionally, a memory circuit for storing display information was developed by Japanese Patent Publication No. 59-1
As shown in Japanese Patent No. 1916, a latch circuit or a parallel output shift register having a bit output equal to the number of Y moving electrodes is used, and the contents of the memory circuit are written every time the selection state of the X thin electrodes changes. To change the following xm
A shift register is provided for receiving and storing new display information from the outside until the m pole is selected.

Then, by integrating the drive circuit for the Y thin electrode, the memory circuit for storing display information, the shift register for storing display information for rewriting, etc., an IC dedicated to driving the Y@electrode of the dot matrix display device was realized. has been done.

However, when driving a large number of Y thin electrodes, all circuits must be operated in order to shift all display information, which has the disadvantage of increased power consumption.

Therefore, the display information that is applied serially is input in m bits, for example every 4 pits, using a shift register, etc.
An integrated circuit for driving a dot display has been developed which stores bit display information in a storage circuit all at once.

(/J Problems to be Solved by the Invention In an integrated circuit that serially inputs m bits, for example, 4 bits, only 4 bits need to be shifted during serial input, which reduces power consumption. Although there is an advantage in reducing
Since input is made at a rate of 4 bits, when all 40 times the display information is input, if it is not transferred to the storage circuit, 5 incorrect display information will be displayed. Therefore, there is an inconvenience that serial transfer of display information cannot be stopped at a number other than 40 times.

B) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and is a serial latch circuit consisting of m latch circuits in which display information applied serially is commonly applied to the input. - Based on the parallel conversion circuit and the synchronization signal applied in synchronization with the display information,
A control circuit that sequentially outputs m pulses for controlling the latch operations of m latch circuits is provided, and display information can be input without being limited to multiples of m.

(E) Function According to the present invention, the m latch circuits of the serial-parallel conversion circuit are activated by pulses sequentially output from the control circuit every time a synchronization signal synchronized with display information is applied.
Only the latch circuit to which that pulse is applied stores display information. Therefore, the display information input to the serial-parallel converter circuit is not shifted, and each latch circuit always stores predetermined display information, so even if all m pieces of display information are not input, the storage circuit Transfer to is possible.

(f) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.
has outputs Y1 to Y8o capable of driving 80 Y thin electrodes of a display device, and receives four externally applied voltages V+ -Vt, Vs, and Vt from a memory circuit (2). It selects based on 80 pieces of display information, and sends out the output Y l """ Y a OK. The memory circuit (2) indicates lighting and non-lighting of dots corresponding to each output Y, -Y, . It stores display information and supplies it to the liquid crystal drive circuit (11), and is composed of, for example, 80 latch circuits.The storage operation of the storage circuit (2) is performed by applying a signal to an external terminal (3). When the control signal LOAD falls, the storage circuit (4) inputs and stores 80 pieces of accumulated display information at once.The storage circuit (4) is controlled by the serial-to-parallel conversion circuit ( 5) is stored sequentially at a 4-bit rate; for example, 8
Consists of 0 latch circuits. In addition, the latch circuit
The latch operation of ~LAG is controlled by the latch clock OI~Oto output from the control circuit (5), and the latch operation of latch circuits L1~L.

is latch clock 1, latch circuit, ~L is latch clock 02, ... latch circuit L? 7~L,.

is a latch clock, which is sequentially controlled every 4 bits such as 12o+. Serial-parallel conversion circuit (5)
is composed of four latch circuits (607) (81 (91), and the external terminal αOj to which display information DATA is serially applied to the input of each latch circuit (61 (71 (8 + (91)) is commonly used. connected. Also, the latch circuit (
The output Q of 6) is the latch circuit of the storage circuit (4),
L, , L,...L? ? , the latch circuit (7
) output Q is the launch circuit Lx, L of the storage circuit (4).
a,...Lea, the output Q of the latch circuit (8) is the latch circuit Ls, L7...L of the storage circuit (4).
The output Q of the latch circuit (9) is connected to the latch circuit L4, Ls...L, of the storage circuit (4). connected to. Further, the clock input card of the latch circuit (6) has a clock pulse CL, the clock input card of the latch circuit (7) has a clock pulse CL, and the clock input card of the latch circuit (8) has a clock pulse CL, However, the clock pulse CL is input to the clock input circuit of the latch circuit (9).
4 is applied from the control circuit αυ. The control circuit aυ is
The control signal LOAD is applied to the set terminal S, and the enable flip-flop α2+C or below is E-FF, which stores the operable state at the rising edge of the control signal LOAD, and E-F.
When E-FFα2 is set, the synchronizing signal CP applied to the external terminal in synchronization with the display information DATA is controlled by the output Q of F(13).
AND game H31 outputs as LOAD and control signal LOAD.
A quaternary counter α that counts clock pulses CLK and an input clock that generates clock pulses CL, ~CL, which are supplied to the serial-to-parallel conversion circuit (5) based on the output of the quaternary counter Q41. Generation decoder α9, output of quaternary counter I, and control signal L
The output of the 20-decimal counter aη to which OAD is applied via the OR gate a61 and the output of the 20-decimal counter (171) are input, and the latch clock U~02 is input based on the clock pulse CLK.
decoder u8 that creates o, and when control signal LOAD is applied, a delay of half lock of synchronization signal CP and 20
It consists of a delay circuit 9 for resetting the advance kakunta αn.

In this control circuit (11), when the synchronization signal CP synchronized with the display information DATA applied serially is counted by the quaternary counter α4, the input clock generation lever l-(m
Haku C! y Cupas CL, , CL2, CLs
Output %CL4 in order. Therefore, display information DAT
A is stored in the order of latch circuit f61 (71 (81 (97). Also, the pulse output when the quaternary counter α counts four synchronization signals CP is stored in the 20-decimal counter C1.
71, one of the latch clocks 01 to 02o is sequentially outputted from the decoder αa, and the latch clocks 01 to 02o are sequentially output from the decoder αa. 4 of storage circuit (4) controlled by
The display information DATA stored in the serial-parallel conversion circuit (5) is transferred and stored in the latch circuits. Furthermore,
When the 20-decimal counter aη counts 20 pulses, the carry CAR is applied to the reset R of the E-FFC 121 and the AND gate 2. E-FFα2 reset by the carry CAR cuts off the synchronizing signal CP by the AND game Q31, and stops the operation of the quaternary counter I. Furthermore, the AND gate (2) to which the carry CAR is applied outputs the synchronization signal CP from the external terminal l2II as the synchronization signal output CPOUT to the next stage. This external terminal +2
11 is connected to the input terminal of the synchronization signal CP of the next stage when the dot display driving ICs shown in FIG. 1 are used in cascade connection.

Next, as shown in Figure 1 (in a dot display driving ICE that can output 80 Y-axis signals, when 78 Y-axis signals are used, 78 pieces of display information are input The operation in this case will be explained with reference to FIG.

First, when the control signal LOAD is applied to the external terminal (3) K, E-FF (13) is set, the quaternary counter α4 is reset, and the decimal counter αη is reset by the pulse delayed by the delay circuit α9. As a result, the synchronization signal CP applied to the external terminal can be used as the clock pulse CLK to count the quaternary counter α.Therefore, display information DATA is applied to the external terminal αα together with the synchronization signal CP.Display information DATA is the display information DA for outputting the output Y of the liquid crystal drive circuit (1).
DATA2 and D in order from TA1 in synchronization with the synchronization signal.
ATA3... is applied to the external terminal (IIK) serially. When the first synchronization signal CP is counted by the quaternary counter α, the clock pulse CLl is output from the input clock generation decoder α9, so the display The information DATA1 is stored in the latch circuit (6).Next, when the second synchronization signal CP is counted by the quaternary counter I, the display information DATA2 is generated by the clock pulse CL2 output from the input clock generation decoder α9. is stored in the latch circuit (7).Similarly, display information DATA3 is stored in the latch circuit (8).
), and further, when the display information DATA4 is stored in the latch circuit (9) by the fourth synchronization signal CP, the display information DATA4 is stored in the latch circuit (9).
Since the output pulses of the quaternary counter circle that counted the synchronization signal CP are counted by the 20-decimal counter αD, the latch clock 01 is output from the decoder 0 seconds. Due to this latch clock, the display information DATAI of the latch circuit (6) is transferred to the latch circuit of the storage circuit (4).

The display information DATA2 of the latch circuit (7) is transferred to the latch circuit, the display information DATA3 of the latch circuit (8) is transferred to the latch circuit, and the display information DATA4 of the latch circuit (9) is transferred to and stored in the latch circuit L4. . By repeating the same operation, display information DATA5 and subsequent parts are accumulated in units of 4 bits. And finally display information DATA77
and DATA 78 are stored in the latch circuit (61 (71), when the application of the display information DATA and the synchronization signal CP is stopped and the control signal LOAD is applied, the control signal LOAD is converted into a 2o system via the OR gate 06). counter(
17) and is counted, the decoder u81 outputs a latte clock 02o. Therefore, the display information DATA77 of the latch circuit (6) is the latch circuit L77.
The display information DATA of the latch circuit (7) is transferred to and stored in the latch circuit (7).
78 is transferred and stored in the latch circuit LEA. At this time, latch circuit L7g and so on. There is also a latch circuit (
The signals stored in (8) and (9) are transferred, but the drive output Y7.8 of the Y thin electrode is transferred. and Y8o are not used, so
Any signal may be transferred. Therefore, when driving Y thin electrodes whose number is not a multiple of 40, the display information can be correctly stored in the storage circuit (4) without inputting all the display information in 4-bit units to the serial-parallel conversion circuit (5). .

(Ton) Effects of the Invention As described above, according to the present invention, it is possible to stop the serial transfer of display information at a number other than 40 times, and it is possible to stop the serial transfer of display information at a number other than 40 times. This eliminates the need for a dot display driving integrated circuit that is easy to use, and has the advantage of shortening display information transfer time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram showing the operation of the embodiment shown in FIG. Explanation of main drawing numbers (1)...Liquid crystal drive circuit, (2)...Memory circuit,
(3) σ112114...external terminal, (4)...
Storage circuit, (serial-parallel conversion circuit,
Housing υ...Control circuit.

Claims (1)

[Claims] 1. m× to drive the dots of a dot matrix display device
A drive circuit that generates and outputs n drive signals, a display information storage circuit that stores m×n pieces of display information indicating lighting and non-lighting of dots and supplies it to the drive circuit, and a display information storage circuit that stores display information that is applied from the outside. an accumulation circuit that sequentially accumulates data in units of m bits;
a serial-to-parallel conversion circuit which inputs m bits of display information serially applied from the outside and supplies it to the storage circuit; and input to the serial-to-parallel conversion circuit based on a synchronization signal applied in synchronization with the display information. In the dot display driving integrated circuit, the serial-to-parallel conversion circuit has inputs to which display information is commonly applied. An integrated circuit for driving a dot display, comprising m latch circuits, each latch operation of the latch circuit being performed by m pulses sequentially outputted from the control circuit based on the synchronization signal. .