JPS62226352A - Storage unit having ras - Google Patents

Abstract

PURPOSE:To prevent lowering of processing speed of a storage unit and reduce hardware by controlling not to make rewriting at the time of occurrence of 1 bit error during reading operation. CONSTITUTION:At the time of refresh cycle, a refresh execution state signal 17 and a 1 bit error detection signal 16 are inputted to an AND circuit 21-b, and when 1 bit error occurred, output signals become significant and inputted to a storage unit operation cycle control circuit 20 and an OR circuit 22-b. Then, the storage unit operation cycle control circuit 20 operates and lengthen internal cycle for writing corrected data. The OR circuit 22-b outputs a DRAM element storage section write signal 18 for writing corrected data. At the time of writing, a memory write signal 19 is inputted to the OR circuit 22-b and the DRAM element storage section write signal 18 is outputted.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is based on ECC (Error Correcting).
RAS with storage using dynamic read only memory (DRAM') with
(Re1ability, Availability
The present invention relates to a storage device with y rService ability)').

[Conventional technology]

FIG. 2 is a block diagram showing an overview of a conventional storage device as shown in, for example, the Intel Microsystem Handbook (Microprocessor and Peripherals Vol. If).

In the figure, 1 is a path, 2 is a DRAM element storage unit (EC
(with C), 3 is ECC check circuit, 4 is memory section/EC
C check circuit control section, 5 is an input data line, 6 is a check bit input data line, 7 is a DRAM element storage section output data line, 8 is a check bit output data line, 9 is an ECC
Check circuit status signal, 10 is ECC check circuit control signal, 11 is read/write (R/W) signal, 12 is response signal, 13 is address, 14 is DRAM element storage address, 15 is storage R/W signal It is.

Further, FIG. 3 is a diagram illustrating detailed internal operations of the storage section/ECC circuit control section 4 shown in FIG. 2.

In the figure, 16 is a 1-bit error detection signal (part of the ECC check circuit status signal 9), 17 is a refresh execution status signal, and 18 is a DRAM element storage write signal (a write signal for the storage R/W signal 15). o), 19 is a memory write signal (a write signal of the R/W signal 11).

), 2o is a storage device operation cycle control circuit, 21.21
-a is an AND circuit, 22°22-a is an OR circuit, and 23 is a memory read signal (R/W read signal 11).
There it is.

Next, the operation will be explained. First, data in the DRAM element storage section 2 is read out using a read signal of the R/W signal 11 from pass 1.

The read signal and address 13 are stored in the storage section.
CC check circuit control unit 4 (Intel, equivalent to DRAM controller 8207) When K is input, memory unit-ECC check circuit control unit 4 outputs memory R/W signal 15 and DRAM
The element memory unit address 14 is set to the DRAM element memory unit (ECC).
Attachment) Send to 2. By this operation, data at the address corresponding to the DRAM element storage section output data line 7 and the check bit (ECC pit) output data line 8 is output to the ECC check circuit 3. and ECC check circuit 3 (Intel Error Detection And
The correction unit (equivalent to 8206) detects errors in input data using check pits.

Here, if there is a 1-bit error, the ECC check circuit status ID number 9 is sent to the storage section/ECC check circuit control section 4, the 1-bit error is corrected, and the data and response signal 12 are transferred to the bus. Go to 1.

The storage section/ECC check circuit control section 4 outputs an ECC check circuit control signal 10 to the ECC check circuit 3, and then the ECC check circuit 3 generates a check bit of the corrected data and sends it to the check pit input data line 6.
Output to. Furthermore, the storage section/ECC check circuit control section 4 is configured to write the correction data existing on the input data line 5 and the check pit data existing on the check pit input data line 6 to the corresponding address of the DRAM element storage section 2. A write signal 15 is output. In this way, the operation of the storage device ends when the writing is completed.

If there is no 1-bit error, data is output to path 1.

Further, as mentioned above, since the DRAM element storage section 2 uses a DRAM element as a storage section, it is necessary to perform refresh. Refreshing is to prevent data in the storage from disappearing.

The memory refresh cycle is based on the row address (RAS).
), the column address (CAS) is output. Therefore, read operation of the storage section is possible. Therefore, it takes several tens of seconds to read all areas in a refresh cycle. Of course, if a 1-bit error occurs when reading,
Data is corrected and rewritten.

Next, the operation of the write signal generation logic when a 1-bit error occurs will be explained. When refreshing the DRAM element, the refresh execution state signal 17 and the 1-bit error detection signal 16 are input to the AND circuit 21, and if significant (when a 1-bit error is detected), the output signal of the AND circuit 21 is output to the OR circuit 22. -a, the DRAM element storage write signal 18 is generated, and the internal cycle is lengthened by the storage device operation cycle control circuit 20.

Further, at the time of reading, the memory read signal 23 and the 1-bit error detection signal 16 are input to the AND circuit 21-a. The output becomes significant when a 1-bit error occurs, and the OR circuit 22
．． 22-a to generate the DRAM element storage section write signal 18, and at the same time, the memory device operation cycle control circuit 2o operates, thereby lengthening the internal cycle.

At the time of writing, the memory write signal 19 is input to the OR circuit 22 to generate the DRAM element storage section write signal 18.

[Problem that the invention seeks to solve]

Conventional storage devices with RAS are configured as described above, so if a 1-bit error occurs when continuous reading of the storage section is performed, the data is corrected and then rewritten. This not only slows down the processing speed of the storage device, but also causes problems such as the control logic becoming complex due to the rewriting operation.

This invention was made to solve the above-mentioned problems. Even if a 1-bit error occurs during a read operation, only the data is corrected, which improves the processing speed of continuous operations and improves the readability. RA that can reduce the amount of hardware by eliminating the logic for writing
The purpose is to obtain a storage device with S.

[Means for solving problems]

In the storage device with RAS according to the present invention, during a read operation,
When a 1-bit error occurs, rewriting is stopped and rewriting is performed only for the 1-bit error during refresh.

[For production]

The storage device with ftAs according to the present invention improves the processing speed of the storage device by controlling to stop rewriting when a 1-write error occurs during a read operation.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same parts as in FIG. 3 are shown with the same reference numerals, 21-b is an AND circuit, and 22-b is an OR circuit.

Next, the operation will be explained. First, the operation of the present invention is as described in the prior art in FIG. It is characterized by not being rewritten. Other operations are the same as in the prior art.

That is, during the refresh cycle, the refresh execution state signal 17 and the 1-bit error detection signal 16 are input to the AND circuit 21-b, and if a 1-bit error occurs, the output signal becomes significant. It is input to the control circuit 20 and the OR circuit 22-b. Then, the storage device operation cycle control circuit 20 operates to lengthen the internal cycle for writing the modified data. Further, the OR circuit 22-b outputs the KDRAM element storage section write signal 18 in order to write the modified data. Also, during writing, the memory write signal 19 is input to the OR circuit 22-b and the DRA
The present invention focuses on the fact that refreshing is essential when using a DRAM element, and writes the row address (RAS) and Column address (C
AS') is output to perform a read operation for the corresponding address.

Therefore, a read operation of all areas of the storage section by refreshing can be executed in several tens of seconds. During this refresh cycle, if a 1-bit error occurs due to a read operation, the corresponding data is corrected and rewritten to the read address.

By the above-described operation, it is possible to correct a 1-bit error in the storage section within several tens of seconds. Incidentally, the main purpose of adding the ECC bit is to prevent soft errors in memory elements. Currently, the soft error rate per single element is approximately 5
About 50Fit (256K DRAM), 1
Even if 00 bits are used, one bit error will occur at a homogeneity of about once every two years. It can occur at any time within two years.

Therefore, it is considered that it is only necessary to detect a 1-bit error, correct the data, and rewrite the data only in the refresh cycle as the performance of the device improves.

It goes without saying that in the present invention, similar effects can be achieved even when the storage section is divided into a plurality of areas.

That is, it goes without saying that a similar effect can be obtained in a storage device that reads one area and refreshes another area only in RAS during a refresh cycle.

〔Effect of the invention〕

As described above, according to the present invention, since the control is performed so that rewriting is not performed even when a 1-bit error occurs during a read operation, the processing speed of the storage device is not reduced and the hardware can be reduced. Therefore, there is an effect that the storage device can be constructed at low cost.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a storage section and an ECC check circuit control section showing an embodiment of the present invention, FIG. 2 is a block diagram showing an overview of a conventional storage device, and FIG. 3 is a block diagram showing an outline of a conventional storage device. E.C.C.
It is a block diagram of a check circuit control part. In the figure, 2 is a DRAM element storage section, 3 is an ECC check circuit, 4 is a storage section/ECC check circuit control section, 1
8 is a DRAM element storage write signal, 19 is a memory write signal, 20 is a storage device operation cycle control circuit, and 21-
b is an AND circuit, and 22-b is an OR circuit. Patent Applicant Mitsubishi Electric Co., Ltd. Agent Patent Attorney 1) Hiroshi Sawa (2 others) Diagram 1 Procedural Amendment (Voluntary) 3. Representative of the person making the amendment Moriya Shiki 4. Agent Postal code: 105 Address place
1-4-10-5 Nishi-Shinbashi, Minato-ku, Tokyo, Subject of amendment (1) Claims of the specification 1ft 6, Contents of amendment (1) The claims are amended as shown in the attached sheet. (2) In the 5th line of page 9 of the specification, the phrase “in the storage unit,” should be amended to read “in the storage unit (storage capacity: 2 megabytes).” 7. After correcting the list of attached documents A document stating the scope of claims of one or more amended claims In a storage device with RAS having a D) tAM element storage section with an ECC check circuit, read when refreshing the D) tAM element storage section. The refresh execution state signal r accompanied by the operation is inputted together with the 1-bit error detection signal from the ECC check circuit to the storage device operation cycle control circuit of the storage section/ECC check circuit control section through an AND circuit, and D) LA by function
When a 1-bit error is detected in the output data of the M-element storage unit, the corrected data is rewritten to the corresponding address in the DRAM element storage unit, and when a read operation other than predistribution fresh is performed, the 1-bit error in the DRAM element storage unit is rewritten. A storage device with RAS, characterized in that only correction of bit errors is executed by an igcc check circuit control signal and a read signal.

Claims (1)

[Claims] R with DRAM element storage section with ECC check circuit
In the storage device with AS, when refreshing the DRAM element storage section, a refresh execution state signal accompanied by a read operation is sent together with a 1-bit error detection signal from the ECC check circuit to a storage device operation cycle control circuit of the storage section/ECC check circuit control section. is input through an AND circuit, and when a 1-bit error is detected in the output data of the DRAM element storage section by the function of the ECC check circuit, rewriting the corrected data to the corresponding address of the DRAM element storage section; A storage device with RAS, characterized in that, during a read operation other than the refresh, only correction of a 1-bit error in the DRAM element storage section is performed using a DRAM element storage write signal.