JPS61129799A - Error detecting and correcting control system of dynamic type memory - Google Patents

Abstract

PURPOSE:To make a delay of an access time due to an ECC circuit zero and to display a sufficient error detecting and correcting function by outputting the data which are not detected and corrected at the usual reading cycle and detecting and correcting the error at the time of refreshing cycles and restoring in a memory cell array. CONSTITUTION:The data read from a memory cell array 1 are quided to a control circuit 2, it is decided whether the cycle is a cycle outputted to a device external part by an external input signal to a memory device or a refreshing cycle, and when the data are outputted to the external part, the read data are sent to an output buffer circuit 3 as they are, in case of the refreshing cycle,reading data are sent to an ECC circuit 4. The output buffer circuit 3 outputs the sent data to the external part of the memory device, the ECC circuit 3 detects and corrects the error of the data sent to the refreshing cycle by means of a horizontal vertical parity system and restores the data into the memory cell array 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory, and more particularly to an error detection and correction control system in a dynamic memory equipped with an error correction code circuit (ECC circuit) for error detection and correction.

[Technical background of the invention]

Figure 4 shows a dynamic memory, one memory cell 40 in a normally used memory cell array. ni, r
One end is connected to the word line 43, and the other end is the MOS capacitor 44.
It is connected to a predetermined potential end via. In this memory cell 4θ, the word line drive signal turns on the FET 41 and stores charge in the capacitor 44C)
, the FET 41 is turned off and the charge is held in the capacitor 44, and dezotal binary information is stored depending on whether the capacitor 44 has a charge or not. The charge (digital information) held in the carrier 44 decays over time due to electrical leakage, etc., and disappears after a long period of time. Therefore, in order to retain the stored information, the information in the memory cell is read out to the bit line 42 at regular intervals and amplified by the sense amplifier 7'' (not shown). The so-called excitation operation (
It is necessary to perform a refrenoche operation).

On the other hand, as described above, information stored in memory cells may be lost due to unexpected causes. For example, α particles in the natural world that fly into a semiconductor memo+7f device (memory integrated circuit) generate a large amount of charge in the semiconductor substrate due to its ionization effect, and a part of it is integrated in the capacitor/mother 44. Therefore, the charge held in the carrier tie 4 is canceled out, resulting in the loss of information.

Such a phenomenon cannot be predicted, and although it may occur extremely rarely, it usually only causes a one-bit transient failure, and is called a so-called soft error. To deal with such defects, normally, as shown in FIG. 5, the read data from the memory cell array 51 is detected and corrected by an ECC circuit 52 on the same semiconductor substrate as the memory cell array. It is considered effective to output to As an example of the false 9 detection correction method using the ECC circuit 52, a horizontal
A vertical system is adopted. That is, mX of mXn memory cells specified by the same row address.
When n pieces of bit information are arranged in a matrix of virtual Km rows x n columns, the medianity of the data in each row is calculated and stored as a horizontal norm, and the medianity of the data in each column is calculated.
4 Rity shall be calculated and stored as Vertical Critity. Then, when reading the data in the first row and fifth column, the nodalities of the first digit and fifth column are simultaneously calculated. If the data at the intersection of the 1st row and 5th column is inverted due to a soft error between writing and reading from the memory cell, and the data inversion is only for the data at the intersection in the i row and 1st column. , the stored horizontal t41J values in the first row and vertical t417 values in the fifth column are the first values calculated at the time of reading.
It is different from the horizontal crit of the row and the vertical parity of the fifth column (they are in an inverted relationship). In other words,
By detecting that these numbers are in an inverted relationship and in a mismatched state, it can be known that the data at the intersection of the first row and fifth column has been inverted.

In this way, when reading data from the memory cell array, it is possible to determine whether the read data is correct or not by calculating and checking the nocritity, and if it is incorrect, the read data is inverted and corrected to the correct data, which is then output and re-stored. .

In addition, when writing data, the information bit and parity bit are stored by calculating the .4 lity of the first row and fifth column corresponding to the write data.

Here, the time-dependent change characteristics of the defective probability of memory cell data when using an ECC circuit are shown in Fig.
For comparison, the figure shows the change over time in the defective probability of memory cell data when the read data from the memory cell is directly output to the output buffer without using an ECC circuit (see Figure 7). It is shown in FIG.

That is, when the ECC circuit is not used, as shown in FIG. 8, after data is written at time t0, the probability that the data is defective increases monotonically with time, and if a sufficiently long time elapses, a large defect occurs. It becomes a probability. On the contrary,
FIG. 9 shows the case where the ECC circuit is used only for read operation, and when data is not read for a long time after writing at time t0, it increases monotonically with time as shown in characteristic A, but at time 1 When data is read out at 20° and a defect is detected and corrected, the defect probability once becomes zero and then increases again as shown in characteristic B. Furthermore, FIG. 10 shows a case where the ECC circuit is used for both the read operation and the refresher operation, and in this case, all memory cells are
False detection and correction will be applied in the cycle T (refresh cycle), so the probability of a defect increases with time within the cycle T, but once every cycle T, the probability of a defect decreases to zero. increase again. In this case, if a read operation occurs in the middle of the period T, defect detection and correction are performed at that point, and the defect probability once becomes zero. That is, in the case of the characteristics shown in FIG. 10, the failure probability does not increase indefinitely, and the period T
It can be seen that the failure probability reaches a ceiling as shown by the dotted line in the figure, with the increased value within the range being the maximum value.

[Problems with background technology]

By the way, when the above-mentioned ECC circuit is mounted on a semiconductor memory, considerably complicated logical procedures are required for data defect detection, such as calculation of accuracy and comparison check, as described above.

For this reason, the time from when the memory receives a signal to read data until it outputs the correct data (so-called access time) is the time required to output the read data from the memory cell directly to the output buffer without using an ECC circuit. The access time is considerably longer than the access time in the case of That is,
In the memory shown in Fig. 7 that does not use an ECC circuit, it usually takes 50 to 50 minutes after receiving the address signal to specify the memory cell.
If the output data is to be output externally in 75ns,
In the circuit shown in FIG. 5 using the ECC circuit, the external output of the above output data is further delayed by about 30 to 40 ns. Such a delay in access time increases the computation time and degrades the performance of the combinator system that uses memory, so there is a risk that it will no longer be actually used in computers. The current situation is that the market value of memory devices equipped with this has declined, and their popularity is currently low.

However, as the trend toward higher integration and miniaturization of memory devices progresses, the probability of soft errors occurring steadily increases, and the need to use ECC circuits increases. There is a need for countermeasures to reduce the impact of circuit usage on access time delays.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and provides error detection and correction control for a dynamic 7-type memory that can eliminate the access time delay caused by the ECC circuit in read cycle operations and that can exhibit a sufficient error detection and correction function. system.

[Summary of the invention]

That is, the dynamic memory error detection and correction control system of the present invention outputs read data from the memory cell array as data that has not been subjected to error detection and correction by the ECC circuit during normal read cycle operation, and outputs data that has not undergone error detection and correction by the ECC circuit during refresh cycle operation. This is characterized in that an erroneous detection and correction is performed by an ECC circuit and the data is stored again in the memory cell array.

As a result, the access time delay caused by the ECC circuit in the read cycle operation can be reduced to zero.
Moreover, a sufficient error detection and correction function can be achieved by error detection and correction during the refresh cycle operation.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a part of a memory 7't4 chair according to an embodiment of the present invention, in which data is read out from a memory cell array 1 via a sense amplifier (not shown) and a column selection circuit (not shown). The obtained data is led to the control circuit 2. This control circuit 2 uses external input signals to the memory device (row address strobe 7'RAS signal, column address strobe CAS signal, etc.) to determine whether the cycle is a cycle in which read data is output to the outside of the device or a freshe cycle. When determining and outputting data to the outside, the read data is sent as is to the output buffer circuit 3,
In the case of reflexology cycle, read data is ECC
It is sent to circuit 4. The output buffer circuit 3 outputs the data sent to the outside of the memory device, and the ECC circuit 4 converts the data sent in the refresh cycle into the horizontal-vertical crit method as described above. Errors are detected and corrected and then stored in the memory cell array 1 again.

FIG. 2 shows another embodiment, in which the memory cell array 1
The read data from the output buffer circuit 21 and E
It is input to the CC circuit 22, and this output panor 7a circuit 2 outputs r-t to the outside when it receives a data output request signal (usually a CAS signal) from the outside, and no data output request signal is received. (Refreno 7 cycle), no data is output. The ECC circuit 22 detects and corrects errors in one piece of data read from the memory cell array 1 during the refresher cycle, and restores the data.

In the error detection and correction control system of each of the above embodiments, the path KEC from the memory cell array 1 to the data output to the outside is
It can be seen that since no C circuit is involved, the access time delay associated with data reading is zero. Note that when writing data, the ECC circuit calculates 4 retaibits as usual, so it takes more time than when the ECC circuit is not used. However, data writing only needs to be completed within one memory cycle time, and this one cycle time is usually 190 to 260n+s, which is long enough, and a normal write operation is completed in a much shorter time than the above one cycle time. Therefore, even if the write time is slightly extended by the ECC circuit, there is no risk of the one cycle time being extended. Further, the 7-receive operation only needs to be completed within one cycle time, just like the write operation, and since there is sufficient time in this case as well, there is no risk of the ECC circuit prolonging the one cycle time.

That is, according to the error detection and correction control system according to each of the above embodiments, the access time and cycle time of the memory device are
This can be the same as when the C circuit is not used. Moreover, the error detection and correction function can be fully utilized even if the error detection and correction is performed only for the refresh operation and the error detection and correction is not performed for the normal read operation. The change over time in the probability of failure in this case is as shown in Figure 3.The probability of failure after data writing is represented by a sawtooth waveform with a refresh period T, and the maximum value of the failure probability is as shown by the dotted line in the figure. EC in refresh cycle
This is the value immediately before using the C circuit, and its magnitude is the same as the maximum value of K in the characteristic (FIG. 1O) when the ECC circuit is used for the read operation shown in the conventional example. From this, it can be seen that the effectiveness of suppressing the probability of failure by using the ECC circuit is no inferior to the characteristics shown in FIG. 10.

〔Effect of the invention〕

As described above, according to the error detection and correction control system for a dynamic memory according to the present invention, it is possible to eliminate the access time delay caused by the ECC circuit in the read cycle operation, and it is also possible to exhibit a sufficient error detection and correction function.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of an error detection and correction control system for a dynamic memory according to the present invention, FIG. 2 is a block diagram showing another embodiment, and FIG.
A characteristic diagram showing the change in defect probability over time in the memory shown in the figure.
Figure 4 is a circuit diagram showing an example of a dynamic memory cell, Figure 5 is a block diagram showing part of a dynamic memory equipped with a conventional ECC circuit, and Figure 6 is a horizontal/vertical/yelty system using an ECC circuit. Fig. 7 is a block diagram showing a part of the conventional Guinaminok memory, and Fig. 8 shows the characteristics of the memory shown in Fig. 7 showing the change in defect probability over time. 9 is a characteristic diagram showing the change over time in the failure probability when the IIECC circuit is used only for the read operation in the memory shown in FIG.
Figure 0 shows the read operation in the memory of Figure 6 and 7.
FIG. 7 is a characteristic diagram showing a change in failure probability over time when a GCC circuit is used for renoshi operation. 1...Memory cell array, 2...Control circuit, 3゜21
...output sofa circuit, 4.22...BCC circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 1
Figure 2 Figure 3 Figure 1 included Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 N9 Figure 10

Claims (3)

[Claims] (1) Data read from the memory cell array is output without error detection and correction by the error correction code circuit during normal read cycle operation, and error detection and correction is performed by the error correction code circuit during refresh cycle operation. An error detection and correction control system for a dynamic memory, characterized in that the error detection and correction control system performs re-storage in a cell array. (2) Read data from the memory cell array,
An error detection and correction control system for a dynamic memory according to claim 1, further comprising means for switching and supplying an output buffer circuit or an error correction code circuit according to an operation mode designation input signal. . (3) Read data from the memory cell array is input to an output buffer circuit and an error correction code circuit, and upon receiving a data output request signal, data is output from the output buffer circuit. An error detection and correction control system for a dynamic memory according to claim 1.