JPS62222626A - Semiconductor wafer - Google Patents
Semiconductor waferInfo
- Publication number
- JPS62222626A JPS62222626A JP6812186A JP6812186A JPS62222626A JP S62222626 A JPS62222626 A JP S62222626A JP 6812186 A JP6812186 A JP 6812186A JP 6812186 A JP6812186 A JP 6812186A JP S62222626 A JPS62222626 A JP S62222626A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- inp
- substrate
- silicon
- germanium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000013078 crystal Substances 0.000 claims abstract description 29
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 21
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 18
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 48
- 239000002356 single layer Substances 0.000 abstract description 2
- 150000001875 compounds Chemical class 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 150000002290 germanium Chemical class 0.000 description 1
- 150000004820 halides Chemical class 0.000 description 1
- LHJOPRPDWDXEIY-UHFFFAOYSA-N indium lithium Chemical compound [Li].[In] LHJOPRPDWDXEIY-UHFFFAOYSA-N 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02543—Phosphides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02461—Phosphides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
- H01L21/02507—Alternating layers, e.g. superlattice
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明はシリコン（Ｓｉ）基板上に良質のインジウム・
リン（ＩｎＰ）単結晶を得るだめの半導体ウェハ構造に
関するものである。[Detailed Description of the Invention] <Industrial Application Field> The present invention provides high-quality indium on a silicon (Si) substrate.
The present invention relates to a semiconductor wafer structure for obtaining a phosphorus (InP) single crystal.
〈従来の技術〉
■−■族化合物半導体は、光学的及び電気的特性に於い
て、■族元素半導体（Ｓｉ、Ｇｅ）等では得られない特
徴を有しており、その特徴デバイスとしてＬＥＤ（発光
ダイオード）、ＬＤ（レーザ・ダイオード）等のエレク
トロ・ルミネッセンス・デバイスや高速ＦＥＴ、ガン・
ダイオード、ホール素子等の電子デバイスが挙げられる
。従来、このようなデバイスは■−ｖ族化合物半導体（
ＧａＡｓ。<Prior art> ■-■ group compound semiconductors have optical and electrical properties that cannot be obtained with group-■ element semiconductors (Si, Ge), etc., and their characteristic devices include LEDs ( Electroluminescent devices such as light emitting diodes), LDs (laser diodes), high speed FETs, gun
Examples include electronic devices such as diodes and Hall elements. Conventionally, such devices have been made using ■-v group compound semiconductors (
GaAs.
ＩｎＰ％ＧａＰ等）の結晶基板上にエピタキシャル成長
等のプロセスを施して作製したものであり、■−Ｖ族化
合物半導体のバルク結晶が常に必要となる。このバルク
結晶は結晶成長の困難さ等のため歩留りが悪く、価格と
しても非常に高価なものであり、また特にインジウム・
リン（ＩｎＰ）などは、現在までのところ２インチ形状
のものしか得られていなく、大面積化についても困難な
状態である。It is manufactured by performing a process such as epitaxial growth on a crystal substrate of (InP%GaP, etc.), and a bulk crystal of a ■-V group compound semiconductor is always required. This bulk crystal has a low yield due to the difficulty of crystal growth and is extremely expensive.
Phosphorus (InP) and the like have so far only been available in a 2-inch shape, and it is difficult to increase the area.
更に、今後、高機能デバイスとして、三次元回路素子や
機能分離型デバイス（信号受発部を■−Ｖ族化合物が、
信号処理部をシリコン（Ｓｉ）が受は持っているような
デバイス）の開発を考慮した場合についても、安価で良
質のシリコン（Ｓｉ）単結晶基板上に■−ｖ族化合物を
形成することは重要な半導体素子形成技術である。Furthermore, in the future, as high-performance devices, three-dimensional circuit elements and functionally separated devices (signal receiving and receiving parts may be made of ■-V group compounds,
Even when considering the development of a device in which the signal processing part is made of silicon (Si), it is difficult to form a ■-V group compound on a cheap and high quality silicon (Si) single crystal substrate. This is an important semiconductor element formation technology.
〈発明が解決しようとする問題点〉
しかし、シリコン（Ｓｉ）基板上にインジウム・リ／の
エピタキシャル成長を行う場合には、その間に約８チの
格子不整があることや単原子結晶上に２原子化合物を成
長させる問題としてアンチフェイズ・ドメインの発生が
あり、結晶成長を困難にしている。<Problems to be solved by the invention> However, when indium lithium is epitaxially grown on a silicon (Si) substrate, there is a lattice mismatch of about 8 cm between them, and two atoms are grown on a monoatomic crystal. A problem with growing compounds is the occurrence of antiphase domains, which makes crystal growth difficult.
本発明は、上記の点に鑑みて創案されたものであり、上
述のシリコン（Ｓｉ）単結晶基板上への■−Ｖ族化合物
成長法の一手法として、多層薄膜形成を可能にするＭＯ
ＣＶＤ法又はＭＢＥ法等の各種成長法によりシリコン（
Ｓｉ）単結晶基板上に良質なインジウム・す７（ＩｎＰ
）のエピタキシャル成長を行うのに適した構造の半導体
ウェハを提供することを目的としている。The present invention was devised in view of the above points, and is a method for growing a -V group compound on the silicon (Si) single crystal substrate described above.
Silicon (
Si) high quality indium 7 (InP) on a single crystal substrate
) The purpose of the present invention is to provide a semiconductor wafer having a structure suitable for epitaxial growth.
く問題点を解決するだめの手段〉
上記の目的を達成するため、本発明の半導体ウェハは、
シリコン（Ｓｉ）基板とインジウム・す／（ＩｎＦ’）
エピタキシャル層との間に、ゲルマニウム（Ｇｅ）’！
１ｃｉｔ’ｒ’ルマニウムーシリコン（Ｇｅ −Ｓｉ）
系の混晶からなる中間層を有してなるように構成してい
る。Means for Solving the Problems> In order to achieve the above object, the semiconductor wafer of the present invention has the following features:
Silicon (Si) substrate and indium su/(InF')
Between the epitaxial layer, germanium (Ge)'!
1cit'r'rumanium-silicon (Ge-Si)
It is configured to have an intermediate layer made of a mixed crystal of the system.
即ち、本発明では、シリコン（Ｓｉ）基板とインジウム
・リン（ＩｎＰ）エピタキシャル層の間に中間層として
、シリコン（Ｓｉ）（格子定数５．４３Ａ）とインジウ
ム・リン（ＩｎＰ）（格子定数５．８７Ａ）の中間の格
子定数を持つゲルマニウム（Ｇｅ） （格子定数５．６
４６Ａ）またはゲルマニウム（Ｇｅ）トシリコン（Ｓｉ
）との混晶により形成した層を用いることにより、良質
のインジウム・リン（ＩｎＰ）エピタキシャル層を形成
するようにしたものである。That is, in the present invention, silicon (Si) (lattice constant 5.43A) and indium phosphide (InP) (lattice constant 5.43A) are used as an intermediate layer between a silicon (Si) substrate and an indium phosphide (InP) epitaxial layer. Germanium (Ge) with a lattice constant intermediate to 87A) (lattice constant 5.6
46A) or germanium (Ge) to silicon (Si)
), a high-quality indium phosphide (InP) epitaxial layer is formed by using a layer formed by a mixed crystal with .
〈実施例〉
以下、図面を参照して本発明の実施例を詳細に説明する
。<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の一実施例の半導体ウェハの構造を示す
断面図である。FIG. 1 is a sectional view showing the structure of a semiconductor wafer according to an embodiment of the present invention.
第１図において、１はシリコン（Ｓｉ）単結晶基板であ
り、この基板ｌ上に中間層２としてゲルマニウム（Ｇｅ
）層を膜厚１〜ｌＯμｍに形成し、このゲルマニウム（
Ｇｅ）中間層２の上にインジウム・リン（Ｉｎｋ）単結
晶層３を得るように構成している０
上記のシリコン（Ｓｉ）基板１は、インジウム・リン（
ＩｎＰ）層におけるアンチフェーズの発生を防ぐ目的で
（１００）面方向に２〜５オンした（１００）方位を用
いる。またゲルマニウム（Ｇｅ）中間層２は分子線エピ
タキシ或いはクラスタイオンビーム法等により形成して
好適である。またゲルマニウム（Ｇｅ）中間層２の上に
インジウム・リン（ＩｎＰ）を成長させる方法としてＭ
ＯＣＶＤ 、ハライドＶＰＥ等を用いて好適である。In FIG. 1, reference numeral 1 denotes a silicon (Si) single crystal substrate, and an intermediate layer 2 made of germanium (Ge) is formed on this substrate l.
) layer is formed to a thickness of 1 to 10 μm, and this germanium (
The above silicon (Si) substrate 1 is configured to obtain an indium phosphide (Ink) single crystal layer 3 on an indium phosphide (Ink) intermediate layer 2.
In order to prevent the occurrence of anti-phase in the (InP) layer, a (100) orientation with 2 to 5 degrees of orientation in the (100) plane direction is used. The germanium (Ge) intermediate layer 2 is preferably formed by molecular beam epitaxy, cluster ion beam method, or the like. In addition, M
OCVD, halide VPE, etc. are preferably used.
上記第１図に示したように、中間層２としてゲルマニウ
ム（Ｇｅ）単層を用いることにより、その上に良質なイ
ンジウム・リン（Ｉ ｎ？ ）の結晶成長を行なうこと
が出来るが、第２図に示すように、ゲルマニウム−シリ
コン（Ｇｅ−Ｓｉ）混晶からなる歪超格子層を中間層と
して用いる、あるいはゲルマニウム−シリコ：ｙ（Ｇｅ
−Ｓｉ）混晶からなる歪超格子層を介してゲルマニウム
層を積層することにより更に欠陥低減をはかることが出
来る。As shown in FIG. 1 above, by using a germanium (Ge) single layer as the intermediate layer 2, high-quality indium phosphide (In?) crystal growth can be performed thereon. As shown in the figure, a strained superlattice layer made of germanium-silicon (Ge-Si) mixed crystal is used as an intermediate layer, or germanium-silico:y(Ge
-Si) Defects can be further reduced by stacking germanium layers via a strained superlattice layer made of mixed crystal.
即ち、第２図はより望ましい本発明の他の実施例の構造
を示す断面図であり、シリコン（Ｓｉ）単結晶基板４と
インジウム・リン（ＩｎＰ）成長層６との間にゲルマニ
ウム（Ｇｅ ）−シリコン（Ｓｉ）系超格子層５を設け
ることにより、インジウム・す／（ＩｎＰ）成長層６と
の格子整合をはかり、良質の単結晶エピタキシャル層を
得るようにしたものである。That is, FIG. 2 is a cross-sectional view showing the structure of another preferred embodiment of the present invention, in which germanium (Ge 2 ) is formed between the silicon (Si) single crystal substrate 4 and the indium phosphide (InP) growth layer 6 - By providing a silicon (Si)-based superlattice layer 5, lattice matching with the indium/su/(InP) growth layer 6 is achieved, and a high quality single crystal epitaxial layer is obtained.
この場合、上記ゲルマニウム（Ｇｅ）−シリコン（Ｓｉ
）系超格子層５は例えばＭＯＣＶＤ法により形成したシ
リコ７（Ｓｉ）とゲルマニウム（Ｇｅ ）の極薄膜交互
成長層（超格子層）で構成しても良く、１７’ｃゲルマ
ニウム（Ｇｅ）−シリコン（Ｓｉ）混晶よりなる極薄膜
をゲルマニウム（Ｇｅ ）の混晶比が順次増加するよう
に積層した組成傾斜成長層（超格子層）で構成して、格
子整合を行なうように成しても良い。In this case, the germanium (Ge)-silicon (Si)
) system superlattice layer 5 may be composed of ultrathin film alternate growth layers (superlattice layer) of silicon 7 (Si) and germanium (Ge) formed by MOCVD method, for example, and 17'c germanium (Ge)-silicon. It is also possible to achieve lattice matching by constructing an ultra-thin film made of (Si) mixed crystal with compositionally graded growth layers (superlattice layers) stacked so that the germanium (Ge) mixed crystal ratio increases sequentially. good.
また、上記超格子層５上にゲルマニウム層を積層し、そ
の上にインジウム・リン（ＩｎＰ）成長層６を形成して
も良い。Alternatively, a germanium layer may be laminated on the superlattice layer 5, and an indium phosphide (InP) growth layer 6 may be formed thereon.
なお、上記第１図及び第２図に示したように構成した場
合においても、インジウム−リン（Ｉｎｋ）とゲルマニ
ウム（Ｇｅ）との間には、まだ４襲程度の格子不整合が
残っているが、第３図に示すように、シリコン（Ｓｉ）
単結晶基板７上に形成したゲルマニウム（Ｇｅ）中間層
８の上にＩｎＰ／ＩｎＧａＰ超格子層あるいはＩｎＰ低
温低温成長７フルフアス第２の中間層９として形成する
ことにより、インジウム・リン（ＩｎＰ）との格子整合
をとり、比較的容易に高品質のインジウム・リン（Ｉｎ
Ｐ）エピタキシャル層１０を得ることが出来る。Note that even in the case of the configuration shown in Figures 1 and 2 above, there is still a lattice mismatch of about 4 bands between indium-phosphide (Ink) and germanium (Ge). However, as shown in Figure 3, silicon (Si)
By forming an InP/InGaP superlattice layer or an InP low-temperature low-temperature growth 7 full-length second intermediate layer 9 on the germanium (Ge) intermediate layer 8 formed on the single crystal substrate 7, indium phosphide (InP) and lattice matching and relatively easily produce high quality indium phosphide (In
P) An epitaxial layer 10 can be obtained.
〈発明の効果〉
以上に説明した本発明に係る中間層構造を用いることに
よりシリコｙ（Ｓｉ）基板上に直接インジウム・リン（
ＩｎＰ）を形成することによっては得られない良質のイ
ンジウム・リン（ＩｎＰ）結晶を得ることができる。こ
のような半導体ウェハ及び成長技術は、大面積で低価格
のインジウム・リン（ＩｎＰ）基板の供給や機能分割型
デバイス等の複合化デバイス実現等に於いて非常に有用
となるものである。<Effects of the Invention> By using the intermediate layer structure according to the present invention described above, indium phosphide (
Indium phosphide (InP) crystals of high quality, which cannot be obtained by forming InP), can be obtained. Such semiconductor wafers and growth techniques are extremely useful in supplying large-area, low-cost indium phosphide (InP) substrates and in realizing complex devices such as functionally divided devices.
第１図乃至第３図はそれぞれシリコン（Ｓｉ）基板上に
形成したインジウム・リン（Ｉ ｎＰ）単結晶ウェハの
実施例を示す断面図である。
１．４．７・・・シリコ／（Ｓｉ）単結晶基板、２゜８
・・・ゲルマニウム（Ｇｅ）中間層、３，６．１０・・
・インジウム・リン（Ｉｎｋ）成長層、５・・・ゲルマ
ニウム（Ｇｅ ）−シリコン（Ｓｉ）系超格子層、９・
・・ＩｎＰ−ＩｎＧａＰ系超格子層。1 to 3 are cross-sectional views showing examples of indium phosphide (InP) single crystal wafers formed on silicon (Si) substrates, respectively. 1.4.7...Silico/(Si) single crystal substrate, 2°8
...Germanium (Ge) intermediate layer, 3,6.10...
・Indium phosphide (Ink) growth layer, 5... germanium (Ge)-silicon (Si) based superlattice layer, 9.
...InP-InGaP superlattice layer.
Claims (1)
）エピタキシャル層との間に、ゲルマニウム（Ｇｅ）ま
たはゲルマニウム−シリコン（Ｇｅ−Ｓｉ）系の混晶か
らなる中間層を有してなることを特徴とする半導体ウェ
ハ。1. Silicon (Si) substrate and indium phosphide (InP)
) A semiconductor wafer comprising an intermediate layer made of germanium (Ge) or germanium-silicon (Ge-Si) based mixed crystal between an epitaxial layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6812186A JPS62222626A (en) | 1986-03-24 | 1986-03-24 | Semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6812186A JPS62222626A (en) | 1986-03-24 | 1986-03-24 | Semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62222626A true JPS62222626A (en) | 1987-09-30 |
Family
ID=13364594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6812186A Pending JPS62222626A (en) | 1986-03-24 | 1986-03-24 | Semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62222626A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009177170A (en) * | 2007-12-28 | 2009-08-06 | Sumitomo Chemical Co Ltd | Semiconductor substrate and method of manufacturing the same, and electronic device |
| WO2019173630A1 (en) * | 2018-03-09 | 2019-09-12 | Atomera Incorporated | Semiconductor device and method including compound semiconductor materials and an impurity and point defect blocking superlattice |
| US10468245B2 (en) | 2018-03-09 | 2019-11-05 | Atomera Incorporated | Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice |
| US10727049B2 (en) | 2018-03-09 | 2020-07-28 | Atomera Incorporated | Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice |
-
1986
- 1986-03-24 JP JP6812186A patent/JPS62222626A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009177170A (en) * | 2007-12-28 | 2009-08-06 | Sumitomo Chemical Co Ltd | Semiconductor substrate and method of manufacturing the same, and electronic device |
| WO2019173630A1 (en) * | 2018-03-09 | 2019-09-12 | Atomera Incorporated | Semiconductor device and method including compound semiconductor materials and an impurity and point defect blocking superlattice |
| US10468245B2 (en) | 2018-03-09 | 2019-11-05 | Atomera Incorporated | Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice |
| US10727049B2 (en) | 2018-03-09 | 2020-07-28 | Atomera Incorporated | Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice |
| CN112005340A (en) * | 2018-03-09 | 2020-11-27 | 阿托梅拉公司 | Semiconductor device including compound semiconductor material and superlattice for blocking impurities and point defects, and method thereof |
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