JPS62220027A - Semiconductor boosting signal generating circuit - Google Patents

Abstract

PURPOSE:To generate a boosting signal at a high speed and with low power consumption by using a boosting signal generating circuit comprising plural MOSFETs and capacitances. CONSTITUTION:MOSFETs 1-4 are turned off for times t0-t1, the MOSFET 2 is turned on to discharge the electric charge in capacitors 5, 11 at the time t1. When the potential at a line 9 is zero, the FET 3 is turned on and a boosting voltage Vp is outputted from a boosting potential generator 8. Then the MOSFET 2 is turned off for times t1-t2, the MOSFET 1 is turned on at the time t2 to charge the potential of the line 9. Then the potential of the signal phi3 is increased at the time t3 and the electric charge stored in the capacitor 5 boosts the potential of the wire 9. Then the MOSFET 4 is turned on at the time t4, the potential of a line 10 is decreased to 0V to restore the state to that at the time t0. Thus, a boosting signal is generated at the line 10 connected between the FETs 3, 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor boost signal generation circuit in a MOS type integrated circuit.

[Conventional technology]

Conventionally, there has been a boost signal generating circuit of this type as shown in FIG. In this figure, φ8 is the boosted signal, 1
8 is a load capacitance to the boosted signal φ, and its value is CI
It is. φB is a boost signal, 19 is a boost capacitor, and its value is C2.

Further, FIG. 5 is a waveform diagram of the boosted signal φ8 and the boosted signal φB during operation of the boosted signal generation circuit shown in FIG. 4.

Next, the operation will be explained with reference to FIG.

First, from time t5, the boosted signal φ8 starts charging the load capacitor 18 and the boost capacitor 19. Next, at time t6, the potential to the boosted signal φ is set to the power supply voltage V or the power supply voltage V
It has a slightly lower potential. Then from time t6 to time t7
During this period, the boosted signal φ^ is boosted to the power supply voltage 7 or higher by the boosted signal φB and the external voltage capacitor 19. The maximum boost value to the boosted signal φ is.

[Problem that the invention seeks to solve]

In the conventional boost signal generation circuit as described above, in order to obtain a high boost potential, the value of C2 of the boost capacitor 19 must be increased, which increases the power consumption and time required to charge the boost capacitor 19. There were problems such as the need to lengthen the interval t6-t5. This invention was made to solve these problems, and it provides a semiconductor boost signal generation circuit that generates a boost signal at high speed and with low power consumption. The purpose is to obtain.

[Means for solving problems]

The semiconductor boost signal generation circuit according to the present invention includes a first MOS connected in series between a high potential power supply and a low potential power supply, and each gate of which is connected to a first signal and a second signal.
FET and a second MOSFET, and one electrode is connected to the first MOSFET.
A capacitor connected between the MOSFET and the second MOSFET, the other electrode of which is connected to the third signal, a boosted potential generator, and a boosted potential generator connected in series between the boosted potential generator and the low potential power supply, respectively. A third MOSFET and a fourth MOSFET each have a gate connected between the first MOSFET and the second MOSFET and to a fourth signal.

[Effect]

In this invention, the first MOSFET and the second MOSFET
The gate of the third MOSFET is controlled by the charge accumulated between the SFETs and the gate of the third MOSFET and in the capacitance, and the gate of the fourth MOSFET is controlled by the fourth signal. 7
) A boost signal is generated between the MOSFETs.

〔Example〕

FIG. 1 is a diagram showing the configuration of an embodiment of the semiconductor boost signal generating circuit of the present invention. In this figure, 1, 2.4 are the 1st . The second and fourth MOSFETs are N
Channel type MoS transistor, 3 is the third MOSFE
T is a P-channel type MOS transistor, 5 is a capacitance, and its value is CIO. 6 is the power line, 7 is the GND line,
8 is a boosted potential generator whose output voltage is Vp.

9.10 is a wiring, and the wiring 9 connects the source of the N-channel MOS transistor 1 and the N-channel MOS transistor 2.
The drain of the P-channel MOS transistor 3 and one electrode of the capacitor 5 are electrically connected. Wiring 1
0 electrically connects the source of P-channel type MOS transistor 3 and the drain of N-channel type MOS transistor 4. In addition, the drain of the N-channel type MO transistor 1 is connected to the power supply line 6, the sources of the N-channel type MO transistors 2 and 4 are connected to GNDVj7, and the drain of the P-channel type MO transistor 3 is connected to the boosted potential generator 8. Wiring is provided to supply the generated boosted potential VP.

11 is a capacity that equivalently represents the load capacity of the meter 9,
Its value is C2G. 12 is a capacitance equivalently representing the load capacitance of the wiring 1o, and its value is C3G. Signals φ1 and φ2, which are the first, second and fourth signals, are applied to the gates of the N-channel MOS transistors 1 and 2.4, respectively.

φ4 is applied, and the third signal °φ3 is applied to the other electrode of the capacitor 5. Note that the voltage of the power supply line 6 is assumed to be V.

FIG. 2 is a diagram showing voltage waveforms of main parts in FIG. 1.

FIG. 3 is a diagram showing the configuration of one embodiment of the boost signal generating device 8 in FIG. 1. In this figure, 13 is a ring oscillator, 14 is a charge pump capacitor, 15.
16 is a MOS transistor, and 17 is a potential storage capacitor. One electrode of the charge pump capacitor 4 is connected to the output of the ring oscillator 13, and the other electrode is connected to the source of the MoS transistor 15 and the drain and gate of the MOS transistor 16. The drain and gate of MOS transistor 15 are connected to a power supply, one electrode of potential storage capacitor 17 is connected to the source of MOS transistor 16, and the other electrode is grounded.

Note that since FIG. 3 is a well-known circuit, a description of its operation will be omitted.

Next, the operation of the semiconductor boost signal generating circuit of the present invention will be explained with reference to FIG.

First, from time to to tl, signals φ1 and φ4
is set below the threshold voltage VIHI, VI114 of the N-channel MOS transistor 1.4. Next, at time t1, the signal φ2 exceeds the threshold voltage V182 of the N-channel MOS transistor 2, discharging the charges in the capacitors 5 and 11, and lowering the potential of the wiring 9 to O [■]. P-channel type MOS transistor 3 is turned on when the potential of wiring 9 drops, and outputs boosted potential VP. Then, from time tl to t2, signal φ2 is made lower than the threshold voltage VIH2 of N-channel MOS transistor 2, and the potential of signal φ3 is also lowered. Then, at time t2, the potential of the signal φl rises, turning on the N-channel MOS transistor 1, and lowering the potential of the wiring 9 to V − V 1
Charge to 81. Then, at time t3, the signal φ
When the potential of the wiring 9 is increased, the potential of the wiring 9 increases to v'P due to the charges accumulated in the capacitor 5. Regarding the value of vTP, let the amplitude of signal φ3 be V.

It can be changed by the formula. Then, at time t4, (
The UY signal φ4 becomes equal to or higher than the threshold voltage vl of the N-channel MOS transistor 4, and the potential of the wiring 1o becomes O (V). Then, when the potential of the wiring 1o becomes approximately O (V), the overall state becomes equal to the initial state at time to.

Note that if Vp'>Vp-I Vr+ul is established at this time, the P-channel MOS transistor 3 will be in a cut-off state, and the current consumption can be almost ignored.

〔Effect of the invention〕

As described above, the present invention includes a first MOSFET and a second MOSFET that are connected in series between a high potential power source and a low potential power source, and whose respective gates are connected to a first signal and a second signal; One electrode is the first MOSF
a capacitor connected between the ET and the second MOSFET, the other electrode of which is connected to a third signal; a boosted potential generator;
This boosted potential generator is connected in series between the low potential power supply, and each gate is connected to a first MOSFET and a second MOSFET.
Third MOS connected between SFETs and fourth signal
Since it is composed of a FET and a fourth MOSFET,
This has the advantage that a boost signal can be generated at high speed and with low power consumption.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of one embodiment of the semiconductor boosted signal generation circuit of the present invention, FIG. 2 is a waveform diagram of the main part in FIG. 1, and FIG. 3 is the configuration of one embodiment of the boosted potential generation device. FIG. 4 is a diagram showing the configuration of an example of a conventional boost signal generation circuit, and FIG. 5 is a waveform diagram for explaining the operation of the conventional boost signal generation circuit. In the figure, 1, 2.4 are N-channel MOS transistors, 3 is a P-channel MOS transistor, 5 is a capacitor, 6 is a power line, and 7 is a GND! 8 is a boosted potential generator. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) I Figure 2 Figure 3 Figure 4 Figure 5 IStfit7

Claims (1)

[Claims] A first MOSFET and a second MOSFET are connected in series between a high potential power supply and a low potential power supply, and each gate is connected to a first signal and a second signal, and one electrode is connected to the first MOSFET. MOSFET and the second MOSFET
A capacitor connected between T and the other electrode connected to the third signal, a boosted potential generator, and a boosted potential generator connected in series between the boosted potential generator and the low potential power supply, each gate connected to the third signal. 1. A semiconductor boost signal generation circuit comprising a third MOSFET and a fourth MOSFET connected between the first MOSFET and the second MOSFET and to a fourth signal.