JPS62219546A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62219546A JPS62219546A JP6189486A JP6189486A JPS62219546A JP S62219546 A JPS62219546 A JP S62219546A JP 6189486 A JP6189486 A JP 6189486A JP 6189486 A JP6189486 A JP 6189486A JP S62219546 A JPS62219546 A JP S62219546A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- chip
- plate
- aln substrate
- sheets
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 6
- 238000005476 soldering Methods 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 229910052759 nickel Inorganic materials 0.000 claims 1
- 239000010936 titanium Substances 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
- 239000010949 copper Substances 0.000 abstract description 16
- 229910000679 solder Inorganic materials 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 230000005496 eutectics Effects 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 229910015365 Au—Si Inorganic materials 0.000 abstract 1
- 229910002480 Cu-O Inorganic materials 0.000 abstract 1
- 229910020220 Pb—Sn Inorganic materials 0.000 abstract 1
- 230000008018 melting Effects 0.000 abstract 1
- 238000002844 melting Methods 0.000 abstract 1
- 239000012299 nitrogen atmosphere Substances 0.000 abstract 1
- 238000005245 sintering Methods 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 101100402795 Caenorhabditis elegans mtl-1 gene Proteins 0.000 description 1
- -1 MO metallization Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000001272 pressureless sintering Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 231100000331 toxic Toxicity 0.000 description 1
- 230000002588 toxic effect Effects 0.000 description 1
- 231100000419 toxicity Toxicity 0.000 description 1
- 230000001988 toxicity Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的コ
（産業上の利用分野）
本発明は高熱伝導性のＡｌＮ基板を用いた半導体装置に
関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention relates to a semiconductor device using a highly thermally conductive AlN substrate.
（従来の技術）
一般にオーバレイトランジスタなどの高周波高出力トラ
ンジスタを実装した半導体装置においては１．半導体か
らの発熱が大きく、この熱を放散させる必要がある。こ
のため半導体を実装する基板に高熱伝導性のＢｅＯ基板
を用いることが行なわれている。(Prior Art) Generally, in a semiconductor device mounted with a high frequency, high output transistor such as an overlay transistor, 1. Semiconductors generate a lot of heat, and it is necessary to dissipate this heat. For this reason, a highly thermally conductive BeO substrate is used as a substrate on which a semiconductor is mounted.
（発明が解決しようとする問題点）
このＢｅＯ基板は優れた高熱伝導性を有するものの高価
で、しかも毒性があるため取扱いに注意を要するという
問題があった。また半導体のＳｉチップと熱膨張係数に
大きな差があるためＳｉチップのマウント時に熱応力が
生じ、従って小さなチップしか実装できず、出力に制限
を受けていた。(Problems to be Solved by the Invention) Although this BeO substrate has excellent high thermal conductivity, it is expensive and has the problem of being toxic and requiring careful handling. Furthermore, since there is a large difference in thermal expansion coefficient from that of a semiconductor Si chip, thermal stress occurs when mounting the Si chip, and therefore only small chips can be mounted, which limits output.
本発明はＡｌＮ基板にＱｕ板を接合した基板が高熱伝導
性でしかも熱膨張係数がＳｉチップと近似していること
に着目してなされたもので、高出力で信頼性が高くしか
も安価な半導体装置を提供することを目的とする。The present invention was developed based on the fact that a substrate made by bonding a Qu plate to an AlN substrate has high thermal conductivity and has a thermal expansion coefficient similar to that of a Si chip. The purpose is to provide equipment.
［発明の構成］
（問題点を解決するための手段）
本発明は上記目的を達成するため、ＡｌＮ基板の両面に
ＣＬＩ板を接合し、一方のＣｕ板上にＳｉチップを接合
し、他方の面を金属板に接合してなることを特徴として
いる。[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention has CLI plates bonded to both sides of an AlN substrate, a Si chip bonded to one Cu plate, and a Si chip bonded to the other Cu plate. It is characterized by its surface being joined to a metal plate.
（作用）
このように半導体基板にＣｕ板が接合されたＡλＮ基板
を使用することにより放熱性に優れＳｉチップとのマウ
ント性に優れた、信頼性の向上した高出力の半導体装置
を得ることができる。(Function) By using an AλN substrate in which a Cu plate is bonded to a semiconductor substrate in this way, it is possible to obtain a high-output semiconductor device with improved heat dissipation, excellent mountability with a Si chip, and improved reliability. can.
（実施例） 次に本発明の実施例について説明する。(Example) Next, examples of the present invention will be described.
実施例
常圧焼結法により得られた熱伝導率１５０Ｗ／ｍに以上
、表面粗さ２〜５μｍのＡｌＮ基板（大きさ５０Ｔｌｌ
ＴＩＸ５０ＴＯＴｌｌＸ Ｏ，３〜１．０ｍｍ）を空気
中で、１０００〜１３００℃に加熱して表面に１〜２μ
ｍ厚のアルミナの酸化層を形成した。Example An AlN substrate (size 50 Tll) with a thermal conductivity of 150 W/m or higher and a surface roughness of 2 to 5 μm obtained by the pressureless sintering method was used.
TIX50TllXO, 3-1.0mm) is heated to 1000-1300℃ in air to coat the surface with 1-2μ
An oxide layer of alumina with a thickness of m was formed.
次いで厚さ０．０５〜０．４０ ｍＴｌ１．好ましくは
ｏ、ｉ〜０．２牝のタフピッチ電解銅からなるＣｕ板を
ＡｌＮ基板の両面に接触させ、窒素中でＣＬＩの融点（
１０８３℃）以下、Ｃｕ−０の共晶温度（１０６５℃）
以上、例えば１０７０℃に加熱して両者を接合した。Then the thickness is 0.05-0.40 mTl1. Preferably, a Cu plate made of tough pitch electrolytic copper of o.
1083℃) or less, the eutectic temperature of Cu-0 (1065℃)
As described above, both were bonded by heating to, for example, 1070°C.
その後２ｎｎ＋＋Ｘ ２ｍｍの大きさに切断し、図に示
すように得られたＡｌＮ基板１上のＣｕ板２に厚さ１〜
３μｍのＮｉめつき３と厚さ１〜５μｍのＡＬＩめつき
４を施した後、一方の面にはＡｕ−８ｉ半田５によりＳ
ｉチップ６を半田付けし、他方の面はＰｂ−８ｎ半田９
により金属板７に半田付けした。またＡｌｌワイヤ８に
よりＳｉチップ６のボンディングを行った。その後常法
により金属キャップをかぶせて気密封止して半導体装置
を製造した。After that, it was cut into a size of 2nn++X 2mm, and the Cu plate 2 on the obtained AlN substrate 1 was cut into a thickness of 1~2 mm as shown in the figure.
After applying Ni plating 3 with a thickness of 3 μm and ALI plating 4 with a thickness of 1 to 5 μm, S is applied to one side using Au-8i solder 5.
The i-chip 6 is soldered, and the other side is soldered with Pb-8n solder 9.
It was soldered to the metal plate 7. Further, bonding of the Si chip 6 was performed using the All wire 8. Thereafter, a metal cap was placed over the cap to airtightly seal it using a conventional method, and a semiconductor device was manufactured.
このようにして得られた半導体装置はパワーサイクルテ
ストに極めて良好な結果を示し、Ｓｉチップとの整合性
は良好であった。またワイヤボンデインク性も極めて良
好で熱抵抗、過度熱抵抗も小さいものであった。またＡ
ぶＮ基板は大形サイズで加工し、最終工程で所定の小形
に切断したので生産性も良好であった。The semiconductor device thus obtained showed extremely good results in a power cycle test and had good compatibility with the Si chip. The wire bonding property was also very good, and the thermal resistance and transient thermal resistance were also low. Also A
Productivity was also good because the N substrate was processed into a large size and cut into predetermined small pieces in the final process.
またＡｆｌＮ基板にＣ１板を直接接合するかわりに、Ａ
、ｅＮ基板に箔またはペーストなどのＴｉ −Ｃｕ−Ａ
（Ｉｔ等の活性金属を介してＣｕ板を配置し、真空中で
約９００℃に加熱して両者を接合したり、あるいは活性
金属上にざらにＡｇろうを被着してＣＩＪ板を接合して
も接合強度の大きい基板が得られ、従って、これを使用
した半導体装置も同様に特性が良好であった。Also, instead of directly bonding the C1 plate to the AflN substrate,
, Ti-Cu-A such as foil or paste on eN substrate
(A Cu plate is placed through an active metal such as It, and the two are bonded by heating it to about 900°C in a vacuum. Alternatively, a CIJ plate is bonded by roughly coating Ag solder on the active metal.) However, a substrate with high bonding strength was obtained, and therefore, a semiconductor device using this also had good characteristics.
一方、従来のＢｅＯ基板を使用し、ＭＯメタライズおよ
びＮｉめつき、Ａｕめつきを施してＳｉチップを搭載し
た半導体装置では、Ｓｉチップとの整合性が良好ではな
く、また毒性のため小形に切断した基板にメタライズ処
理を施す必要があり、操作が容易ではなかった。On the other hand, in semiconductor devices that use a conventional BeO substrate, MO metallization, Ni plating, and Au plating and mounting a Si chip, the compatibility with the Si chip is not good, and due to toxicity, it is cut into small pieces. It was necessary to perform metallization treatment on the substrate, which was not easy to operate.
［発明の効果］
以上説明したように本発明においては高熱伝導性のＡｌ
Ｎ基板の両面に高熱伝導性のＣｕ板が接合された基板に
Ｓｉチップを搭載したので放熱性が極めて優れたものに
なり、またＡｌＮ基板は熱膨張係数がＳｉチップと近似
しているので、Ｓｉチップを半田付けするに際しても不
整合が生じにくく、信頼性の高い高出力のものを得るこ
とができる。量産性に適し、安価に高品質の製品を提供
し得る。[Effect of the invention] As explained above, in the present invention, high thermal conductivity Al
The Si chip is mounted on a substrate with highly thermally conductive Cu plates bonded to both sides of the N substrate, resulting in extremely excellent heat dissipation, and since the AlN substrate has a thermal expansion coefficient similar to that of the Si chip, Even when soldering Si chips, mismatching is less likely to occur, and highly reliable and high output products can be obtained. It is suitable for mass production and can provide high quality products at low cost.
【図面の簡単な説明】 図面は本発明装置の特徴部分を示す断面図である。 １・・・・・・・・・ＡｌＮ基板 ２・・・・・・・・・Ｃｕ板 ３・・・・・・・・・Ｎｉめっぎ ４・・・・・・・・・Ａｕめっき ５・・・・・・・・・ＡＵ−８ｉ半田 ６・・・・・・・・・Ｓｉチップ ７・・・・・・・・・金属板[Brief explanation of drawings] The drawing is a sectional view showing a characteristic part of the device of the present invention. 1・・・・・・AlN substrate 2...Cu plate 3...Ni Meggi 4...Au plating 5・・・・・・AU-8i solder 6...Si chip 7・・・・・・・・・Metal plate
Claims (6)
板上にＳｉチップを接合し、他方の面を金属板に接合し
てなることを特徴とする半導体装置。(1) Cu plates are bonded to both sides of the AlN substrate, and one Cu plate is bonded to both sides of the AlN substrate.
A semiconductor device comprising a Si chip bonded to a plate and the other side bonded to a metal plate.
第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the bonding is by soldering.
求の範囲第１項記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the Cu plate is directly bonded to the AlN substrate.
ている特許請求の範囲第１項または第２項記載の半導体
装置。(4) The semiconductor device according to claim 1 or 2, wherein the Cu plate is bonded to the AlN substrate via an active metal.
４項記載の半導体装置。(5) The semiconductor device according to claim 4, wherein the active metal is a titanium-based metal.
、半田付けはこれらのめつきを介して行われている特許
請求の範囲第２項ないし第４項のいずれか１項記載の半
導体装置。(6) The semiconductor device according to any one of claims 2 to 4, wherein the Cu plate is plated with Ni and Au, and soldering is performed through these platings. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6189486A JPS62219546A (en) | 1986-03-19 | 1986-03-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6189486A JPS62219546A (en) | 1986-03-19 | 1986-03-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62219546A true JPS62219546A (en) | 1987-09-26 |
Family
ID=13184304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6189486A Pending JPS62219546A (en) | 1986-03-19 | 1986-03-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62219546A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5559369A (en) * | 1989-10-02 | 1996-09-24 | Advanced Micro Devices, Inc. | Ground plane for plastic encapsulated integrated circuit die packages |
| US6111308A (en) * | 1991-06-05 | 2000-08-29 | Advanced Micro Devices, Inc. | Ground plane for plastic encapsulated integrated circuit die packages |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5848926A (en) * | 1981-09-18 | 1983-03-23 | Hitachi Ltd | Insulated type semiconductor device |
| JPS617647A (en) * | 1984-06-21 | 1986-01-14 | Toshiba Corp | Circuit substrate |
-
1986
- 1986-03-19 JP JP6189486A patent/JPS62219546A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5848926A (en) * | 1981-09-18 | 1983-03-23 | Hitachi Ltd | Insulated type semiconductor device |
| JPS617647A (en) * | 1984-06-21 | 1986-01-14 | Toshiba Corp | Circuit substrate |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5559369A (en) * | 1989-10-02 | 1996-09-24 | Advanced Micro Devices, Inc. | Ground plane for plastic encapsulated integrated circuit die packages |
| US6111308A (en) * | 1991-06-05 | 2000-08-29 | Advanced Micro Devices, Inc. | Ground plane for plastic encapsulated integrated circuit die packages |
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