JPS62219031A - Interruption control system - Google Patents

Abstract

PURPOSE:To easily select a vector interruption and an auto-vector interruption by selecting the vector interruption or the auto-vector interruption according as a sublevel is outputted or not and performing the interruption processing. CONSTITUTION:When an interruption device I/O 4 which causes the auto-vector interruption outputs a signal INT1, encoded main levels IPL2-IPL0 are inputted to a processor 1, and the processor 1 outputs a data strobe signal DATB after outputting an acceptance permission signal IACK and main levels (A1-A3) similarly to the vector interruption. The signal INT1 is not assigned to another I/O, and the sublevel is not outputted. Therefore, a gate 7 outputs an auto-vector interruption command signal VPA when the signal DSTB is outputted, and the processor 1 generates a vector number corresponding to INT1 and performs the address conversion and refers to a vector to start the interruption processing. The sublevel is monitored to discriminate the auto-vector interruption or the vector interruption in this manner, and the I/O side selects an interruption means optionally.

Description

[Detailed Description of the Invention] [Summary] A first interrupt processing means (hereinafter referred to as auto-vector interrupt) in which a processor automatically generates a vector number corresponding to the main level, and a vector number to the corresponding main level interrupt device. a second interrupt processing means (hereinafter referred to as vectored interrupt) for responding to This is an interrupt processing method that responds with a number, and is characterized in that the interrupt processing is performed by selecting either a vectored interrupt or an auto-vectored interrupt depending on whether a sublevel is output or not. ] The present invention relates to improvements in interrupt control methods.

In a processor that has both auto-vector interrupt processing and vectored interrupt processing, the interrupt device (hereinafter referred to as l10) that performs auto-vector interrupts must output an interrupt signal of a predetermined main level and an auto-vector interrupt command to the processor. .

On the other hand, the interrupt level at which auto-vectored interrupts are performed cannot be used for vectored interrupts, so it is inconvenient to freely allocate vectored interrupts and auto-vectored interrupts as an interrupt control device that targets various Ilo. there were.

For this reason, there is a need for an interrupt control system that can easily set interrupt means.

[Conventional technology]

FIG. 3 (al is a block diagram of a conventional interrupt control unit, and FIG. 3(b) is an explanatory diagram of a conventional interrupt process showing a flowchart diagram and a time chart diagram in correspondence.

It should be noted that throughout the figures, signal names with a "-" symbol above them represent negative logic.

Interrupt processing analyzes interrupt signals from I10 devices and executes corresponding interrupt processing programs.The interrupt level indicating the priority and the vector number for analyzing the address of the interrupt processing program are Set.

There are usually 8 interrupt levels from INTO to INT7 (
Three sets of interrupt signals (IPL
2 to IPLO) is input to the processor.

On the other hand, vector numbers can be automatically generated depending on the main level (auto-vector interrupt) or notified by the (10) device (vector interrupt), and once the vector number is determined, it is converted into a vector address.

This vector [2b in FIG. 3 (al)] stores the start address of the interrupt processing program (2a) at the address corresponding to the vector number, and thereby enables interrupt processing.

The details of the above interrupt processing will be explained below with reference to FIGS. 3(a) and 3(b).

Note that the following explanation is an example that uses sublevels.

In FIG. 3(a), l103 is a vector interrupt, l1
04 is an I10 device that performs auto-vector interrupts, each of which is given an interrupt level of INT6°lNTl.

(Vector interrupt) When an interrupt cause occurs in 1103 and the interrupt signal 1NT6 is output, the IP encoded by encoder 5
L2. Interrupt signals having three sets of main level information, iPLL and IPLO, are input to the processor 1.

When the processor 1 is ready to accept interrupt processing, it returns its main level information to each address line A1 to A3 110 along with an acceptability signal (IACK signal).

The I 103 that has issued the interrupt signal reads the contents of the address lines A1 to A3 based on the IACK signal, and if it is at its own main level, outputs the assigned sublevel to the address lines A8 to A15.

This sublevel is assigned to 8 bits A8 to A15, and each 110 reads the contents of A8 to A15 based on the DSTB signal, and if its own sublevel is higher, it is sent to data lines DO to D7. Output vector number.

When there is no autovector interrupt command (described later), processor 1 executes DO~ based on the DTAC signal output from l103.
Read the contents of D7 and recognize the vector number.

(Autovector Interrupt) When an interrupt cause occurs at 1104 and the lNTl signal is sent to the encoder 5, IPL2 to IPLO are input to the processor 1.

Similarly to the vectored interrupt, the processor 1 outputs the IACK signal and main level information, but the IACK signal is lN.
Tl is ANDed by gate 6, and its output sends an auto-vector interrupt command (VPA signal) to processor 1.
will be notified.

Based on the VPA signal, the processor 1 determines that the autovector is in the evening, and generates a vector number assigned to lNTl using a table (not shown) provided in the processor 1.

Note that, as shown in FIG. 3(b), since priority is given to the autovector interrupt operation, that interrupt level cannot be used for vector interrupts.

[Problem that the invention seeks to solve]

As explained above, auto-vector interrupts require a means to provide an auto-vector interrupt command for each interrupt level, and to disable auto-vector interrupts for that interrupt level when vector interrupts are used, which can be assigned to any I10 device. was inconvenient.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide an interrupt control method that can easily select between vectored interrupts and autovectored interrupts.

[Means for solving problems]

For the above purpose, the interrupt control method of the present invention is provided with means for verifying the presence or absence of a sublevel, as shown in the principle explanatory diagram of FIG. , is equipped with a means for outputting an automatic vector generation command to the processor, and after the processor accepts a main level interrupt signal, performs vector interrupt processing using the output sublevel, and when the sublevel is not output, an autovector interrupt It performs processing.

[Effect]

In an interrupt processing method that performs vector interrupts based on sublevels, as described above, autovector interrupts do not output sublevels, and vectored interrupts are not used for that interrupt level.

Therefore, after the interrupt is accepted, the address lines A8 to A
If the sublevel is not output to 15, it is recognized as an autovector interrupt.

Therefore, gates are provided which receive the address lines A8 to A15 as inputs, and when all sublevels are "1" (negative logic), a notification is sent to the processor as an autovector interrupt command.

As described above, there is no need to create an autovector interrupt command corresponding to the interrupt level of the autovector interrupt, and vector interrupts and autovector interrupts can be easily used in combination.

〔Example〕

An embodiment of the present invention will be described with reference to FIG.

FIG. 2(a) is a block diagram of the interrupt control section of the embodiment;
Figure (b) is an operation time chart diagram of the embodiment.

In FIG. 2(a), 7 is a gate that receives eight sets of address signals from address lines A8 to A15, an IACK signal, and a data strobe DSTB signal, and performs an AND of each negative logic signal. There are things.

That is, since the sublevel output based on the IACK signal is valid in the DSTB signal, the presence or absence of the sublevel is determined based on this.

The output of this gate 7 is connected to the VPA signal input terminal of the processor 1, and is configured so that an autovector interrupt command is notified to the processor 1 when the IACK signal and the DSTB signal are present and there is no sublevel output.

Note that the same reference numerals represent the same objects throughout the plan.

The interrupt analysis processing operation will be explained below.

(vector interrupt) This is the same as the conventional example, and is as follows.

(1) When the l103 inputs the INT6 signal to the encoder 5, the encoded main levels IPL2 to IPL
An interrupt is notified to processor 1 by 0.

(2) Having received the IACK signal, l103 reads the data of A1-A3 and outputs the sub-level if it is the main level corresponding to INT6.

Next, data of 88 to A15 is read based on the DSTB signal, and if the own sublevel is higher, Do-D7
Outputs the vector number.

(Autovector interrupt) (1) When I/04 outputs lNTl, the encoded main levels IPL2 to IPLO are input to processor 1, and processor 1 outputs INTl as well as vectored interrupts.
After outputting the ACK signal and main level (At-A3)
Outputs STB signal.

(2) INT1 is not assigned to any other Ilo, so no sublevel is output.

Therefore, the gate 7 is connected to the DS as shown in FIG. 2(b).
When the TB signal is output, the auto vector interrupt command V
Outputs PA signal.

As a result, processor 1 generates a vector number corresponding to lNTl, converts the address, refers to the vector, and starts interrupt processing.

As mentioned above, the sublevel is monitored to determine whether the interrupt is an autovector interrupt or a vector interrupt, and therefore the I10 side can arbitrarily select the interrupt means.

〔Effect of the invention〕

The present invention provides a simple interrupt control method that distinguishes between auto-vectored interrupts and vectored interrupts based on whether a sublevel is output from each I10, and arbitrarily selects between auto-vectored interrupts and vectored interrupts. The effects that can be achieved are extremely large.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the embodiment, FIG. 2(a) is a block diagram of the interrupt control section of the embodiment, and FIG.
(bl is a time chart diagram of the embodiment, FIG. 3(a) is a block diagram of a conventional interrupt control unit, and FIG. 3(b) is a diagram explaining conventional interrupt analysis processing. In the figure, 1 is a processor , 2 is the memory, 2a is the interrupt processing program, 2b is the vector, 3 is Ilo of the vector interrupt, 4 is I of the auto vector interrupt, 10°5 is the encoder, 6 is the gate, DTACK -]--f Example of actual run No Drops or Mei Kui 14 Nayat Fallen Figure 2 (Meeting of Shikaku Bundle MM Uri Rod ψ Right Y) ゛ Tips 7M Figure 3 (cL
)

Claims (1)

[Claims] When a main level interrupt signal indicating priority is received,
A first interrupt processing means that generates a vector number corresponding to the main level based on a vector automatic generation command, and a second interrupt processing means that returns the main level information and causes the interrupt device to respond with the vector number. In the processor, when an interrupt device receives the returned main level information, it outputs a sublevel representing a priority within the main level, and an interrupt device with a higher sublevel responds with the vector number. and means (8) for verifying the presence or absence of the sub-level and outputting the vector automatic generation command to the processor when the sub-level is not output within a predetermined time from the main level return; An interrupt control method characterized in that after a processor receives a signal, second interrupt processing is performed based on the output sublevel, and when the sublevel is not output, first interrupt processing is performed.