KR930010755A - Method for Diagnosing Interrupt Function Failure and Recovering Data between Processors in Multiprocessor - Google Patents

Method for Diagnosing Interrupt Function Failure and Recovering Data between Processors in Multiprocessor Download PDF

Info

Publication number
KR930010755A
KR930010755A KR1019910019574A KR910019574A KR930010755A KR 930010755 A KR930010755 A KR 930010755A KR 1019910019574 A KR1019910019574 A KR 1019910019574A KR 910019574 A KR910019574 A KR 910019574A KR 930010755 A KR930010755 A KR 930010755A
Authority
KR
South Korea
Prior art keywords
processors
data
control board
memory
system control
Prior art date
Application number
KR1019910019574A
Other languages
Korean (ko)
Other versions
KR940006834B1 (en
Inventor
이재경
손덕주
이종광
Original Assignee
경상현
재단법인 한국전자통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 경상현, 재단법인 한국전자통신연구소 filed Critical 경상현
Priority to KR1019910019574A priority Critical patent/KR940006834B1/en
Publication of KR930010755A publication Critical patent/KR930010755A/en
Application granted granted Critical
Publication of KR940006834B1 publication Critical patent/KR940006834B1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

내용 없음No content

Description

다중처리기 시스템에서 처리기들 간의 인터럽트 기능장애 진단 및 복구자료 산출방법Method for Diagnosing Interrupt Function Failure and Recovering Data between Processors in Multiprocessor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명이 적용되는 하드웨어의 구성도.1 is a block diagram of hardware to which the present invention is applied.

제2도는 본 발명의 전체 흐름도.2 is an overall flow chart of the present invention.

제3도는 인터럽트 송신 절차의 흐름도.3 is a flowchart of an interrupt transmission procedure.

제4도는 인터럽트 수신 절차의 흐름도.4 is a flowchart of an interrupt receiving procedure.

Claims (1)

시스템 제어보드와, 메모리와, 복수의 처리기들을 포함하는 다중처리기 시스템에서 상기 처리기들 사이에 인터럽트의 기능장애를 진단하고 상기 기능장애를 복구하기 위한 자료를 산출하는 방법에 있어서, 상기 시스템 제어보드로부터 작업지시를 받게 된 상기 처리기들이 자신의 고유자원들을 초기화 시킨 후 작업준비가 완료되었음을 상기 시스템 제어보드에 통보하면 인터럽트 송수신 절차를 수행할 수 있도록 상기 처리기들을 상기 시스템 제어보드와 동기시키는 제1단계와, 상기 처리기들에게 각종 형태의 인터럽트들을 송신할 수 있도록 각종 송신용 레지스터들을 제어하고 전송오류가 발생될때 재전송 여부를 판별하여 적합한 조치를 함과 아울러 송신용 레지스터들의 정보를 유효한 자료의 형태로 변환시켜 상기 메모리에 기록관리하는 제2단계와, 수신용 레지스터들로부터 정보를 발췌하고 분류하여 유효한 자료의 형태로 상기 메모리에 기록한 후 이전상태로 복귀하는 제3단계와, 상기 인터럽트 송수신 절차가 완료된 후 상기 처리기들을 상기시스템 제어보드와 동기화 시키고 상기 메모리에 기록된 상기 자료들을 비교 분석하여 고장진단 및 복구를 위해 진단자가 확인할 수 있는 형태의 산출자료를 출력하는 제4단계를 포함하는 것을 특징으로 하는 다중처리기 시스템에서 처리기들간의 인터럽트 기능장애 및 복구자료산출 방법.A method for diagnosing a malfunction of an interrupt between the processors and calculating data for recovering the malfunction in a multiprocessor system including a system control board, a memory, and a plurality of processors, the method comprising: A first step of synchronizing the processors with the system control board to perform an interrupt transmission / reception procedure when the processor receiving the work order initializes its own resources and notifies the system control board that work preparation is completed; By controlling various transmission registers to transmit various types of interrupts to the processors, and determining whether to retransmit when a transmission error occurs, take appropriate measures and convert the information of the transmission registers into valid data forms. A second stage for recording management in the memory A third step of extracting and classifying information from the registers for receiving and sorting the information, writing the data into the memory in the form of valid data, and returning to a previous state; and synchronizing the processors with the system control board after the interrupt transmission and reception procedure is completed. And a fourth step of comparing and analyzing the data recorded in the memory and outputting calculation data in a form which can be checked by a diagnosis person for fault diagnosis and recovery. And recovery data calculation methods. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910019574A 1991-11-05 1991-11-05 Method of generating the diagnosing and recovery data file in multiprocessor system KR940006834B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910019574A KR940006834B1 (en) 1991-11-05 1991-11-05 Method of generating the diagnosing and recovery data file in multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910019574A KR940006834B1 (en) 1991-11-05 1991-11-05 Method of generating the diagnosing and recovery data file in multiprocessor system

Publications (2)

Publication Number Publication Date
KR930010755A true KR930010755A (en) 1993-06-23
KR940006834B1 KR940006834B1 (en) 1994-07-28

Family

ID=19322279

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910019574A KR940006834B1 (en) 1991-11-05 1991-11-05 Method of generating the diagnosing and recovery data file in multiprocessor system

Country Status (1)

Country Link
KR (1) KR940006834B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100516929B1 (en) * 2002-10-23 2005-09-23 한국과학기술정보연구원 Apparatus and method for analyzing task management, and storage media having program thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100516929B1 (en) * 2002-10-23 2005-09-23 한국과학기술정보연구원 Apparatus and method for analyzing task management, and storage media having program thereof

Also Published As

Publication number Publication date
KR940006834B1 (en) 1994-07-28

Similar Documents

Publication Publication Date Title
US6829729B2 (en) Method and system for fault isolation methodology for I/O unrecoverable, uncorrectable error
KR950033759A (en) Nonvolatile Fault Log Acquisition Method in Microprocessor Fault Logging Device and Microprocessor Control
KR870002504A (en) Fault recovery method and apparatus in the calculation system
US6845469B2 (en) Method for managing an uncorrectable, unrecoverable data error (UE) as the UE passes through a plurality of devices in a central electronics complex
CN110147343A (en) A kind of Lockstep processor architecture compared entirely
KR930010755A (en) Method for Diagnosing Interrupt Function Failure and Recovering Data between Processors in Multiprocessor
KR102123616B1 (en) Method and apparatus for parallel journaling using conflict page list
JP2580558B2 (en) Interface device
JP2743562B2 (en) Failure handling method
JPS5875256A (en) Monitoring system for execution instruction processing state
JPH0281259A (en) Fault information freezing system
JP2979553B2 (en) Fault diagnosis method
JPH0448257B2 (en)
JPS60204050A (en) Error recovering system of input/output device
JPS5854698B2 (en) Fault detection method
JPH07152497A (en) Disk control device
KR910012938A (en) RMW transmission method for synchronization of processors
CN118132151A (en) Method for identifying first synchronous exception processor in multiprocessor parallel architecture
JPS5451347A (en) Fault detection system of data processor
KR930011494A (en) FIFO memory test method
JPS59163653A (en) Debug device
JPS6312036A (en) Maintenance diagnosing device
JPS60144142U (en) diagnostic control circuit
JPS5943425A (en) Interface operation check system
Comerford Link systems for multi-computer control of a large process: Part 2—Fault detection

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010627

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee