KR910012938A - RMW transmission method for synchronization of processors - Google Patents

RMW transmission method for synchronization of processors Download PDF

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Publication number
KR910012938A
KR910012938A KR1019890019311A KR890019311A KR910012938A KR 910012938 A KR910012938 A KR 910012938A KR 1019890019311 A KR1019890019311 A KR 1019890019311A KR 890019311 A KR890019311 A KR 890019311A KR 910012938 A KR910012938 A KR 910012938A
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South Korea
Prior art keywords
rmw
interlock
receiving
processor
read
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KR1019890019311A
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Korean (ko)
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KR920000479B1 (en
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박병관
강경용
심원세
기안도
윤남석
윤용호
박진원
임기욱
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경상현
재단법인 한국전자통신연구소
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Priority to KR1019890019311A priority Critical patent/KR920000479B1/en
Publication of KR910012938A publication Critical patent/KR910012938A/en
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Publication of KR920000479B1 publication Critical patent/KR920000479B1/en

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Abstract

내용 없음.No content.

Description

프로세서의 동기화를 위한 RMW 전송 방법RMW transmission method for synchronization of processors

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 동작을 나타내기 위한 블럭도.1 is a block diagram illustrating the operation of the present invention.

제2도는 본 발명의 데이터 전송 버스 요청기의 동작을 나타낸 플로우 챠트.2 is a flow chart showing the operation of the data transfer bus requester of the present invention.

제3도는 본 발명의 데이터 전송 버스 응답기의 동작을 나타낸 플로우 챠트.3 is a flow chart showing the operation of the data transfer bus responder of the present invention.

Claims (1)

다중 처리 시스템에서의 프로세서 동기화를 위한 RMW를 수행함에 있어서, 프로세서(1)와 연결된 데이터 전송 형태 및 발생기 및 데이터 전송 버스 요청기 버스 인터페이스(3)에서는 RMW의 전송 형태인가를 구별하는 단계와, RMW의 읽기 또는 쓰기의 동작인가를 구분하는 단계와, RMW 읽기인 경우에는 인터록 읽기의 동작을 수행한 후 긍정 응답을 전송받는 단계와, RMW의 쓰기인 경우에는 인터록 쓰기 동작을 수행한 후 긍정 응답을 전송받는 단계들에 의하여 동작을 수행하도록 하고, 메모리(4)와 연결된 로킹 전송형태 처리기 및 데이터 전송 버스 응답기 버스 인터페이스(5)에서는 로킹 상태인가를 확인하는 단계와, 인터록 읽기 또는 쓰기인가를 구별하는 단계와 인터록 읽기에 의해 로크된 경우에는 LOCK BUSY를 전송하거나 OK와 데이터를 전송하는 단계들을 수행하는 단계와, 인터록 쓰기에 의해 로크된 경우에는 OK를 전송하면서 로크를 해제하는 동시에 데이터를 쓰거나 ERROR를 전송하는 단계들에 의하여 동작을 수행하도록 함으로써 버스를 점유하지 않은 상태에서 RMW을 수행하도록 한 프로세서의 동기화를 위한 RMW 전송 방법.In performing the RMW for synchronizing the processor in the multi-processing system, the data transmission type and the generator and the data transmission bus requester bus interface 3 connected to the processor 1 may be distinguished from the transmission type of the RMW, and the RMW And a positive response after receiving an interlock read operation in the case of RMW read, and receiving an affirmative response in the case of RMW write, and performing an interlock write operation in the case of RMW read. In order to perform an operation by the steps of receiving and receiving, the locking transmission type processor and the data transmission bus responder bus interface 5 connected with the memory 4 check whether the locking state is in a locked state, and distinguish between whether the interlock is read or written. If locked by step and interlock reading, send LOCK BUSY or send OK and data. And the processor performing the RMW without occupying the bus by performing an operation by the step of releasing the lock while transmitting OK, and writing data or transmitting an ERROR if locked by interlock writing. RMW transmission method for synchronization. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890019311A 1989-12-22 1989-12-22 Rmw transmission method for synchronization of processors KR920000479B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890019311A KR920000479B1 (en) 1989-12-22 1989-12-22 Rmw transmission method for synchronization of processors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890019311A KR920000479B1 (en) 1989-12-22 1989-12-22 Rmw transmission method for synchronization of processors

Publications (2)

Publication Number Publication Date
KR910012938A true KR910012938A (en) 1991-08-08
KR920000479B1 KR920000479B1 (en) 1992-01-14

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Application Number Title Priority Date Filing Date
KR1019890019311A KR920000479B1 (en) 1989-12-22 1989-12-22 Rmw transmission method for synchronization of processors

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KR920000479B1 (en) 1992-01-14

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