KR930020277A

KR930020277A - Data transfer method using shared memory

Info

Publication number: KR930020277A
Application number: KR1019920003636A
Authority: KR
Inventors: 유광섭
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1992-03-05
Filing date: 1992-03-05
Publication date: 1993-10-19

Abstract

본 발명은 2개의 CPU사이에 공유메모리와 레지스터를 이용한 데이타 전송방법에 관한 것이다.The present invention relates to a data transfer method using a shared memory and a register between two CPUs.

본 발명은 송신측CPU(1)가 레지스터(42)의 값을 읽어 데이타를 기록할 공유메모리(3)의 블럭 유무를 검사하는 제1단계(51)와, 상기 제1단계(51) 수행후, 데이타를 기록할 블럭이 없으면 수신측 CPU(2)가 데이타를 읽어 가기를 기다리고, 여분의 블럭이 있으면 데이타를 써넣기 전에 제리스터(4)에 상태를 표시하여 수신측 CPU(2)에 공유메모리(3)가 현재 사용중임을 알리고 나서 데이타를 써넣는 제2단계(52내지53)와, 상기 제2단계(52내지53) 수행후, 데이타를 써넣은 블럭번호를 테일 레지스터(41)에 써넣고 처음으로 리턴하는 제3단계(54)와, 수신측 CPU(2)가 레지스터(41)를 검사하면서 공유메모리(3)의 블럭전체에 대한 데이타를 읽어오면서 레지스터(4)에 데이타를 읽는 중심을 기록하여 송신측 CPU(1)가 감지할 수 있도록 하는 제4단계(61내지 64)에 의해 수행된다.According to the present invention, the first CPU 51 checks the presence or absence of a block of the shared memory 3 in which the transmitting CPU 1 reads the value of the register 42 to write data, and after the first step 51 is performed. If there is no block to write data, it waits for the receiving CPU 2 to read the data. If there is an extra block, the status is displayed on the Jerryster 4 before the data is written. In the second register (52 to 53) for writing data after informing that (3) is currently in use, and after performing the second step (52 to 53), the block number in which the data is written is written into the tail register 41. The third step 54 to return for the first time, and the center of reading data to the register 4 while reading the data for the entire block of the shared memory 3 while the receiving CPU 2 checks the register 41. The recording is performed by the fourth steps 61 to 64 so that the transmitting side CPU 1 can sense it.

Description

Data transfer method using shared memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명이 적용되는데 데이타 전송회로의 구성도.1 is a block diagram of a data transmission circuit to which the present invention is applied.

제4도는 데이타를 송신하는 방법의 흐름도.4 is a flowchart of a method of transmitting data.

제5도는 데이타를 수신하는 방법의 흐름도.5 is a flowchart of a method of receiving data.

Claims

Two CPUs (1, 2) and a shared memory (3) connected to the CPU (1, 2) and a system (address, data, control) bus to transfer data between the two CPUs (1, 2). In the data transfer method applied to a data transfer circuit comprising a register (4) connected to the data bus and the control bus of the system bus connecting the CPU (1, 2) and the shared memory (3) to function as an interface, A first step 51 in which the sending CPU 1 reads the value of the register 42 and checks whether there is a block in the shared memory 3 to write data, and after the first step 51 performs the data, If there is no block to be written, the receiving CPU 2 waits to read the data, and there is an extra block, and the state is displayed in the register 4 before the data is written, so that the shared memory 3 is stored in the receiving CPU 2. A second step (52 to 53) for writing data after notifying that it is currently in use, and the second step (52 to 53) 53) After execution, the third step 54 of writing the block number into which the data is written into the tail register 41 and returning for the first time, and the shared CPU 3 while the receiving side CPU 2 examines the register 41; Is performed by a fourth step (61 to 64) for recording the data in the register 4 while reading the data for the entire block of " Data transfer method.

2. The data transfer method according to claim 1, wherein said sending side CPU (1) writes together an indication of the size of data to be written when writing data to a block of a shared memory (3).

※ Note: The disclosure is based on the initial application.