JPS62217499A - Controller for camera - Google Patents

Abstract

PURPOSE:To improve the reliability of an EEPROM for automatic focusing control over a camera by storing the EEPROM with data which includes an error correction code. CONSTITUTION:The electrically erasable programmable fixed value memory (EEPROM) is stored with data which includes an inspection bit as the error correction code and even if there is an error at the time of reading, the read data is decoded into correct data. For example, data is stored in a memory device 3 after inspection bits (c1-c3) are added through an inspection bit generating circuit 2a, etc., and information bits 7 having no error are outputted through a syndrome generating circuit 4a, an error position specifying circuit 5a, an error correcting circuit 6a, etc. Consequently, even if data has an error when read out of the EEPROM, it is corrected, so the reliability of the data storage is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a camera control device equipped with a microcomputer consisting of a central processing unit ((:PI+)) and a storage device.

(Prior Art) It is known to use a 5-microcomputer in a control circuit that controls a shutter circuit, an aperture circuit, a photometry circuit, an automatic focus detection circuit, a sensor circuit, a display circuit, etc. of a camera. The microcomputer consists of a central processing unit and a storage device, and the storage device stores the control blockrum described in -F and the data necessary for its execution. The microcomputer and each of the peripheral circuits described above are connected by a data bus, and mutually exchange data using control signals. The central processing unit performs predetermined data processing on data stored in the storage device and measurement data from peripheral circuits according to a predetermined program stored in the storage device, and outputs control signals and data according to the results. It is sent to peripheral circuits and controls these peripheral circuits.

Storage devices made of semiconductors include random access memory (RAM), fixed value memory (ROM), and electrically erasable programmable fixed value memory (EEI').
ROM), etc., and each has its advantages and disadvantages.

It is possible to rewrite data to II8 at any time, but a backup power source is always required to maintain the data contents, and if this power supply is cut off, the stored contents will be lost, so the camera control It is not suitable as ROM
does not require a backup power supply and has the best data storage performance, but the data cannot be rewritten and data is usually written all at once during manufacturing as a mask ROM, so it is possible to store data separately according to the characteristics of each camera. data cannot be written. EEPIIOM combines the above-mentioned advantages, requires a backup power supply to retain data, and can electrically rewrite data, but is inferior to ROM in data storage performance. Therefore, E 14 P I
'l OM has poor reliability in applications where data must be retained for a long time after being incorporated into a product, such as a camera control device, and there is a risk of data loss.

<Problems to be Solved by the Invention> One object of the present invention is to improve EEF in a camera control device.
The purpose is to improve the reliability of data stored in ROM.

(Means for Solving the Problems) According to the present invention, this object is achieved in a camera control device equipped with a microcomputer consisting of a central processing unit and a storage device, in which a part of the storage device can be electrically erased. A programmable fixed value memory (EEPROM) is used,
This is achieved by the control data stored in the fixed value memory including an error correction code.

(Function) The basic idea of the present invention is that by using El':PROM as one of the storage devices of a microcomputer for controlling a camera, while taking advantage of the rewritability of data, The purpose of this method is to include an error correction code in the control data to compensate for its drawback in data storage characteristics and improve reliability as a whole.

Next, a method for generating error correction codes will be described.

An error correction code is the original code (information bit) plus check pits created according to a certain rule from the information bits.This check pit generation method allows various error correction iF symbols to be created. can.

Generally, W is used for k bits of information [a, a2...ak].
Bit check bits [clc2...ck] are added, and the entire I (= K + m) pit error correction code V [a, a2--akc, c2--c,
] is generated. The error correction code V is a parity check matrix H
(matrix of size mXI, hereinafter referred to as H matrix) is generated so as to satisfy the following relationship.

H-VT=0 (1) Combination or C+ =)1+i8+ +hrxaz +°' ” +
h l h ak < 3), and the sign can be determined by the H matrix. If the column vectors of the H matrix are determined to be linearly independent of each other, the code generated by this matrix will be a 1-bit error correction code.

As an example, when the information bit = 4 and the inspection pit m = 3, the H matrix is as follows. Using this H matrix, the information bit is [10
10], the check bit is calculated from equation (3) as [
011]. The error correction code V from the information bits and check bits is V=[1010011] (5).

The error correction code V obtained by such calculation is EEF
Store in ROM.

Decryption is performed as follows. First, it is checked whether the word V' read from F and EFROM satisfies the expression (+).

If V' contains an error, equation (1) is not satisfied and H-
(V')T=ST (6), and the syndrome S is derived. The error included in V′ is expressed as E [
e, C2...e! ], then V=V'+E
(7) By substituting equation (5) into equation (4), 5T=H-ET (li) is derived. As can be seen from equation (6), the syndrome S has characteristics due to the error pattern E, and the error pattern can be determined by examining the syndrome.

Error correction is performed as follows. Using equation (5), the error correction code V = [1010011] is F,
Assume that the data stored in the EFROM contains a 1-bit error and that V' = [1000011] is read from the EEFROM. In this case, when the syndrome S is calculated using equation (6), it becomes S=[101. In the case of a 1-bit error as in this example, the value of the column vector of the H matrix corresponding to the error position becomes equal to the syndrome. That is, since ST is equal to the third column of H, the error position is the third hit from the left, and E=[0010000 is derived. Therefore, the IE L/sign V is V=V'
+E=[1010011]. Of these, 4 from the left
Since bits up to bit [1 are the original information bits, the original data becomes [1010].

By using the above error correction algorithm, EEFRO
When data stored in M is read out, even if it contains an error, it can be decoded into correct data, thereby improving the apparent reliability of EEPROM data storage.

(Example) Next, embodiments of the invention will be described.

FIG. 1 is a block connection diagram of an encoder and a decoder for implementing an error correction algorithm performed when storing data in a storage device of a control device according to the present invention. Encoding is performed in the encoder shown in FIG. 1(a) as follows.

The k bits (at to ah) of information bits 1 are sent to the check bit generation circuit 2. The check bit generation circuit 2 generates a check n dot 9 of m bits (c+ to C, . . .). Both the information bit 1-8 and the check bit 9 are stored in the storage device 3. Decoding is performed by the decoder shown in FIG. 1(b). The sign (a, ~ak') of the I (= k + m) bits read from the storage device 3.

C8~cII,') II is sent to the syndrome generation circuit 4. Syndrome generation circuit 4 is syndrome 12
is generated and sent to the error position designation circuit 5. The error position specifying circuit 5 determines the error position from the syndrome 12 and outputs an error pattern 13. The error correction circuit 6 corrects errors from the error pattern 13 and the error-containing information bits IO read from the storage device, and outputs corrected correct information bits 7.

FIG. 2 is a connection diagram showing detailed circuit configurations of the encoder and decoder shown in FIG. 1. Portions corresponding to those in FIG. 1 are given the same symbols. Figure 2 shows 4 bits (aI to a
-+) information bits and 3 bits (c+ to 03) check bits. In the encoder of FIG. 2(a), the check bit generation unit 2 includes exclusive OR circuits 2a, 2b,
2c is used to calculate the above equation (3), and as a result, the check bit c+ + 2 + is obtained from each output.
Output C3. In the decoder of FIG. 2(b), the syndrome generation circuit 4 includes exclusive OR circuits 4a, 4b,
4c and produces a syndrome from its output.

The error position designation circuit 5 selects elements 58 to 5 according to the error position.
One of the outputs of d becomes logic 1, and the others become logic 0. The error correction circuit 6 corrects the error. Among the read information bits a, ~a4'', errors in bits for which the output of the error location designation circuit 5 is logic 1 are corrected, and bits for which the output of the error location designation circuit 5 is logic 0 are output as they are. Ru.

FIG. 3 shows a flowchart of the error correction algorithm in the present invention. FIG. 3(a) shows the encoding process. For information bit 15, which is the original data before encoding, check bits for this data are generated at step 16, and information bits and check bits are stored at step 17. Store in the device. FIG. 3(b) shows the decoding process. At step 18, the data stored in the storage device is retrieved. 19 Syndrome is generated from this data and the read data is 1.
Fl + cut at 20 to see if it is possible. When an error is discovered (S≠0), the error position is detected at 21, and one error is corrected at 22:.

Then, corrected information pits 23 are obtained. If no error is found (S=O), 21 and 22 are skipped and output as is.

By adding or adding a program based on this flowchart to a part of the control block of the camera control device, it is also possible to implement the present invention without changing the hardware.

The data storage method adopted in the present invention is
The present invention is not limited to M, and can be applied regardless of the type of storage device. That is, it is applicable to data for output correction of a photoelectric conversion sensor in an automatic focus detection device, which is usually stored in a ROM or PRIM, and also to film counter data, which is usually stored in a RAM.

(Effects of the Invention) By using the camera control device to which the data storage method according to the present invention is applied, even if an error occurs in the data read from the storage device, it can be corrected and replaced with iTE correct data. Error correction 1 [Errors within the ability can be ignored. Therefore, even a storage device such as Li 14 F ROM, which has a drawback in long-term data retention characteristics, can be incorporated into a camera control device, and its rewritability can be advantageously utilized.

[Brief explanation of drawings]

Fig. 1 shows a block connection diagram of an encoder and a decoder used in a camera control device according to the present invention, and Fig. 2 shows a detailed circuit configuration of the encoder and decoder shown in Fig. 1. The connection diagram shown in FIG. 3 is a flowchart 1 showing the error correction algorithm adopted by the present invention. 1...Information dotu)~, 2...Test pick 1~Generation circuit 3...Storage device, 4...Syndrome generation circuit, 5
・・・j(ri position designation circuit, 6... error correction circuit, 7
...Information dot, 2a, 2b, 2c,
4a, 4b, 4c. 5a, 5b, 5c, Ha, 8b, Bc, 6
d...υ [Alternative OR circuit Figure 1 (α) ? Figure (1 Teguri City Masaki = (spontaneous) April 10, 1988 [1 1986 Patent Application No. 47882 2 Title of invention Camera control device 3, Relationship with the Nagisa Incident without amendment Patent applicant address 3-30-2 Shimomaruko, Inuda-ku, Tokyo Name (+00
) Canon Co., Ltd.] Representative Ryu Kaku 3 Division 4, Agent Address 158 Tokyo [■2-17-3 Okuzawa, Tani-ku (1)
) Column for detailed explanation of the invention in the specification (2) Drawing 6 attached to the application, content of amendments (1) (() (2) from line 12 of page 5 of the specification
Correct with Eq. (b) Expression (7) in the second line of page 7 of the specification %Formula% ” and rST=H−E” in the same fourth line (
8) J to rH・(V') T=H(V+E) T=HV
Correct it as “+HET (3)”. (c) Next to "...can be done." on page 7, line 8 of the specification [that is, HVT=0, and if there is an error, HET=
1 and there is no error, HE"=O." is inserted. (d) Insert `` next to member 7, line 15, 11 of the specification. (2) Amend Figures 2 (a) and (b) attached to the application as shown in the attached sheet. Figure 2 (a)

Claims (2)

[Claims] (1) In a camera control device equipped with a microcomputer consisting of a central processing unit and a storage device, an electrically erasable programmable fixed value memory (EEPROM) is used as part of the storage device; A camera control device, wherein control data stored in a value storage device includes an error correction code. (2) The device according to claim 1, wherein the data is output signal correction data of a photoelectric conversion sensor in an automatic focus detection device of a camera.