JP2008158908A - Memory controller, flash memory system, and control method of flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently correct errors of storage data and restore the corrected data in a flash memory. <P>SOLUTION: Data read from a memory cell array 21 is held in a page register 22. The held data is read by the flash memory controller 3, and inputted to an ECC block 11 within the memory controller 3. The ECC block 11 determines correction data and a column address corresponding to the correction data based on the input data, and accumulates them in a correction register within the controller 3. The correction data accumulated in the correction register is transferred to the page register 22 (the transfer destination of the correction data is specified by the column address accumulated in the correction register) to correct errors contained in the data retained in the page register 22. The corrected data retained in the page register 22 is written to the memory cell array 21. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method.

  In recent years, flash memory, which is a non-volatile storage medium, has been actively developed, and is widely used as a storage medium for information devices (host systems) such as digital cameras. As the data handled by such information devices has increased in capacity, the storage capacity of the flash memory has been increased. For this reason, attention has been focused on NAND flash memories that have a high degree of integration and are easy to increase in capacity.

  The flash memory can be performed in units of memory cells when the memory cells are changed from the erased state (logical value = 1) to the written state (logical value = 0). However, when the memory cell is changed from the write state (logic value = 0) to the erase state (logic value = 1), this is performed only in a predetermined erase unit (block unit) composed of a plurality of memory cells. I can't.

  In the NAND flash memory, the block is composed of a plurality of pages. This page is a processing unit for reading and writing data. However, because the data cannot be overwritten due to the above characteristics, when rewriting the stored data, the rewritten data is different from the original block. Must be written to.

  Further, due to the characteristics of a flash memory, when reading or writing is performed on a certain memory cell, the state of another memory cell that shares the bit line with that memory cell may change. This phenomenon is called a disturb phenomenon, and it is known that the occurrence rate is increased by repeating the write / erase operations on the memory cells. Due to the disturb phenomenon, the data once written changes, and an error is mixed in the data.

In such a case, it is preferable to read the data of the page in which the error is mixed from the flash memory, correct the error, and then write the data to the flash memory again. For example, Patent Document 1 discloses an invention in which, when an error included in data read from a flash memory is detected, the corrected data is written in another block.
JP 2004-272476 A

  However, in the process described in Patent Document 1, data stored in a page in which an error is detected is read from the flash memory and held in a buffer in the memory controller, and after correcting the error included in the data, The corrected data is written to the flash memory. That is, in this process, after one page of data is transferred from the flash memory to the memory controller, one page of data must be transferred from the memory controller to the flash memory. Therefore, the process described in Patent Document 1 is not efficient when the corrected data is stored again in the flash memory.

  The present invention has been made in view of the above circumstances, and provides a memory controller, a flash memory system, and the like that can efficiently correct an error in data stored in a flash memory and save the data in the flash memory again. The purpose is to provide.

To achieve the above object, a memory controller according to a first aspect of the present invention holds a memory cell array composed of a plurality of pages and data to be written to or read from the memory cell array in units of pages. A read instruction that instructs the internal register to read data stored in the first page in the memory cell array, and the internal register based on the read instruction A data copy instruction means for giving a write instruction for instructing to write the data read into the second page different from the first page;
Reading means for reading data stored in the first page from the flash memory via the data bus of the flash memory;
Error correction means for obtaining a correction value of an error included in the data stored in the first page read from the flash memory by the reading means;
Correction data holding means for holding correction data including the correction value in units of bits corresponding to the bus width of the data bus;
Data replacement means for transferring the correction data held in the correction data holding means to the flash memory via the data bus and replacing a part of the data held in the internal register with the correction data; With
When the data stored in the first page includes an error, a part of the data read from the first page to the internal register is the correction data After the replacement, the flash memory is provided with a write instruction for instructing to write to the second page.

  In the memory controller according to the present invention, when an error included in the data read from the flash memory is detected, the correction data for correcting the error portion is the data corresponding to a unit of data transfer to the flash memory. It is held in units of the number of bits corresponding to the bus width of the bus. Further, after the correction data is transferred to the internal register holding the data corresponding to the correction data, and the error included in the data held in the internal register is corrected, the data held in the internal register Are written into the memory cell array. That is, in the memory controller according to the present invention, when an error included in the data read from the flash memory is detected, only the correction data for correcting the error part is transferred to the internal register, and on the internal register. An error in data held in the internal register is corrected.

  The correction data holding unit holds position information indicating a position in the internal register of data to be replaced with the correction data, and the data replacement unit replaces a portion of data corresponding to the position information with the correction data. It is characterized by that.

In order to achieve the above object, a flash memory system according to a second aspect of the present invention provides:
The memory controller and a flash memory are provided.

In order to achieve the above object, a flash memory control method according to a third aspect of the present invention includes:
For a flash memory comprising a memory cell array composed of a plurality of pages and an internal register for holding data to be written to the memory cell array or data read from the memory cell array in units of pages, the first in the memory cell array A first step for instructing reading of data stored in a page to the internal register;
A second step of reading data read into the internal register in the first step from the internal register via a data bus of the flash memory;
A third step for obtaining a correction value of an error included in the data read in the second step;
A fourth step of holding correction data including the correction value obtained in the third step in units of bits corresponding to the bus width of the data bus;
A fifth step of transferring the correction data held in the fourth step to the internal register via the data bus, and replacing a part of the data held in the internal register with the correction data; ,
After a part of the data held in the internal register in the fifth step is replaced with the correction data, the data held in the internal register is transferred to the first page with respect to the flash memory. A sixth step for instructing to write to a second page different from
It is characterized by including.

In order to achieve the above object, a flash memory control method according to a fourth aspect of the present invention includes:
For a flash memory comprising a memory cell array composed of a plurality of pages and an internal register for holding data to be written to the memory cell array or data read from the memory cell array in units of pages, the first in the memory cell array A first step for instructing reading of data stored in a page to the internal register;
A second step of reading data read into the internal register in the first step from the internal register via a data bus of the flash memory;
A third step for obtaining a correction value of an error included in the data read in the second step;
A fourth step of holding correction data including the correction value obtained in the third step in units of bits corresponding to the bus width of the data bus;
A fifth step for instructing the flash memory to read the data stored in the first page into the internal register;
The correction data held in the fourth step is transferred via the data bus to the internal register in which the data read in the internal register in the fifth step is held, and the internal register A sixth step of replacing a part of the data held in the data with the corrected data;
After a part of the data held in the internal register in the sixth step is replaced with the correction data, the data held in the internal register is transferred to the first page with respect to the flash memory. A seventh step for instructing to write to a second page different from
It is characterized by including.

  According to the present invention, it is possible to efficiently correct an error in data stored in the flash memory and save it again in the flash memory.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram schematically showing a configuration of a flash memory system 1 according to an embodiment of the present invention.
As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a flash memory controller 3 that controls the flash memory 2, and is connected to a host system 4 via an external bus 13.

  The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

  The flash memory 2 is a nonvolatile memory and includes a memory cell array 21 and a page register (internal register) 22. Data written to the memory cell array 21 or data read from the memory cell array 21 is temporarily held in a page register (internal register) 22.

  The flash memory controller 3 transfers the data supplied from the host system 4 to the flash memory 2, writes it in the memory cell array 21 via the page register (internal register) 22 in the flash memory 2, and writes it in the memory cell array 21. Data is read through the page register (internal register) 22 and provided to the host system 4. That is, the flash memory controller 3 writes data to the page register 22 or reads data from the page register 22, and the flash memory 2 reads data from the page register 22 to the memory cell array 21 in accordance with a command given from the flash memory controller 3. Is written (copied) or data is read (copied) from the memory cell array 21 to the page register 22.

The address space of the flash memory 2 is composed of “pages” and “blocks (physical blocks)”.
A page is a processing unit of a data read operation and a data write operation performed in the flash memory 2. That is, in the data read operation and data write operation, the memory cells in the memory cell array 21 are selected in units of pages, and data is written (duplicated) from the page register 22 to the memory cells or pages from the memory cells in units of pages. Data is read (copied) from the register 22.

  The physical block is a processing unit of data erasing operation performed in the flash memory 2, and is composed of a plurality of pages. Therefore, in the data erasing operation, data stored in a plurality of pages belonging to the same physical block are erased together.

  The flash memory 2 is written when data is written from the page register 22 to the memory cell array 21, data is read from the memory cell array 21 to the page register 22, and data stored in the memory cell array 21 is erased. Is in a busy state where data, address information, internal commands, etc. cannot be exchanged.

FIG. 2 is a diagram schematically showing the structure of the address space of the flash memory 2.
In the example shown in FIG. 2, the address space of the flash memory 2 is composed of 4096 physical blocks of blocks 0 to 4095. Each physical block includes 64 pages, page 0 to page 63. Further, each page includes a user area 25 of 4 sectors (512 bytes × 4 sectors = 2048 bytes) and a redundant area 26 of 64 bytes.

  Here, the user area 25 is an area for storing user data supplied from the host system 4. The redundant area 26 is an area for recording additional data. The additional data includes an error correction code (ECC) described later, logical address information for specifying a logical block corresponding to the physical block, a block status indicating whether the physical block is a defective block, and the like. It is out.

  Row addresses (0 to 262143) are assigned to all pages included in 4096 physical blocks of the flash memory 2, that is, 262144 pages. A page to be written or read is specified by the row address. Further, in each page, column addresses (0 to 2111) are assigned in units of 1 byte consisting of bits b0 to b7. The position in the page to be written or read is specified by this column address. Here, an area of 2048 bytes (4 sectors) with a column address of 0 to 2047 corresponds to the user area 25, and an area of 64 bytes with a column address of 2048 to 2111 corresponds to the redundant area 26.

  When the data input / output bus (data bus for inputting / outputting data) of the flash memory 2 is 8 bits (8 terminals), the page register (internal register) 22 has 1 byte (8 bits) as described above. The unit column address is assigned, and the data written to the page register 22 is input (supplied) from the flash memory controller 3 to the flash memory 2 in units of 1 byte, and the data read from the page register 22 is flash memory 2 in units of 1 byte. Is input to the flash memory controller 3. When the data input / output bus of the flash memory 2 (data bus for inputting / outputting data) is 16 bits (16 terminals), the data written to the page register 22 is in units of 2 bytes from the flash memory controller 3 to the flash memory. Since the data input (supplied) 2 and read from the page register 22 is output from the flash memory 2 in units of 2 bytes, the page register (internal register) 22 has a column address (0 in units of 2 bytes (16 bits)). -1055).

FIG. 3 is a diagram showing a storage area of a page configured by a user area 25 of 4 sectors (2048 bytes) and a redundant area 26 of 64 bytes. The configuration of the storage area of the page referring to FIG. 3 will be described. The configuration of the page register (internal register) 22 that temporarily holds data to be written to the page or data read from the page is the same as the configuration of the page storage area.
The user area 25 is divided into four areas, ie, a first sector area 251, a second sector area 252, a third sector area 253, and a fourth sector area 254. The first sector area 251 is an area corresponding to column addresses 0 to 511, the second sector area 252 is an area corresponding to column addresses 512 to 1023, and the third sector area 253 is a column address 1024 to 1535. The fourth sector area 254 is an area corresponding to column addresses 1536 to 2047. User data of one sector (512 bytes) supplied from the host system 4 is stored in each of the first sector area 251 to the fourth sector area 254, which are 512-byte areas obtained by dividing the user area 25 into four.

  The redundant area 26 is divided into a common area 260, a first individual area 261, a second individual area 262, a third individual area 263, and a fourth individual area 264. The common area 260 is an 8-byte area corresponding to column addresses 2048 to 2011, and stores logical address information, block status, and the like. Since the logical address information and the block status are management information common to 64 pages included in the physical block, the logical address information and the block status are usually written only in the common area 260 of the first page of the physical block.

  The first individual area 261 is a 14-byte area corresponding to the column addresses 2056 to 2069, and stores information related to data written in the first sector area 251. The second individual area 262 is a 14-byte area corresponding to the column addresses 2070 to 2083, and stores information related to the data written in the second sector area 252. The third individual area 263 is a 14-byte area corresponding to the column addresses 2084 to 2097, and stores information related to the data written in the third sector area 253. The fourth individual area 264 is a 14-byte area corresponding to the column addresses 2098 to 2111, and stores information related to data written in the fourth sector area 254.

  For example, in the first individual area 261, an error collection code corresponding to data stored in the first sector area 251 is stored. Similarly, the error correction codes corresponding to the data stored in the second sector area 252, the third sector area 253, and the fourth sector area 254 are the second individual area 262, the third individual area 263, the fourth Each is stored in the individual area 264.

  The error collection code is generated by the ECC block 11 based on each user data written from the first sector area 251 to the fourth sector area 254, and is transferred from the first individual area 261 to the fourth individual area 264 according to the above correspondence relationship. Written. Therefore, the error included in the user data read from the first sector area 251 is corrected based on the error collection code read from the first individual area 261, and the user read from the second sector area 252 is corrected. The error included in the data is corrected based on the error collection code read from the second individual area 262, and the error included in the user data read from the third sector area 253 is corrected from the third individual area 263. An error included in the user data read from the fourth sector area 254 is corrected based on the read error collection code, and the error included in the user data read from the fourth sector area 254 is corrected based on the error collection code read from the fourth individual area 264. .

  The data amount of the error correction code can be set as appropriate according to the error correction capability. For example, when Reed-Solomon code is used as an error collection code and 10 bits are used as one symbol and an error of 4 symbols or less is to be corrected, an error collection code of 8 symbols (10 bytes) is the first individual area. 261 to the fourth individual area 264 are written respectively.

FIG. 4 is a diagram showing the correspondence between the address space (logical address) on the host system 4 side and the address space (physical address) on the flash memory 2 side.
A physical block address (PBA) is assigned to each physical block in the flash memory 2. The physical block in the flash memory 2 is specified by this physical block address (PBA). When a storage area in the flash memory 2 composed of a plurality of physical blocks is divided into a plurality of zones for management, a physical zone is composed of a plurality of physical blocks, and a physical zone number (PZN) is assigned to each physical zone. ). A physical zone is specified by this physical zone number (PZN). Further, the serial number in each physical zone of the physical block included in each physical zone is called a physical zone block number (PZIBN).

  On the other hand, the address space on the host system 4 side is managed by an LBA (Logical Block Address) which is a serial number assigned to an area divided in units of sectors (512 bytes). The host system 4 designates an access area in the flash memory 2 with this LBA.

  Inside the flash memory controller 3, a group of a plurality of sectors is handled as a logical block. Data corresponding to each logical block is written to the physical block assigned to that logical block. The flash memory controller 3 determines the correspondence between the logical block and the physical block based on the logical address information written in the redundant area 26.

  A serial number assigned to this logical block is called a logical block number (LBN), and a serial number in each logical block of sectors included in each logical block is called a sector number (SN).

  In this embodiment, a combination of 256 sectors is used as a logical block. Therefore, the lower 8 bits of the LBA correspond to the SN, and the upper bit side excluding the lower 8 bits corresponds to the LBN. For example, the LBN of a logical block composed of sectors with an LBA of 0 to 255 is 0, and the LBN of a logical block composed of sectors with an LBA of 256 to 511 is 1.

  Whether the sector specified by the LBA is any of page 0 to page 63 is specified based on the value of the third to eighth bits counted from the lower side of the LBA. Further, which of the first sector area 251 to the fourth sector area 254 is specified based on the value of the lower 2 bits of the LBA (the first and second bits counted from the lower side of the LBA). The For example, a sector whose LBA lower 8 bits are “00000100” to “00000111” corresponds to page 1. Also, the sector whose LBA lower 2 bits are “00” corresponds to the first sector area 251, the sector “01” corresponds to the second sector area 252, and the sector “10” is the third sector area. The sector “11” corresponds to the fourth sector region 254.

  A group of a plurality of logical blocks is called a logical zone. A serial number assigned to the logical zone is called a logical zone number (LZN), and a serial number in each logical zone of a logical block included in each logical zone is called a logical zone block number (LZIBN). Therefore, when the number of logical blocks included in each logical zone is k, the quotient when LBN is divided by k corresponds to LZN, and the remainder corresponds to LZIBN.

  In addition, one physical zone is allocated to each logical zone, and data corresponding to each logical block included in the logical zone is written to a physical block included in the physical zone allocated to the logical zone. Therefore, the number of sectors included in one logical block is set according to the number of sector areas included in one physical block. However, one logical block can be assigned to a plurality of physical blocks. In this case, the plurality of physical blocks are regarded as one physical block, and the number of sectors included in one logical block is determined. Set.

  In the example shown in FIG. 4, one physical block includes 64 pages, and one page is a flash memory corresponding to 4 sectors, that is, one physical block is composed of 256 sector areas. Assumed flash memory. Therefore, 256 sectors correspond to one logical block. Therefore, the logical zone of LZN # 0 configured with 500 logical blocks of LBN # 0 to # 499 corresponds to the 128000 sector area of LBA # 0 to # 127999. Similarly, the logical zone of LZN # 1 corresponds to the 128000 sector area of LBA # 128000 to # 255999, the logical zone of LZN # 2 corresponds to the 128000 sector area of LBA # 256000 to # 383999, ..., the logical zone of LZN # 7 corresponds to the 128000 sector area of LBA # 896000 to # 1023999.

  In addition, the logical zone of LZN # 0 configured with 500 logical blocks of LBN # 0 to # 499 is allocated to the physical zone of PZN # 0 configured with 512 physical blocks of PBA # 0 to # 511. It has been. Similarly, the logical zone of LZN # 1 is assigned to the physical zone of PZN # 1, the logical zone of LZN # 2 is assigned to the physical zone of PZN # 2, ..., the logical zone of LZN # 7 Are assigned to the physical zone of PZN # 7. Here, the number of physical blocks included in the physical zone is greater than the number of logical blocks included in the logical zone because the new data and old data corresponding to the same logical block are separated into separate physical blocks. This is to cope with cases where they coexist, or when a defective block in which data cannot be normally written occurs.

  In the present embodiment, data of logical blocks assigned to the physical block is written in each physical block in the LBA order. Therefore, by managing the correspondence between the physical block and the logical block, the correspondence between the LBA given from the host system 4 and the storage area in the flash memory 2 can be managed.

  In the flash memory 2, data is erased in units of blocks, and data cannot be overwritten on the pages constituting the physical block. Therefore, when rewriting data stored in some pages in a physical block, the rewritten data of the page to be rewritten and the non-rewritten page included in the same physical block as the page to be rewritten Is stored in another erased physical block.

  In such data rewriting, the rewritten data is written in a physical block different from the physical block stored previously. Therefore, each time data is rewritten, the correspondence between the logical block and the physical block changes.

  Therefore, an address conversion table for managing the correspondence between the two at each time point is created and updated whenever the correspondence between the two changes. With this address conversion table, the correspondence between the logical address on the host system 4 side and the physical address in the flash memory 2 is managed. The correspondence relationship between the logical zone and the physical zone is set in advance, and an address conversion table is created for each logical zone.

  The address conversion table is created based on logical address information (information indicating logical blocks having a correspondence relationship) written in the redundant area 26 of the first page of the physical block. As the logical address information, information for specifying a logical block such as a logical block number (LBN) is used. If the correspondence relationship between the logical zone and the physical zone is set in advance, an address conversion table can be created based on the block number (LZIBN) in the logical zone, so LZIBN having a smaller data amount than LBN. Is preferably used as logical address information. In this case, the address conversion table stores the correspondence between the logical zone block number (LZIBN) and the physical zone block number (PZIBN) for each pair of the corresponding logical zone and physical zone.

  The logical address information is information for specifying a logical block corresponding to a physical block in which data is stored in the user area 25. Therefore, for a physical block in which valid data is not stored in the user area 25, Logical address information is not stored.

  Therefore, by determining whether or not logical address information is stored in the redundant area 26, it is possible to determine whether or not valid data is stored in the physical block including the redundant area 26. .

  The redundant area 26 on the first page of the physical block stores a block status indicating whether or not the physical block is a bad block. A physical block that cannot normally perform data writing or the like is determined as a defective block, and a block status indicating that it is a defective block is written in the redundant area 26.

  A physical block that does not store valid data and is not a bad block can be a data write destination. In order to manage such physical blocks as erased blocks (empty blocks), an erased block table is created. This erased block table is created for each physical zone based on logical address information and block status written in the redundant area 26 of the first page of the physical block. An example of the erased block table is a table describing information (PBA, PZIBN, etc.) that can identify an erased block.

  When the data stored in the flash memory 2 is rewritten, the erased block is selected from the erased block table, and the rewritten data is written into the selected erased block. Further, when data is written in the erased block or when data stored in the physical block is erased, the erased block table is updated.

Next, the flash memory controller 3 that controls access to the flash memory 2 will be described.
The flash memory controller 3 supplies data, address information, internal commands and the like to the flash memory 2 to perform each process such as a read process, a write process, a block erase process, and a data copy process.

  Here, the internal command is a command for the flash memory controller 3 to instruct the flash memory 2 to execute processing, and the flash memory 2 operates according to the internal command given from the flash memory controller 3. On the other hand, a command given from the host system 4 to the flash memory controller 3 is called an external command.

  As shown in FIG. 1, the flash memory controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, and an ECC (error collection code) block. 11 and a ROM (Read Only Memory) 12. The flash memory controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

  The microprocessor 6 controls the overall operation of the flash memory controller 3 by controlling the operation of each functional block constituting the flash memory controller 3 according to the program stored in the ROM 12.

  The host interface block 7 exchanges data, address information, external commands, and the like with the host system 4 via the external bus 13. Data or the like supplied from the host system 4 to the flash memory system 1 is taken into the flash memory system 1 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 by the microprocessor 6 is temporarily stored, and is composed of a plurality of SRAM (Static Random Access Memory) cells. In the work area 8, for example, the above-described address conversion table, erased block table, and the like are stored.

  The buffer 9 temporarily stores data read from the flash memory 2 and data to be written to the flash memory 2. That is, the data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data. The data written to the flash memory 2 is held in the buffer 9 until the flash memory 2 is in a writable state.

  The flash memory interface block 10 executes various processes such as data reading and writing in accordance with a command set that defines various processes read from the ROM 12 by the microprocessor 6 (hereinafter referred to as a sequence command). Specifically, the flash memory interface block 10 inputs / outputs data, address information, status information, internal commands, and the like to the data input / output bus of the flash memory 2 according to the sequence command.

  Here, the flash memory 2 includes control signal terminals such as a command latch enable (CLE), an address latch enable (ALE), a write enable (WE), and a read enable (RE). These control signal terminals and the data input / output bus are connected to the flash memory controller 3 via the internal bus 14. The type of information supplied to the data input / output bus is specified by the signal levels of the signals applied to the control signal terminals of command latch enable (CLE) and address latch enable (ALE). Also, information such as data, address information, and internal commands is taken into the flash memory 2 at the timing when the signal level of the signal applied to the control signal terminal of the write enable (WE) transitions, and the control signal terminal of the read enable (RE) The information such as data is output from the flash memory 2 at the timing when the signal level of the signal applied to is changed.

  The ECC block 11 generates an error correction code (ECC) added to data to be written to the flash memory 2 and detects an error included in the read data based on the error correction code added to the read data. correct. In the present embodiment, it is assumed that a Reed-Solomon code is used as an error correction code (ECC), and 10 bits are used as one symbol to correct an error in symbol units.

  The ROM 12 is a non-volatile storage element, and stores a program for controlling the entire operation of the flash memory controller 3, the above-described sequence command, and the like.

  FIG. 5 is a block diagram showing the configuration of the host interface block 7 and the flash memory interface block 10. The host interface block 7 includes a command register R1, a sector number register R2, an LBA register R3, and the like. The flash memory interface block 10 includes a physical block address register R11, a sector number register R12, a counter R13, and the like. Further, the flash memory interface block 10 includes a correction data register (see FIG. 8) described later.

  Information given from the host system 4 is written in the command register R1, the sector number register R2, and the LBA register R3. External commands such as a write command and a read command are written in the command register R1. The number of sectors in the access target area is written in the sector number register R2. In the LBA register R3, the head LBA of the access target area is written.

In the physical block address register R11, the sector number register R12, and the counter R13, information that indicates an access target area in the flash memory 2 based on information written in the sector number register R2 and the LBA register R3 of the host interface block 7 Is written.
That is, when the LBA range specified based on the information written in the sector number register R2 and the LBA register R3 does not extend over a plurality of logical blocks, the physical relationship corresponding to the logical block including the LBA range is included. The physical block address (PBA) of the block (the erased block selected using the erased block search table when data is written in the erased block) is set in the physical block address register R11. Further, the sector number (SN) of the head sector included in the LBA range is set in the sector number register R12, and the number of sectors included in the LBA range is set in the counter R13.

  If the LBA range specified based on the information written in the sector number register R2 and the LBA register R3 extends over a plurality of logical blocks, the above setting is performed for each logical block.

  In operations such as reading and writing, a row address and a column address given to the flash memory 2 are generated based on information set in the physical block address register R11 and the sector number register R12. The value set in the sector number register R12 is incremented (increased by 1) each time user data and additional data for one sector are input to or output from the flash memory 2 by operations such as reading and writing. Then, the value set in the counter R13 is decremented (decremented by 1). The increment of the value set in the sector number register R12 and the decrement of the value set in the counter R13 are repeated until the set value of the counter R13 becomes zero. Accordingly, areas corresponding to the number of sectors initially set in the counter R13 are read or written from the sector areas in the page specified based on the SN initially set in the sector number register R12.

  As in this embodiment, when one page is composed of four sector areas and one physical block is composed of 64 pages, the sector number register R12 has an 8-bit value. SN (0-255) is set. The row address to be given to the flash memory 2 can be obtained by connecting the upper 6 bits of SN set in the sector number register R12 to the lower side of the PBA set in the physical block address register R11. On the other hand, the column address given to the flash memory 2 can be obtained based on the lower 2 bits of SN. That is, any one of the first sector area 251 to the fourth sector area 254 is specified based on the lower 2 bits of SN, and the column addresses of the first sector area 251 to the fourth sector area 254 are set in advance. Therefore, the column address to be given to the flash memory 2 can be obtained based on the lower 2 bits of SN.

  Next, referring to FIG. 6, the data of 4 sectors stored in one page is transferred to a page in a different physical block or a same physical block via a buffer 9 in the flash memory controller 3. A conventional transfer process for transferring (copying) to different pages will be described. The process of reading data stored in the transfer source page will be described with reference to FIG. 6A, and the process of writing data to the transfer destination page will be described with reference to FIG. 6B. For simplicity of explanation, it is assumed that the data read from the flash memory 2 does not include uncorrectable errors (errors of 5 symbols or more).

  In this transfer process, first, information for reading data from the transfer source page is set in the physical block address register R11, the sector number register R12, and the counter R13. That is, the physical block address (PBA) of the physical block including the transfer source page is set in the physical block address register R11. In the sector number register R12, a sector number (SN) corresponding to the first sector area 251 in the transfer source page is set. The counter R13 is set to 4, which is the number of sector areas included in one page.

  Based on these settings, a read command, a row address (a row address corresponding to the transfer source page), and a column address (a column address corresponding to the first sector area 251) are given to the flash memory 2 (of the flash memory 2). Input to the data input / output bus). In response to this, the data stored in the page corresponding to the row address is read (copied) from the memory cell array 21 to the page register 22. The data read to the page register 22 is sequentially output from the data input / output bus at the timing when the signal level of the signal applied to the read enable (RE) terminal changes from high to low. The column address of the data output to the data input / output bus starts from the column address given to the flash memory 2 and is sequentially counted up.

  From the page register 22, data stored in the first sector area 251, error correction code stored in the first individual area 261, data stored in the second sector area 252, data stored in the second individual area 262 Stored error collection code, data stored in third sector area 253, error collection code stored in third individual area 263, data stored in fourth sector area 254, fourth individual area Data and error correction codes are read out in the order of error correction codes stored in H.264.

When reading the error correction code stored in the first individual area 261 after reading the data stored in the first sector area 251, the random data output command and the column address (corresponding to the first individual area 261) Column address) is applied to the flash memory 2 (input to the data input / output bus of the flash memory 2). Data stored in the second sector area 252, error collection code stored in the second individual area 262, data stored in the third sector area 253, error collection stored in the third individual area 263 Similarly, when reading the code, the data stored in the fourth sector area 254, and the error correction code stored in the fourth individual area 264, the random data output command and the column address (the column corresponding to each area) Address) is applied to the flash memory 2 (input to the data input / output bus of the flash memory 2).

  Data read from the first sector area 251, the second sector area 252, the third sector area 253, and the fourth sector area 254 is input to both the buffer 9 and the ECC block 11. The error correction codes read from the first individual area 261, the second individual area 262, the third individual area 263, and the fourth individual area 264 are input to the ECC block 11.

Data read from the first sector area 251 is held in the first buffer area 91 of the buffer 9, and data read from the second sector area 252 is held in the second buffer area 92 of the buffer 9, Data read from the third sector area 253 is held in the third buffer area 93 of the buffer 9, and data read from the fourth sector area 254 is held in the fourth buffer area 94 of the buffer 9. .

  The ECC block 11 detects errors contained in the data read from the first sector area 251 based on the data read from the first sector area 251 and the error collection code read from the first individual area 261. If an error is detected, the error correction is performed on the data held in the first buffer area 91 of the buffer 9. Similarly, data read from the second sector area 252, third sector area 253, and fourth sector area 254 and error read from the second individual area 262, third individual area 263, and fourth individual area 264 Based on the collection code, an error included in each data is detected, and if an error is detected, an error is detected with respect to the data held in the second buffer area 92 to the fourth buffer area 94 of the buffer 9. Make corrections.

  Next, information for writing data to the transfer destination page is set in the physical block address register R11, the sector number register R12, and the counter R13. That is, the physical block address (PBA) of the physical block including the transfer destination page is set in the physical block address register R11. In the sector number register R12, a sector number (SN) corresponding to the first sector area 251 in the transfer destination page is set. The counter R13 is set to 4, which is the number of sector areas included in one page.

  Based on these settings, a data input command, a row address (a row address corresponding to the transfer destination page), and a column address (a column address corresponding to the first sector area 251) are given to the flash memory 2 (flash memory). 2 input / output bus).

  Subsequently, data of one sector (512 bytes) held in the first buffer area 91 of the buffer 9 is sequentially output from the buffer 9. The data output from the buffer 9 is input to the data input / output bus of the flash memory 2 and also input to the ECC block 11. After one sector (512 bytes) of data held in the first buffer area 91 of the buffer 9 is input to the data input / output bus of the flash memory 2, a random data input command and a column address (in the first individual area 261) The corresponding column address) is given to the flash memory 2 (input to the data input / output bus of the flash memory 2). Further, an error correction code output from the ECC block (an error correction code generated based on one sector (512 bytes) data held in the first buffer area 91 of the buffer 9) is input to the data in the flash memory 2. Input to the output bus.

  In the same manner, the data held in the second buffer area 92, the third buffer area 93, and the fourth buffer area 94 of the buffer 9 together with the random data input command and the column address, and the error collection corresponding to these data The code (the error correction code generated by the ECC block 11) is input to the data input / output bus of the flash memory 2. As described above, the data input to the data input / output bus and the error correction code are held in the page register 22.

  Data held in the first buffer area 91, the second buffer area 92, the third buffer area 93, and the fourth buffer area 94 of the buffer 9, and error correction codes (generated by the ECC block 11) corresponding to these data The error correction code) is input to the data input / output bus of the flash memory 2, and then a write command is applied to the flash memory 2 (input to the data input / output bus of the flash memory 2).

  In response to this write command, the data held in the page register 22 is written (copied) to the transfer destination page in the memory cell array 21.

The ECC block 11 converts the input data of 1 byte (8 bits) and the error correction code into symbols of 10 bits and processes them. On the other hand, when an error correction code is output, a 10-bit symbol is converted into 1-byte (8-bit) information and output. One sector of data is converted into 410 symbols by adding 4-bit dummy data set in advance to the end. On the other hand, the 8-symbol error correction code generated by the ECC block 11 is converted into 10-byte information. In addition, the ECC block 11 performs mask processing on the generated 8-symbol error correction code in order to eliminate the mismatch between the data in the physical block from which the stored data has been erased and the error correction code. In this mask processing, when the logical values of all the bits included in the data of one sector are 1 (logical value in the erased state), the logical values of all the bits included in the error correction code of 8 symbols for this data are obtained. Conversion is performed so as to be 1 (logical value in the erased state). That is, when the logical value of all the bits included in the data of one sector is 1 (the logical value in the erased state), the generated error correction code of 8 symbols includes a bit whose logical value is 0. However, after the mask process is performed, the logical values of all bits become 1 (logical value in the erased state). On the other hand, the error correction code read from the redundant area 26 of the flash memory 2 and input to the ECC block 11 is subjected to processing for canceling the mask processing performed at the time of generation.

Next, transfer processing according to the present invention will be described with reference to FIG. In this transfer process, data of four sectors stored in one page is transferred (copied) to a page in a different physical block or a different page in the same physical block. The process of reading data stored in the transfer source page will be described with reference to FIG. 7A, and the process of writing data to the transfer destination page will be described with reference to FIG. 7B. For simplicity of explanation, it is assumed that the data read from the flash memory 2 does not include uncorrectable errors (errors of 5 symbols or more).

  As in the conventional transfer process, information for reading data from the transfer source page is set in the physical block address register R11, the sector number register R12, and the counter R13. That is, the physical block address (PBA) of the physical block including the transfer source page is set in the physical block address register R11. In the sector number register R12, a sector number (SN) corresponding to the first sector area 251 in the transfer source page is set. The counter R13 is set to 4, which is the number of sector areas included in one page.

  Based on these settings, a read command, a row address (a row address corresponding to the transfer source page), and a column address (a column address corresponding to the first sector area 251) are given to the flash memory 2 (of the flash memory 2). Input to the data input / output bus). In response, the data stored in the page corresponding to the row address is read (copied) from the memory cell array 21 to the page register 22. The data read to the page register 22 is sequentially output from the data input / output bus at the timing when the signal level of the signal applied to the read enable (RE) terminal changes from high to low. The column address of the data output to the data input / output bus starts from the column address given to the flash memory 2 and is sequentially counted up.

  Here, the read command given to the flash memory 2 may be a copy back read command or a normal read command, but a copy back read command is more preferable. However, if it is not a normal read command, the normal read command is used in the case of a flash memory having a specification in which the data read to the page register 22 cannot be output via the data input / output bus.

  From the page register 22, data stored in the first sector area 251, error correction code stored in the first individual area 261, data stored in the second sector area 252, data stored in the second individual area 262 Stored error collection code, data stored in third sector area 253, error collection code stored in third individual area 263, data stored in fourth sector area 254, fourth individual area Data and error correction codes are read out in the order of error correction codes stored in H.264.

When reading the error correction code stored in the first individual area 261 after reading the data stored in the first sector area 251, the random data output command and the column address (corresponding to the first individual area 261) Column address) is applied to the flash memory 2 (input to the data input / output bus of the flash memory 2). Data stored in the second sector area 252, error collection code stored in the second individual area 262, data stored in the third sector area 253, error collection stored in the third individual area 263 Similarly, when reading the code, the data stored in the fourth sector area 254, and the error correction code stored in the fourth individual area 264, the random data output command and the column address (the column corresponding to each area) Address) is applied to the flash memory 2 (input to the data input / output bus of the flash memory 2).

  Data read from the first sector area 251, the second sector area 252, the third sector area 253, and the fourth sector area 254 is input to both the buffer 9 and the ECC block 11. The error correction codes read from the first individual area 261, the second individual area 262, the third individual area 263, and the fourth individual area 264 are input to the ECC block 11.

  The ECC block 11 detects errors contained in the data read from the first sector area 251 based on the data read from the first sector area 251 and the error collection code read from the first individual area 261. Perform detection. If an error is detected, error correction is performed on the data read from the first sector area 251 held in the buffer 9. Further, the correction data in byte units including the corrected bits and the column address corresponding to the correction data are written in the correction register R20.

  For example, if some of the bits included in the 15th byte data from the beginning of the 512-byte data read from the first sector area 251 (data having a column address of 0 to 511) are corrected, 15 bytes The eye data (corrected data) is written as correction data in the correction register R20. 14 is written in the correction register R20 as the column address of the correction data together with the correction data.

  After the correction data corresponding to the data read from the first sector area 251 and its column address are written to the correction register R20, an error included in the data read from the second sector area 252 is detected. . This error detection is performed based on the data read from the second sector area 252 and the error correction code read from the second individual area 262. When an error is detected, error correction is performed on the data read from the second sector area 252 held in the buffer 9. Further, the correction data in byte units including the corrected bits and the column address corresponding to the correction data are written in the correction register R20.

  The column address of 512-byte data read from the second sector area 252 corresponds to 512 to 1023. Therefore, when the 15th byte data from the beginning of the data read from the second sector area 252 is written as correction data in the correction register R20, 526 is written in the correction register R20 as the column address of the correction data. It is.

  Similarly, when an error is included in the data read from the third sector area 253 and the fourth sector area 254, the correction data and its column address are written in the correction register R20. The column address of 512-byte data read from the third sector area 253 corresponds to 1024 to 1535, and the column address of 512-byte data read from the fourth sector area 254 is 1536 to 2047. It corresponds to. Also, when an error included in the error correction code read from the redundant area 26 (first individual area 261 to fourth individual area 264) is detected, the corresponding correction data and its column address are stored in the correction register. Written to R20.

  In the transfer process according to the present invention, data read from each of the first sector area 251, the second sector area 252, the third sector area 253, and the fourth sector area 254, as in the conventional transfer process, It is not necessary to hold in different areas (for example, the first buffer area 91 to the fourth buffer area 94) in the buffer 9, and the first sector area 251, the second sector area 252, Data read from each of the third sector area 253 and the fourth sector area 254 may be sequentially overwritten.

  After the correction data and its column address are written in the correction register R20 as described above, the writing of data to the transfer destination page is started. When reading data from the transfer source page, if the data is read using a normal read command instead of a copyback read command, the copyback read command should be used before starting the following processing. The data stored in the transfer source page must be read from the memory cell array 21 to the page register 22.

  Next, information for writing data to the transfer destination page is set in the physical block address register R11 and the sector number register R12. That is, the physical block address (PBA) of the physical block including the transfer destination page is set in the physical block address register R11. In the sector number register R12, a sector number (SN) corresponding to the first sector area 251 in the transfer destination page is set.

  Based on the information set in the physical block address register R11 and the sector number register R12 and the column address of the correction data written in the correction register R20, a data input command for copyback writing, a row address (transfer destination A row address corresponding to a page) and a column address (a column address corresponding to a write destination of the first correction data written in the correction register R20) are given to the flash memory 2 (to the data input / output bus of the flash memory 2). Entered). Subsequently, the first correction data written in the correction register R 20 is input to the data input / output bus of the flash memory 2.

  Thereafter, the second and subsequent correction data written in the correction register R20 and the column address thereof are sequentially input to the data input / output bus of the flash memory 2 together with the random data input command. By this processing, a part of the transfer source data held in the page register 22 is replaced with the correction data held in the correction register R20. By this replacement, the error included in the transfer source data held in the page register 22 is corrected.

  After all the correction data written in the correction register R20 is input to the data input / output bus of the flash memory 2, a write command for copy back writing is input to the data input / output bus of the flash memory 2. In response to this write command, the transfer source data held in the page register 22 is written (copied) to the transfer destination page in the memory cell array 21.

  Next, a process for replacing a part of the data held in the page register 22 with the correction data written in the correction register R20 will be described in detail. In the correction register R20, correction data for correcting the transfer source data held in the page register 22 and a column address corresponding to the correction data are written. That is, correction data in the column address unit of the page register 22 is written in the correction register R20. Therefore, as shown in FIG. 2, when the data input / output bus in which one page is composed of the 2048-byte user area 25 and the 64-byte redundant area 26 is the 8-bit flash memory 2, the correction register R20 The correction data is written in units of 8 bits, and the column address of each written correction data corresponds to one of 0 to 2111.

FIG. 8 shows correction data (correction data # 0 to correction data # n-1) and column addresses (column address # 0 to column address n-1) written in the correction register R20 and data input to the flash memory 2. The correspondence relationship between the column address and correction data input to the output bus is shown. Here, the correction data # 0 to the correction data # n−1 are 1 byte (8 bits) data overwritten on the data held in the page register 22. The position in the page register 22 where the correction data # 0 to correction data # n-1 is overwritten is specified by the column address # 0 to the column address n-1. In the example shown in FIG. 8, the column address # 0 corresponds to the correction data # 0, the column address # 1 corresponds to the correction data # 1, and similarly, the column address # 1 corresponds to the correction data # n-1. n-1 corresponds.

  Next, the column address and correction data input to the data input / output bus of the flash memory 2 will be described. When inputting the first correction data (correction data # 0), the data input command (In-cmd), column address (C-add), row address (R-add), and correction data (Data) are in this order. Input to the data input / output bus. The page to which the data held in the page register 22 is written (transfer destination page) is specified by the column address (C-add) given here. When inputting the subsequent correction data (correction data # 1 to correction data # n-1), a random data input command (In-cmd '), a column address (C-add), and a row address (R-add) And correction data (Data) is input to the data input / output bus in this order.

  In step # 0 shown in FIG. 8, column address # 0 is input as the column address (C-add), and correction data # 0 is input as correction data (Data). In step # 1, column address # 1 is input as column address (C-add), and correction data # 1 is input as correction data (Data). For example, when column address # 0 is 256 and column address # 1 is 511, 1-byte data with column address 256 is replaced with correction data # 0, and 1-byte data with column address 511 is corrected data #. Replaced with 0.

Similarly, the correction data and the column address written in the correction register R20 are input. In step # n-1, the column address # n-1 is input as the column address (C-add), and the correction data (Data ) Is input correction data # n-1. In step # n-1, a write command (P-cmd) is further input. In response to the write command (P-cmd), the data held in the page register 22 is input in step # 0. The data is written (copied) in the page in the memory cell array 21 corresponding to the row address (R-add).

  As described above, in the example illustrated in FIG. 8, n bytes of the 2112 bytes of data held in the page register 22 are corrected data # 0 to corrected data # written in the correction register R20. After being replaced with n-1, the data is written to the transfer destination page. In other words, in this process, n correction data (n-byte correction data) is transferred to the flash memory 2, whereby the error contained in the 2112-byte data held in the page register 22 is corrected. Here, the 2112-byte data held in the page register 22 is data stored in the transfer source page, and therefore, the transfer source is substantially determined by n correction data (n-byte correction data). An error included in the data stored in the page is corrected.

  As described above, in the transfer process according to the present invention, the data read from the transfer source page is held in the page register 22, and when this data has an error, it is held in the page register 22. A part (error part) of this data is replaced with the correction data given from the memory controller side, and the data whose error is corrected by this replacement is written to the transfer destination page. Therefore, by giving only correction data from the memory controller side, it is possible to correct an error in data in which the transfer source page is stored.

  In the above embodiment, the Reed-Solomon code is used as the error collection code. However, the error collection code may be an error collection code of another encoding method such as a BCH code or a Hamming code. Even in the case of error correction codes of other encoding methods, the same applies if correction data in column address units (for example, in units of 1 byte) including the bits to be corrected and their column addresses are written in the correction register R20. Can be implemented.

1 is a block diagram showing a configuration of a flash memory system according to an embodiment of the present invention. It is a figure which shows the structure of the address space of flash memory. It is a figure explaining the structure of the storage area of a page. It is a figure which shows the correspondence of the address space on the host system side, and the address space on the flash memory side. It is a block diagram which shows the structure of a host interface block and a flash memory interface block. It is a figure for demonstrating the procedure of the conventional transfer process. It is a figure for demonstrating the procedure of the transfer process which concerns on embodiment of this invention. It is the figure which showed the correction data and column address which concern on embodiment of this invention, and the correspondence of a column address and correction data.

Explanation of symbols

1 Flash memory system 2 Flash memory 3 Flash memory controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 21 Memory cell array 22 Page register

Claims (5)

For a flash memory comprising a memory cell array composed of a plurality of pages and an internal register for holding data to be written to the memory cell array or data read from the memory cell array in units of pages, the first in the memory cell array A read instruction for instructing reading of data stored in a page to the internal register, and data read into the internal register based on the read instruction are transferred to a second page different from the first page Data copying instruction means for giving a writing instruction for instructing writing;
Reading means for reading data stored in the first page from the flash memory via the data bus of the flash memory;
Error correction means for obtaining a correction value of an error included in the data stored in the first page read from the flash memory by the reading means;
Correction data holding means for holding correction data including the correction value in units of bits corresponding to the bus width of the data bus;
Data replacement means for transferring the correction data held in the correction data holding means to the flash memory via the data bus and replacing a part of the data held in the internal register with the correction data; With
When the data stored in the first page includes an error, a part of the data read from the first page to the internal register is the correction data A memory controller, wherein after the replacement, the flash memory is provided with a write instruction for instructing writing to the second page.   The correction data holding unit holds position information indicating a position in the internal register of data to be replaced with the correction data, and the data replacement unit replaces a portion of data corresponding to the position information with the correction data. The memory controller according to claim 1. Memory controller according to claim 1 or 2,
Flash memory,
A flash memory system. For a flash memory comprising a memory cell array composed of a plurality of pages and an internal register for holding data to be written to the memory cell array or data read from the memory cell array in units of pages, the first in the memory cell array A first step for instructing reading of data stored in a page to the internal register;
A second step of reading data read into the internal register in the first step from the internal register via a data bus of the flash memory;
A third step for obtaining a correction value of an error included in the data read in the second step;
A fourth step of holding correction data including the correction value obtained in the third step in units of bits corresponding to the bus width of the data bus;
A fifth step of transferring the correction data held in the fourth step to the internal register via the data bus, and replacing a part of the data held in the internal register with the correction data; ,
After a part of the data held in the internal register in the fifth step is replaced with the correction data, the data held in the internal register is transferred to the first page with respect to the flash memory. A sixth step for instructing to write to a second page different from
A method for controlling a flash memory, comprising: For a flash memory comprising a memory cell array composed of a plurality of pages and an internal register for holding data to be written to the memory cell array or data read from the memory cell array in units of pages, the first in the memory cell array A first step for instructing reading of data stored in a page to the internal register;
A second step of reading data read into the internal register in the first step from the internal register via a data bus of the flash memory;
A third step for obtaining a correction value of an error included in the data read in the second step;
A fourth step of holding correction data including the correction value obtained in the third step in units of bits corresponding to the bus width of the data bus;
A fifth step for instructing the flash memory to read the data stored in the first page into the internal register;
The correction data held in the fourth step is transferred via the data bus to the internal register in which the data read in the internal register in the fifth step is held, and the internal register A sixth step of replacing a part of the data held in the data with the corrected data;
After a part of the data held in the internal register in the sixth step is replaced with the correction data, the data held in the internal register is transferred to the first page with respect to the flash memory. A seventh step for instructing to write to a second page different from
A method for controlling a flash memory, comprising:

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