JPS62216416A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent the transient power consumption of slightly shifting operation timings of complementarily operated switching circuits in a complementary high voltage output circuit when a high turn-on/off voltage is outputted from the complementary high voltage output circuit in accordance with signal turning- on/off of the logic level through a level converting circuit. CONSTITUTION:Since the turning-on timing of the first control signal SA, namely, the third signal SC and that of the second control signal SB are shifted from each other, the first switching circuit 31 and the second switching circuit 32 are not simultaneously operated. Consequently, a transient current for switching does not flow. In this case, periods tau1 and tau2 are made short enough to prevent the simultaneous switching operation of switching circuits 31 and 32. Thus, an output circuit is obtained which has a simple circuit constitution and has a low power consumption even for switching.

Description

[Detailed Description of the Invention] [Summary] When outputting a high voltage on/off voltage from a complementary high voltage output circuit in response to the on/off of a logic level signal via a level conversion rgJ path, a complementary high voltage output circuit is used. The operation timings of switching circuits that operate complementary to each other in the high-voltage output circuit are slightly shifted to prevent transient power consumption.

[Industrial application field]

The present invention relates to an output circuit equipped with a level conversion circuit, and more specifically, the present invention is directed to an electroluminescent display (
The present invention relates to a semiconductor output circuit equipped with a level conversion circuit that can be used in a driver circuit for an electrostatic display (ELD), a plasma display (PDP), an electrostatic printer, or a communication path switch for an electronic exchange.

[Conventional technology]

A conventional example of an ELD driver circuit is shown in FIG.

The output circuit shown in FIG. 6 includes a level conversion circuit 2'' in which transistors 21 to 24 and an inverter 25 are connected as shown, and a complementary output circuit 3'' in which transistors 31' and 32' are configured in a bush-pull configuration. The output circuit takes out the high voltage vH as an output signal OUT in response to the on/off input signal IN, and applies the output signal OUT to the display electrode of the ELD.

The level conversion circuit 2' cannot directly drive the high voltage switching transistor 31', for example, V)I = 60V, with the logic level input signal IN of about several volts, so the level conversion circuit 2' converts the logic level input signal IN into the switching transistor 31'. You can drive it.

The signal is level-converted to a signal level of 100.degree., and outputs a drive signal SC for the transistor 31'. The output circuit 3'' has a bush-pull configuration, and the transistors 31' and 32'' operate in a complementary manner, resulting in low power consumption in a steady state.

[Problem that the invention seeks to solve]

Complementary transistor 31'' of the output circuit of FIG.

32'' performs a switching operation almost simultaneously in response to the input signal IN. Therefore, there is a problem that a transient current flows during the switching operation and consumes power, and low power consumption is not necessarily sufficient.

ELD driver circuits and the like have high switching frequency, high voltage, and large current, so transient power consumption is also large.

Furthermore, there is a possibility that the semiconductor circuit will be thermally destroyed due to the heat generated by the current during this transient period, and therefore, heat dissipation measures are required.

As a countermeasure to the above, it is possible to turn off the RVH side during the above transition, but this poses a problem of complicating the circuit configuration.

[Means for solving problems]

The present invention solves the above-mentioned problems with a relatively compact circuit configuration.

As illustrated in FIG. 1, the output circuit according to the present invention includes a timing control circuit that outputs a first control signal SA and a second control signal SB based on a signal, and a switching circuit that operates according to the first control signal. a voltage level conversion circuit that outputs a third control signal SC in response to the first control signal; a first switching circuit 31 that operates in response to a third control signal from the voltage level conversion circuit; , a complementary output circuit 3 having a second switching circuit 32 responsive to a second control signal and configured to operate complementary to said first switching circuit.

The operation of the output circuit of FIG. 1 is shown in the timing diagrams of FIGS. 2(al) to (g).

The input signal IN is a logic level on/off signal (FIG. 2(a)). The timing control circuit l receives an input signal IN
Similarly, the timing control circuit l outputs the first control signal SA with an on-pulse that is 11 hours longer than the on-time of the first control signal SA (FIG. 2(b)). A second control signal SB having an on-pulse shorter by τ2 than the input signal IN is output. Therefore, the second control signal SB is shorter than the on-time of the first control signal SA. 1st
The control signal SA is applied to the voltage level conversion circuit 2, and the level is converted into a third control signal SC having a high enough level to drive the first switching circuit 31 of the complementary output circuit 3 (see FIG. 2). (f)). The third control signal SC is applied to the first switching circuit 3L, and the second control signal SR is applied to the second switching circuit 32. The first switching circuit 31 and the second switching circuit 32 are turned on and off in a complementary manner (FIG. 2 (dl, (e)).

Here, the first control signal SA, that is, the third signal S
Since there is a timing difference in on time between C and the second control signal SO, the first switching circuit 31 and the second switching circuit 32 do not operate at the same time. Therefore, when switching. Transient current will no longer flow.

The above-mentioned times τ1 and τ2 are the switching circuit 31°3.
The time should be short enough to prevent simultaneous switching operations.

〔Example] An embodiment of the present invention is shown in FIG.

The output circuit of FIG. 1 is the level converter circuit 2 shown in FIG.
A timing control circuit 1 is added to a circuit including a bush-pull circuit 3' and a bush-pull circuit 3' as a complementary output circuit.

The timing control circuit 1 connects a plurality of inverters 112 to lld in series, in this embodiment, four inverters, that is, an even number, and delays the input signal IN by a time corresponding to the time τ2 of C1 in FIG. A signal delay circuit 11, a series circuit of a NOR gate 12 and an inverter 14 that logically OR the delayed signal and the input signal IN and output the first control signal SA shown in FIG. 2('b), and the signal delay circuit 11. A NAND gate 13 which performs the logical product of the delayed signal and the input signal IN and outputs the second control signal SR shown in FIG. 2 (C1)
and an inverter 15 in series. In this embodiment, τ1 in FIG. 2) and τ2 in FIG. 2(C) are the same value.

The level conversion circuit 2' includes p-channel transistors 21 and 23 to which a high voltage vH, for example, 60.degree.

The level conversion circuit 2' is configured as a kind of flip-flop circuit, and the first control signal SA is sent to the gate of the transistor 22 as a cent input, and the inverted signal S4' of the first control signal SA is sent to the gate of the transistor 22 as a reset input. is applied to the gate of The output signal SC of the level conversion circuit 2' is generated by the first control signal SA and its inverted signal SA' as shown in FIG.
1'.

The Pushpull circuit 3'' as a complementary output circuit includes a push-up side p-channel transistor 31'' that is turned on in response to the "low" level of the high voltage output signal SC to which a high voltage vH is applied, and a second control signal SB. A pull-side n-channel transistor 32' turns on in response to the "high" level of
are connected.

In response to the on/off of the input signal IN, the transistor 3
The signals SB and SC that drive 1' and 32' are the second
Since the on/off operations of the transistors 31' and 32' are generated as shown in FIG.

32' are not turned on at the same time, thereby preventing a transient high voltage from being grounded through transistor 32''.

The waveform of the output signal OUT at this time is similar to that shown in FIG. 2(g).

In the embodiment of FIG. 3, the delay time τ1. An impark series circuit 11 is used to generate τ2, but the delay circuit may be an RC delay circuit 11' using an RC filter as shown in FIG. 4, or a monostable multivibrator 11'' shown in FIG. You can also use

〔Effect of the invention〕

As described above, according to the present invention, an output circuit with a simple circuit configuration that consumes less power even during switching can be provided. As power consumption is reduced, heat generation in the output circuit and destruction of circuit elements due to heat generation are prevented.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an output circuit according to the present invention, FIG. 2 (al to (g)) is an operation timing diagram of the output circuit of FIG. 1, and FIGS. 3 to 5 are diagrams of the output circuit according to the present invention. A circuit diagram showing an embodiment of the output circuit. FIG. 6 is a circuit configuration diagram of a conventional output circuit. (Explanation of symbols) 1: Timing control circuit, 2: Level change 4g! circuit, 3... Complementary output circuit, 11... Signal delay circuit, 11'... RC delay circuit, 11"... Monostable multi-by-break. Fig. 1 Operation timing diagram of output circuit Embodiment of the present invention Output circuit diagram of Fig. 3 Fig. 3 Other embodiment circuit diagram of timing control circuit Fig. 4

Claims (1)

[Claims] 1. A timing control circuit that receives an on/off input signal and outputs a first control signal and a second control signal based on the input signal; a switching circuit that operates according to the first control signal; a voltage level conversion circuit that outputs a third control signal in response to the first control signal; a first switching circuit that operates in response to a third control signal from the voltage level conversion circuit; a complementary output circuit having a second switching circuit responsive to a second control signal and configured to operate complementary to the first switching circuit; switching circuit and second
When one of the switching circuits is switched between on and off operation, the output circuit generates the first and second control signals so that the other switching circuit is in the off operation.