GB1414402A - Bistable circuits - Google Patents

Bistable circuits

Info

Publication number
GB1414402A
GB1414402A GB392573A GB392573A GB1414402A GB 1414402 A GB1414402 A GB 1414402A GB 392573 A GB392573 A GB 392573A GB 392573 A GB392573 A GB 392573A GB 1414402 A GB1414402 A GB 1414402A
Authority
GB
United Kingdom
Prior art keywords
fet
input
output
load
pulse signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB392573A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB1414402A publication Critical patent/GB1414402A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356052—Bistable circuits using additional transistors in the input circuit using pass gates
    • H03K3/35606—Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356069—Bistable circuits using additional transistors in the feedback circuit
    • H03K3/356078—Bistable circuits using additional transistors in the feedback circuit with synchronous operation

Abstract

1414402 FET bistable circuits HITACHI Ltd 25 Jan 1973 [28 Jan 1972] 3925/73 Heading H3T A bistable circuit includes a first load T6 connected to a first FET T1 a second load T8 connected to a series connected second and third FETs T2, T3 and a fourth FET T4 connected as a transfer gate between an input and the input of FET T1. The output of the FET T1 is connected to an input of one of FET T2 or FET T3, the connection point between the second load T8 and the second FET T2 or the third FET T3 is directly connected for feedback to the input of FET T1, a first pulse signal #X is applied to the input of FET T4 and a second pulse signal #X different in phase from the first pulse signal is applied to the input of the other one of FET T2 or FET T3. As shown the FETs are of P channel type and information (V in Fig. 3, not shown) is read in from input FET T10 by a clock control signal #X which causes T4 to conduct so that the input is stored at a (as Va) in the feedback circuit. The potential at b is the inverse (Vb) of that at a and the output (V OUT ) is delayed with respect to the potential (Vb) by the clock signal #2 which makes T5 conduct. In a modification (Fig. 4, not shown) the load FETs T9 and T6 are driven by clock pulse signal #X and a further FET load (T7) is connected in parallel with T6 and FETs (T7) and T8 are driven from clock pulse signal #2 so as to lower the power consumption. The output may be taken from the output electrode of T2 through T5 instead of from b. Inverter circuits may be connected between the output of T4 and a or between the output of T1 at b and the input of T5.
GB392573A 1972-01-28 1973-01-25 Bistable circuits Expired GB1414402A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP987072A JPS5644606B2 (en) 1972-01-28 1972-01-28

Publications (1)

Publication Number Publication Date
GB1414402A true GB1414402A (en) 1975-11-19

Family

ID=11732161

Family Applications (1)

Application Number Title Priority Date Filing Date
GB392573A Expired GB1414402A (en) 1972-01-28 1973-01-25 Bistable circuits

Country Status (5)

Country Link
JP (1) JPS5644606B2 (en)
DE (1) DE2303157A1 (en)
FR (1) FR2182817B1 (en)
GB (1) GB1414402A (en)
NL (1) NL7301187A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5985107U (en) * 1982-11-30 1984-06-08 株式会社吉野工業所 compact container
JPS59111614U (en) * 1983-01-17 1984-07-27 株式会社吉野工業所 compact container
JPS59111608U (en) * 1983-01-17 1984-07-27 株式会社吉野工業所 compact container
JPH0122567Y2 (en) * 1984-09-06 1989-07-06
JPS62192314U (en) * 1986-05-29 1987-12-07
JPS6337113U (en) * 1986-08-28 1988-03-10

Also Published As

Publication number Publication date
FR2182817B1 (en) 1983-06-24
DE2303157A1 (en) 1973-08-23
NL7301187A (en) 1973-07-31
JPS4879960A (en) 1973-10-26
FR2182817A1 (en) 1973-12-14
JPS5644606B2 (en) 1981-10-21

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee