DE2303157A1 - FLIP-FLOP CIRCUIT - Google Patents

Description

Flip-flop circuit (priority: January 28, 1972, Japan, No. 9 870/72)

The invention relates to a flip-flop, in particular a static flip-flop with field effect transistors.

Flip-flops made from field effect transistors with an insulated gate are divided into dynamic and static flip-flops. Even though Dynamic flip-flops are simple in structure, static flip-flops are often preferred because of their storage capacity.

Fig. 1 of the accompanying drawings shows a built up of field effect transistors, known, static flip-flop.

The flip-flop shown in Fig. 1 contains a first inverting stage of transistors T ^ ₁ and T ^ ₂ , a second inverting stage of transistors T.. and Τ., -, a third reversing stage from trai sistors Tj £ and T. “and transistors T. _, Τ, ο uttd · T, _q as transmission or switching gates. The second and third reverse stages are connected in cascade. An output terminal of the third inverting stage is fed back to the one input terminal of the second inverting stage, specifically via the transistor for the transmission gate TQ. The information is held or stored by the feedback loop. The content of the feedback

309834/1023

loop stored information is dependent on the output signal of the first inverter at the time of the conductive state of the transistor for the transmission gate T ₁ -. The gates of the transistors TQ and T ₁ Q are given a clock signal 0 _? out, while a clock signal 0 ,, whose phase differs from that of the signal 0 ₂ , the gate of the transistor T ₁ - is fed.

The flip-flop circuit drives the load transistors Τ .., T ₁ J. and to keep T ₁ 'with a DC voltage Tpp · TJM the power consumption low, are the transistors driven by clock pulses, the difficulty arises that the charge divided will.

As an example it is assumed that the transistor T _{12 is driven} by the clock signal 0 ₁ , while the transistors T ₁₁ - and T ₁ , are driven or controlled by the clock signal 0 _2. 2s it is assumed that the electrical potential that the gate of the transistor T ₁ . is supplied before the transistor T ₁ ^ wirä switched on by the clock signal 0 ₁ in order to write new information in the feedback loop, ground potential is used. Accordingly wiri in the gate capacitance C _{1 of} the transistor T ₁ . and in the capacitance C _{2 of} the wiring between the transistors T ₁ , - and T _1R usar. no charge stored. New information is then written in, the gate capacitance G _{1 of} the transistor T ₁ * being charged so that the gate is brought to the potential Y. Then, when the transistor T. "is switched on by the clock signal 0 ~, the gate potential of the transistor T ₁ - to V. C ₁ Z (C ₁ + C ₂ ) lowered so that the transistor T ₁ . is prevented from working satisfactorily. This phenomenon is the cause of operational errors and limits the value of the wiring capacity. C ₂ .

309834/1023

23Ü3157

The present invention is based on the object To create a static flip-flop made of field effect transistors that can be operated with direct current and clock signals.

The flip-flop according to the invention contains a static section which consists of a first load resistance with a first load resistance connected field effect transistor, a second field effect transistor connected to a second load resistor and a third field effect transistor, which is connected in series with the second field effect transistor. An output terminal of the first field effect transistor is connected to an input of the second or third field effect transistor, while the second Pulse signal is supplied to one input of the other. An output terminal of the second field effect transistor is for feedback connected to an input of the first field effect transistor. In addition to the static section, the flip-flop includes one fourth field effect transistor for a transmission gate, which between an input signal source 'wind the input of the first field effect transistor of the static section is switched and whose input terminal is supplied with the first pulse signal. The first and second pulse signals differ in their phase.

In this flip-flop circuit, the information can always stored in the static section. The registered one new information takes place in such a way that the fourth field effect transistor for the transmission gate is turned on by the first pulse signal. This causes an input signal to be sent to the Input of the first field effect transistor.

The invention will be described in the following on the basis of the preferred exemplary embodiments shown in the accompanying drawings explained in more detail. Show it:

309834/1023

2 shows the circuit diagram of a DC-controlled ·

erten static flip-flops;
Figure 3 is a timing diagram for the flip-flops of Figures 3 and 4;

and
4 shows the circuit diagram of a clock-controlled static flip-flop according to the invention. '

FIG. 2 shows the circuit diagram of a flip-flop made up of field effect transistors, with the load transistors through Throw fed direct current voltage sources.

In the circuit of Fig. 2, the transistors T g, T _g and Tq act as load resistors. The gates are each connected to a DC voltage -Yqq. connected, while the brains are connected to a direct voltage -Υτ) -η.

The drains of the transistors T. and ÜD «are connected to the sources of the load transistors Tg and T _Q , respectively. The source of the TranvSistor T. is connected to ground, the drain of a transistor T- is connected to the source of the transistor Tp. The source of the transistor T ~ is connected to ground. An output terminal of the transistor T .., namely the drain of the same, is connected to the input, i. H; to the gate of transistor T _? connected. The output of the transistor Tp is fed back to the input of the transistor T.

The transistors Tq and T ^ q form an inverter, whose Output signal via a transistor for a transmission gate T. is fed to the input of the transistor T ^.

The transistor Tj- is connected as a transfer gate, that in the conductive state the output signal of one of the transistors T ^ and Tg existing inverting stage of an output terminal OUT feeds.

309834/1023

23U3157

_{A control} clock signal 0 is fed to the gate of the transistor T A and the negated signal 0 is fed to the gate of the transistor T ". The gate of the transistor T ₅ is fed by a clock signal 0 _{2 t}

The mode of operation of the flip-flop of FIG. 2 will be explained with the aid of the timing diagram of FIG.

FIG. 3a shows the clock signal 02 »FIG. 3" b an input signal fed to the input IH, FIGS. 3c and 3d the control clock signals 0 and 0, respectively, FIGS. 3e and 3f the electrical potentials at points a and b of FIG. 2 and FIG.? g, the electric potential at the output OUT. In the timing chart of Fig. 3, the upper level represents each signal ground potential, the lower level of a particular negative potential. the respective transistors are illustrated as p-channel field effect transistors, which become conductive when a certain negative voltage is applied to the gates The invention is of course not restricted to this.

The flip-flop of Fig. 2 operates as follows. While the transistor T- is kept conductive, information is kept static by the feedback circuit containing _{the transistors T 1, Tp and T,.} If thereupon new information is written into the feedback circuit, that is, if the control clock signal 0 assumes negative potential, so that the transmission gate transistor T, becomes conductive, the transistor T, to which the inverted signal of the above signal is impressed, becomes non-conductive. The electrical potential supplied to the gate of transistor T ₁ is brought to the output potential of transistor T _1n , which is independent of the previous state. In this way the new information is written into the feedback circuit. It is statically generated in the feedback circuit

309834/1023

hold until the transmission gate transistor T. then again becomes conductive, causing the next enrollment.

As can be seen from the timing diagram of FIG

the potential V of the gate of the trai sistor T ₁ (potential at point a - ι

a) to the potential of the inverted signal of the input signal V., when the control clock signal 0 falls to a negative value.

Jv

The state is held until the clock signal 0 follows it

Jv.

is brought back to negative potential. The output potential of the transistor T., ie the potential V, at point b is the reverse potential of the potential V at point a. The output _{potential V ou} + is delayed in relation to the potential V, at point b by the clock signal 0 _2.

A static flip-flop is described with reference to FIG which the load transistors are clock-controlled. In Fig. 4 are the same parts are denoted by the same reference numerals as in FIG. 2..

In the embodiment of FIG. 4, the gate of the load transistor T _Q, the control clock signal 0 is supplied. The gate of the load transistor Tg is also fed with the control clock signal. _{A load transistor T 7 is} connected in parallel with the load transistor T 1. The clock signal 0 _{2 is} fed to the gates of the load transistors T _{7 and T_.}

The load transistors, the gates of which are supplied with the predetermined clock signals, operate as follows.

When the clock signal 0 falls to negative potential, so the load transistor T ~ becomes conductive and the output potential

309834/1023

-T-

of the transistor T ₁₀ is determined ". The load transistor T." has a low power consumption, since it is only switched on when new information is written, ie only when the clock signal 0 becomes negative.

The load transistor Tg also becomes conductive when new information is written, as a result of which the potential at point b is determined. If, when writing information, the ground potential of the new information is transmitted to point a via the transmission gate transistor T. and thus point b is at the ground potential of an old item of information, the state of the flip-flop becomes indefinite. This is avoided by the load transistor Tg. The transistor T ₁ is namely in this case non-conductive and the load transistor Tg conductive, so that the potential of the point b is converted from the ground potential of the old information into the negative potential of the new information.

The load transistor T ₇ becomes conductive when the clock signal takes on negative potential. It determines the potential at point b. If the period of the clock signal 0 is long, that is, if the writing interval of information is large, the gate capacitance of the transistor Tp is gradually discharged, so that operational errors occur. In order to avoid this, the load transistor T "charges the gate capacitance of the transistor Tp during the period of the clock signal 0p.

The transistor T _{ß also} becomes conductive when the clock signal 0p assumes a negative potential. This determines the output potential of the transistor Tp.

In the thus-constructed flip-flop circuit of the Übertragungsgatterfcransistor T _fi 1 is not in the feedback loop, as is the case in Fig. 1, that is, the capacity is determined by the transistor T is not _ft as in the circuit of Fig. In the compo-

3Ö9334M023

elements C. and Cp so that operational errors ^ as a result of the Load sharing can be avoided. Hence not just one DC but also clock control possible.

Pie invention is not limited to the embodiments described above, but extends to one Variety of modified embodiments.

For example, the control clock signal 0- the gate of the transistor T _? are supplied, while the output of the transistor T can be connected to the gate of the transistor T ". A pulse signal that differs in phase from the clock signal 0, namely the clock signal 0 ", can be fed to the gate of the transistor Τ" or of the transistor T-. The clock signal can be obtained by delaying the phase of the clock signal 0 ₂ . It can also consist of a signal that is generated by a logic circuit between the clock signal and another pulse signal. The output signal can also be via the transfer gate transistor instead of from point b. T ₁ - from the output of transistor T _? be derived. Various logic gate circuits such as inverters can be connected between the feedback circuit or the static section and the transmission gate transistors T. and T.

Patent claims

30983AM023

Claims (2)

S DA-10 298 PAIENI APPLICATIONS 2 3 U j Ib 7 _r '1. j flip-flop circuit, characterized by a first field effect transistor connected to a first load resistance device, by a second field effect transistor connected to a second load resistance device, by a third field effect transistor connected in series with the second field effect transistor and by a fourth field effect transistor as Transmission gate connected between an input signal source and an input of the first field effect transistor, a first pulse signal being fed to an input of the fourth field effect transistor, an output of the first field effect transistor being connected to an input of the second Ovicr third field effect transistor, a second Iinpulssignal that differs in phase from the first pulse signal, is fed to an input of the third or second field effect transistor, and an output of the second field effect transistor to the input for feedback ang of the first skin effect transistor is connected. 2. flip-flop circuit according to claim 1, characterized in that a fifth field effect transistor as Transmission gate is added to the output of the first or second field effect transistor, with a third pulse signal, which differs in phase from the first pulse signal, an input of the fifth field effect transistor is supplied that the first load resistance device a sixth 309834/1023 - 1 night - Lind seventh field effect transistor contains, which are parallel to each other are connected and the inputs of which are connected to the first and third pulse signals, respectively, and that the second load resistance device contains an eighth field effect transistor, the input of which is fed the third pulse signal. Blank page