DE1807105A1 - Driver circuit for flip-flops - Google Patents

Description

rl.-lng.R.Beafliii. 81-1 ^ .027p 11/5/1900

f I.-Ina. Lamprecht, · «" .. ""

nch.n 22, Staintdorftfr. 1 · I Q Q 7 I U 5

HITACHIv LTDo, Tokyo (Japan) Driver circuit for flip-flops

The invention relates to a driver circuit for operating flip-piopa, which consist of surface field effect transistors.

An attempt has already been made to create flip-flops using circuits with surface field effect transistors, such as, for example, metal insulator half-way field effect transistors, hereinafter referred to as MIS transistors for short ren should be called “build up” An example of such a flip-flop can be found in the USA patent No. 3 36 * 3 115 * The advantage here is that an HIS transistor can easily be integrated into a single semiconducting substrate integrate IWt and that a power requirement as a result of the voltage-controlled design is low. Accordingly, a flip-flop, which is constructed using MIS transistors, proves to be advantageous.

When investigating the Annelderln on the one hand has shown that often when operating such flip-flops as they are described in the above-mentioned USA patent memorandum, a faulty work see 1st, and on the other hand.

8l- (Item I5.76 *) - DfE (O)

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that this faulty working on an undesired lateral relationship sswischen a first input signal pulse supplied by a pulse source and a second the inversion of the first input signal pulse representing input pulse This fact is explained below under Reference to the drawing explained in more detail and in one piece.

The aim of the invention is therefore to provide a driver circuit which prevents incorrect operation of a Plip-Plop consisting of surface field effect transistors, and a transistorized flip-flop is also intended according to the invention arise »which can be operated with a voltage source of low voltage and easily manufactured as a semiconductor body constructed using integrated circuit technology.

For the following description, which serves to further explain the objectives, features and advantages of the invention, reference is made to the drawing; in this are s

PIg. 1 and 10 circuit diagrams for flip-flops each consisting of surface field effect transistors;

2 shows an illustration of the signal waveforms occurring on the input and output sides of this flip-flop *;

Flg. 3 and 4 are a schematic sectional view of in

an integrated half-parent body built-in upper "

surface-Ftldftifekt-Transietoren and a substitute switch 9Q8f28 / 5tr

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picture for one in both figures within the through dashed lines framed area lying trigger circle;

Flg. 5 shows an illustration of the working range of a flip-flop as a function of the voltage supply;

Flg. 6 is a circuit diagram for a conventional driver circuit in FIG Connection with a flip-flop;

FIG. 7 shows the input and output signal waveforms for the circuit of FIG Fig. 6;

8 shows a circuit diagram for a driver circuit according to a first embodiment of the invention in conjunction with a flip flop and

Fig. 9 is an illustration of the input side and the ausgangsseltlgen signal waveforms for the circuit of Figure "8 _O

Xn FIg «1 a conventional flip-flop circuit is shown, which consists of MIS transistors.

In such a flip-flop circuit, the gate capacitance of the MIS transistors is temporarily used as a storage element, so that a binary count can be achieved. Such Flip-flop circuit is far superior to a conventional binary flip-flop counter consisting of bipolar transistors in that than it gets by with a significantly lower number of required components. Another advantage of such

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ORiGJNAL INSPECTED

Flip-flops are made in shape a semiconductor body implemented in integrated circuit technology is much easier because it is made from MIS translators that are better suited to this than any other transistors.

In Flg. 1 denote the reference _{symbols T 1} and T ₅ inverter MXS translators and the reference symbols Tg and T ₁₀ load MIS translators, the drain electrodes of which are each connected via a terminal P to a DC voltage source (voltage V _DD ). The reference symbols T ^ and Tg belong to blocking MIS translators, the Oate electrodes of which are each connected to an input terminal E for the supply of a first input pulse. The reference symbols T * and T ₇ refer to Spelcher MXS transistors, which are each set up to generate a memory effect with the aid of their gate capacitances C ₁ and C ₂ , and the reference _{symbols T 2} and Tg denote trigger MXS- Translator, the Oate electrodes of which are each connected to a second input terminal E * for the supply of a second input pulse · »

By applying input pulses that are phase-shifted by 180 ° from one another, as shown in lines b and a in Flg. 2 are illustrated, at the first and the second input terminal E or E * in FIG. 1, output pulses can be obtained at output terminals A and A ^v , the repetition frequency of which is half as large as the repetition frequency of the input pulses, as shown in FIG Cells d and c in Flg. 2 illustrates 1st. A flip-flop like the circuit of Flg. So 1 is capable of binary counting, and consequently you can use any numerator, any

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arbitrary «shift registers and the like by interconnecting such a Fllp-Fftop« build up tfri 9in9T FMp-Flop chain «

Tür den Vertuen However, an "olohen flip-flop in For" a semiconductor implemented in an integrated holding part Establishing an arrangement is more essential than that ensures that the loss of performance is reduced to a minimum. This is equivalent to old * the requirement that the Flip-flop works satisfactorily even if the Voltage VU *. the supply voltage source is low "

Xst dl «Voltage V _{00 of} the supply voltage source low», the current flowing through the MIS transistors in the conductive state is also reduced, and then the power supply in the «flip-flop itself» is reduced. This is an advantage as a result Can prevent temperature rise in the semiconductor circuit implemented in integrated circuit technology «If a chain of such flip-flops in \;

• inen einsigen semiconducting substrate integrated so it 1st necessary to lower the Lelstungsversehr to "in Mlninun to I a unxulllealge WMmeeneugung prevent au * since the MIS Tranai- 'interfere in such a" inzigen semiconducting substrate with j high Diohte Busantengepaokt are · To meet this requirement, "the flip-flop should therefore not be able to be operated with a low supply voltage"

On the other hand, the flip-flop described above has Inasmuch as the input pulse voltage Vg sun Operation of the blocking MIS transistors T ^ and Tj-, ho h be muä,

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This means * .dad the Oate voltage naohtelligerwelse for 8p> rr-MI3 Tran "iatoren% and T _n over Onea reference potential" more than sum of these transistors Transfer to the conducting state required 1st and will be referred to hereinafter as Sohwellenspannung, the level (for example -1? volt) of the voltage waveform (from example -6 volts) for the storage MIS transformers T * and T "are" uf, since the source electrodes of the blocking MIS translators and Tq alt the gate electrodes of the Spelcher-Mie translators

T * and Τ »are connected.

The reason for this lies in the fact that the p-conducting Berelohe 32 and 42 (91g · 3) 'which form the souroe electrodes S of the translators T' and T ', and the p-conducting areas yy and 4> * which the drain electrode D forming these transistors integrally in a elnslgen semiconducting substrate? 1 are formed of n-leltenden Silizlun and the semiconducting substrate y \ Ui of catfish shown in Fig. 3 through a "AnschluSklenne _O2 old," ins "Besugspotentlal, How about the Brdpotential is connected, the ohmic wave voltages of the transistors T ^ (or T ₂ ) and Tg (or T ^), whose source electrodes S are not directly connected to the absorption potential, through the semiconducting substrate 31 in this way can be influenced so that they are higher than that of the transistor T 1 (or T ₇ ), as can be seen from FIG. 3 and below. Bnpirlse IKSt see that the threshold voltage increases essentially proportionally to the square root of the inverse voltage between the semiconducting substrate and the respective source electrode S. As a result, will

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the threshold voltages of the blocking MIS transistor T ^ (or 1 influenced by the substrate 51 so that they are slightly more than twice the threshold voltage of the storage NIS transistor T «(or T ₇ ), whose source electrode is directly with it connected to the reference potential, as described above.

In contrast, the threshold voltages of the trigger * MIS transiators Tg and Tg are not influenced by the substrate 31 and assume a low value (for example -6 volts) because the switch-on process in which the trigger ^ MIS translator Tg or Tg becomes conductive, is limited only to the case in which the storage MIS transistor T, or T ₇ becomes conductive, although the source electrodes of the MIS transistor Tg and Tg via the current path between the source electrodes and the drain -Electrodes of the storage MIS transit gates T, and T _{7 are} connected to the reference potential Vg).

From the above it can be seen that the The usual flip-flop described above is disadvantageous in that than although the input pulse voltage Vg may be low, the On the other hand, the initial pulse voltage Vg must be high.

Accordingly, in order to be able to operate such a flip-flop with a low input pulse voltage Vg, made the attempt in the usual way, in front of the flip-flop 2 • inen inverter 1 and the blocking MIS transistors

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■ ι

• - ■ - · _ ORiQINALlNSPECTED '

and operate Tg by the output of this inverter as shown in FIG. The arrangement according to FIG. 6 is constructed in such a way that when a low pulse voltage 7 "is applied as an input signal to the inverter I, which is connected to a supply voltage source for a high voltage V ₀₀ ", a high voltage Vg is applied to an output _{terminal A 1} for the operation of the locking MIS-Tranelstoren T ^ and Tg is obtained.

Investigations by the applicant have shown, however, that with this customary method of operating a flip-flop there is the possibility that the inverter transistor T ₂₀ in the inverter 1 can cause the flip-flop 2 to operate incorrectly, which is explained in more detail below.

By applying a pulse voltage v * _B , as shown in cell a in Fig. 7, to the input _{terminal E 1 of} the inverter 1, an inverted pulse voltage Vg is generated in which a delay occurs for the rising and falling parts of the pulse as illustrated in line b in Pig. 7. The rise time or rise time between a time tj at which the inverter transistor Tg _{0 is} turned off and a time tg at which this transistor is turned on depends on the product from the resistance of the inverter transistor T ₂₀ I _n the on mode and the Bingangskapazität the flip-flop 2 or the time constant resulting from ο. This rise time is so great that the locking MIS tranfeiator T ^ (or Tg) when the voltage V- is more negative than the thresholds «

909928/1529

ORIGINAL INSPECTED

«! Ί! Η-! | Ι!> Ιίϊ! IS = ρίξρ, ιΐ!

voltage B _{01 of} the blocking MIS transistor T ₄ (To), dasu tends, while B ^ 2 ^ f * t _Qff (see. Flg. 7) work at the same time old the Trlgger MIS transistor T ₂ (or Tg) gu * which results in a faulty Arbeltewelse *

The ·· Arbeltswels · should now be based on Flg. 7 should be examined in more detail. Dasu Assume dai in the tent point t _1, trigger MIS transistors T ₂ and T g in the conductive state transitioning · · dl then Zustund DAFL · the inverter-IUB Transietoren T ₁ and T ₅ reverse. If the Xhverter-MXS-Translstor T- changes from the non-conductive state to the conductive state, this means that the Xnverter-MXS-Translstor T _{1 is switched off} by the Trlgger-m8-Transformer T ₂ and Tg la tent point tj becoming conductive is switched from the conductive state to the non-conductive state. If the locking MIS transistors T ^ and Tq la tent point t ₁ were now switched off * this did not damage the normal operation of the flip-flop _{are kept} in the switched-on state during the time segment · t Qff »is dl · drain voltage

(i.e. dl * voltage la switched off state) for the Inverterco

^ MIS transistor T ₁ during the ··· time segment «t _{A # M} , over the ^ Spfrr MIS transistor Tj | at the gate llektrode the memory KI8- ^ Transietors T * to "so dal this transistor is turned on instantly (^" On the other side there is the "trigger MIS transistor T ₂ In theseA time in the conducting state · Demsufolge goes the ItaTfr | er | ae transistor T ₁ again from the non-conductive to the conductive state via * This means, however, that the Iwrerter-Ilis transistor T, la time t ₁ from

ORIGINAL INSPECTED

conductive to non-conductive state »however la time t ^ returns to the conductive state, from which a faulty. Arbeltswelse of the flip-flop results.

As a result of such an incorrect operation, the operating range of the flip-flop in terms of the supply voltage is reduced. Flg. 5 illustrates the work area 10 of the flip-flop 2, this work area being indicated by the hatched lines and the supply voltage Vg ₀ for the flip-flop 2 along the horizontal axis and the supply voltage V ₀₀ for the inverter 1 along the vertical axis .

As can be seen from Fig. 5, the _{selectable range for the voltage V 00 is} limited when the voltage _{Vj 30} is lower than -25 VoIt _9, for example, and the operation of the flip-flop 2 stops when the voltage V ₀₀ becomes hotter "the reason for this is" DAFL sunlmmt therein by an increase in the voltage V ₀₀ of the level for the output voltage Vg of the inverter 1 to the value -E _'2 as b in the line in Figure "7 illustrates in dotted lines 1st, so that the time segment t _off in the catfish indicated by the addition synbol t ' _off (tj proportional to t,) expands and thus increases the possibility of incorrect operation. This means, conversely, that the voltage Vjp cannot be made lower than up to one point determined by the definition su of the voltage Vg ₀ limit value, if dl * voltage V _{00 is} lower than, for example, -35 volts.

The invention is based on experiments and investigations

"ORiGiNAL INSPECTED

1807106

which were carried out on the basis of the! the transition of a memory MIS transistor from the conductive in the non-conductive state after applying a pulse voltage the time interval required to the blocking MIS transistor is larger is than that for the transition of a Trlgger MXS transistor from locked time interval required in the conductive state, and it is characteristic of the invention that the trigger MIS transistors are triggered by the output signal of one of the MIS transistors existing inverters are operated and that the inputs of the blocking MIS transistor transistors are combined with those of the inverter.

Ih the following description is the invention of Explained further for the sake of better understanding

In Pig. Figure 8 illustrates one embodiment of the invention, wherein components similar to those of Pig. 6 correspond, are denoted by the same Besugssywbolen as in this figure. According to the invention, an additional inverter 3 is provided which has an inverter MIS transistor T ₅₀ and a load HIS translator T, ^. An output Kleane Ag of the inverter iat connected to the Oate electrodes of the trigger MIS translators T ₂ and Tg of the flip-flop 2, and the gate electrodes of the blocking MIS transistor transistors T ^ and Tg of the flip-flop are connected to the Input terminals E _{2 of} the inverter 3 connected.

Next, the mode of operation of the invention will be explained in more detail. For the sake of simplicity of illustration, it should be assumed that at the input terminal E _{2 of} the inverter 3 and at the Elnganeskletne E for the blocking transistors T> and To

909028/1529

ORIGINAL INSPECTED

j gu ι ι wa

a perfectly square-shaped voltage V_ occurs, as it is illustrated in Fig. 9 in line b Signal "voltage Vg received as it is in Fig. 9la of the line a ¥ transehau · = light" The invested signal voltage Vg is fed to _{the trigger MXS traneietors T g} and Tg as an input signal.

It is assumed that the inverter HIS transistor T 1 of the flip-flop 2 is switched on at the times tj and tg in FIG. 9 and therefore the inverter HIS transistor Te of the flip-flop 2 is switched off in this time interval a voltage Vp arises at the drain electrode of the inverter MIS transistor Tr, and the drain electrode of the inverter-ltlS transistor T "is kept at a BeKUgspotential" At this point in time, since the blocking HIS transistors T ^ and Tg conduct, the drain voltage V _{0 of} the Xhverter-MIS-Traneietore T ₁ stored in the gate capacitance Cg of the storage ~ MIS "transistor T", whereby this transistor is switched on "Besides" the gate voltage for- the memory MIS translator T reduced to zero. After the blocking "MIS transit gates Tj ^ and Tg _{are switched off at time t g} , the Trigg @ r ~ MIS" transistors T _g and Tg are switched on at time t ^. In this way it can in such an arrangement does not come ku such misconduct, wi © is watch it below in the usual arrangement (see "Fig. 7 lines a and to).

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BAO ORIGINAL

Between times t, and t ^ the trigger ~ MIS ~ transistors Tg and Tg oind turned on, so that the inverter MIS Translstor T is eingeechaltct while the inverter "MIS Translstor T dureh _1, Conduction of the transistors IV and Tj becomes conductive. In this way, the states of the inverter MXS _{transistor transistors T 1} and T ₅ are suggested by the pulse voltage introduced into the carrier MIS transistors T ₂ and Tg? _E vice versa.

The Trlgger MIS translators T ₂ and Tg are still in the conductive state between the times t ^ and t-, and at the time t ^ the blocking MTS transistor T ^ (and the f blocking HIS -Transistor Tg) the pulse voltage V _{£ is} applied and switches it on. Accordingly, one could assume that there is a possibility that the Speloher MIS transistor T is switched on while the memory MIS transistor T _{7 is} switched off the time interval between the time at which the pulse voltage V _{£ is} actually applied to the input terminal E until the time at which the memory MIS transistor T is switched on (the sum of the time intervals required to switch on the locking MIS- Transistore T ^ and the memory MIS Transistor T, are required), greater than the time interval t _off illustrated in FIG. 9, so that the memory MIS transistor T _{5 is} switched on and the memory = MIS transistor T »is switched off after the trigger MIS transistors T. ₂ and Tg sum time te are switched off. Accordingly, there is no faulty mode of operation in which the trigger MIS transistor T ₂ and the memory WS transistor T 1 would be switched on simultaneously between the times ti and tc «

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BATH ORIGINAL

irfi & disi ^ sgiäiSÖ mt 'js (MhQr miiglleh ₉ © abs faulty J f · «wc ί ^ over Γ ιί CAo ¹ B arrangements occurs, au ti'" Ί ^T j ^Ί or * ^ - "dorm by Uh®vfi \ hv® n the

i "i Γ ^T "'t -π ^f zi conductive ''Mat& nü, reverslerfe

ι nc'it '> ^Λ fr ι » ¹¹ US"T' ί ^ isfeoren ^ follkoKimen abge =>

^T j J if "it" ti ei erdefi öle f'Figger-MIS

H -ifie & er uhgßßistisltet ₃ and daaaeii w © 3rcl © n die SpsF aiisfcoren febgesehaitetf, wio this cfessi toeeotoieben

That is! "Ige S nit geste-S

. ^{1Γ f} ! 'Rr ¹ ** ^ ^r :? Ji, ii: si' -Ti ₁ ¹ T ₁ . "ι Frfindiißg zum ic * ^ i" -Pi ορέ ¹ Π Λ is tlJ. © c ^, If / PL ' ^Γ ι τ βιβιι a * 8 through the Γ ¹ ? iuui / ^, f .ι / »jlclfcai 2 hinsiehlieh c1s? f SpeissspaiiiMaag gs ^ öftar geraachfc M« L ^r flw ::,: cann than liaor-inimg? mc! dal operation even at low:? · 8p £ ÄiMü§; raöglieh is _s Isa this case corresponds to the isafe limit PIr the voltage Vg _D üem Ilinlmalifsrt, in which άϊθ ii£-3.gg@x »-MIS" TFassi3 £ ^ t®p © n ö @ s sewn-3eioldeten flip-flop "in CIEI * Änoriniüifig ^ © a Fäß ₀ 8 can be operated, and the Un £ ®rgrenze for di © Sparamiig ¥ g _ß srofe-, • speaks the minimum value * at clera the Spei ⁱ r =" US "TFSiisi8tor © n dsa Connected flip-flops in the arrangement shown in FIG. 8 can be operated.

The invention can therefore be used with advantage in cases in which a flip-flop chain is to be constructed from a multiplicity of flip-flops 2 Ä ^p

9O0§'28 / 1529

A flip-flop 2 available output pulse voltage V * _E between successive flip-flop stages is converted into a high pulse voltage Vg, since the subsequent flip-flop must be operated by this output pulse voltage. To meet this requirement, an inverter 1 and the inverter 3 according to the invention must be provided between a first flip-flop stage and one of these following second flip-flop stages. The resulting flip-plop chain can be operated satisfactorily with a lower value for the supply voltage V _DD for the flip-flop than is the case with a conventional arrangement, as can be seen from FIG. From this it follows without further ado "that the power consumption in the flip-flop chain can be reduced by the invention and that the flip-flops can easily be built in integrated circuit technology"

In summary, the invention is characterized in that the locking = MIS Translstoren the flip-flop to the input pulse voltage of the inverter and the Trlgger MIS transistors of the flip-flops are driven by the output pulse voltage of the inverter like. Of course, the invention can also be applied to flip-flops 2 that use a single trigger MXS transistor T ^a ₂ , as shown in FIG. 10 is shown »

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BAD ORlGfNAL

Claims (1)

- 16 claims 1, driver circuit to operate flip-flops with at least one trigger circuit consisting of at least one trigger surface "field effect" transistor, a pair of speakers connected to the trigger field effect transistor. * "Surface field effect transistors and a) pair with the Spsicher-surface & chen "field effect transistors connected locking = Oberi'lächen" FeIdeffekt transistors by a single SpannungsiKipulsquelle, 'characterized by one of a field effect QberffiMehen ~ ~ £ r-ansisfc © r {T} and a _4n LastiiQpedanz (T.- _n ) therefor existing inverters 0} and "by connecting the gate" = electrodes of the trigger surface field effect sensor (T ^ and Tg) to the inverting output '(JW) on ^the> side of the drain electrode of the iriverter ^ Transistor gate (T ^ ₀ ) and the gate electrodes of the blocking surfaces ^ field effect transistors (T «, and Tq) to the input (Eg) on the side of the gate electrode of the driver transistor () 2ο driver circuit according to claim 1 for use in combination with a flip-flop which is constructed from. one cross =. we ism interconnection of the inputs and the outputs of a first and a second each made of an Ofoarflächen-Feideffekt-Transistor- and a load impedance for it - existing inverter stage, from one with the output of the first inverter stage and connected to the input of the second inverter stage and from one first surface ~ field effect ~ transit gate, one with the electricity 909828/1529 ^J ^ BATH ORIGINAL w 17 »· path between its source electrode and its drain electrode between the drain electrode of the first surface = field effect transistor and the output of the first inverter stage inserted second surface field effect transistor and one with the current path between its source electrode and its drain Electrode between the gate electrode of the first surface field effect transistor and the third surface field effect transistor inserted into the output of the first inverter stage and a circuit connected to the output of the second inverter stage and the input of the first inverter stage from a fourth surface field effect transistor, a fifth surface field effect transistor inserted with the current path between its source electrode and its drain electrode between the drain electrode of the fourth surface field effect transistor and the output of the second inverter stage and one with the current path between his sour ce electrode and its drain electrode between the gate electrode of the fourth surface field effect transistor and the output of the second inverter stage, the sixth surface field effect transistor inserted second trigger circuit, characterized in that the input (Eg) of a third inverter stage Representing inverter (3) from the surface field effect transistor (T ^ ₀ ) and the load = impedance (T ^ ₁ ) ciafür with the gate electrodes of the third and sixth surface field effect transistor (Tj ^ or »Tg ) and its output (Ag) with 909828/1529 BAD ORlGfNAL the gate electrodes of the second and dös fifth surfaces » Field effect transistor (Tg or «, Tg) are susaiBisengesehaltefc and the input (Eg) of the inverter (3) is connected to a signal pulse source (Fig. 8) _{or the like} 3 »Driver circuit according to claim 1 sur use in combination with a flip-flop, which is constructed from a cross-connection of the inputs and the outputs of a first and a second inverter stage, each consisting of a surface" field effect transistor and a load impedance each with their drain electrodes connected to the output of the first inverter stage and the input of the second inverter stage of the first and second surface fair effect transistors, of which the second surface field effect transistor at its gate electrode with the source electrode of the first surface field effect transistor is connected, each with its drain electrodes connected to the output of the second inverter stage and the input of the first inverter stage connected third and fourth surface field effect signals, of which the fourth surface field effect transistor & n its gate «= Electrodq with the source electrode of the third O surface field effect transistor is connected, and a fifth surface field effect transistor connected with its drain ° electrode to the source llsktrotiä of the second and fourth surface field effect transistor, characterized in that the input (E ₂ ) of the a third inverter * representing inverter (3) from the surface Fsldeffeiet 909828/1529 Trai'isiöfcoi · (ϊ-kq) vsna der Lastitnpsdang (^ j) «! Af'ir rait the gate electrodes of the first and third ofcer £ X £ ch« £ i "Pelde.ffekfc ·» T} * a.nsi sticra (Tjj or 'Sg / imd whose output (Ag) "dt car gate electrode of the fifth surface.-Foldcffekfc-Tr-aßsiiEitora (T ^B ₂ ) si'.satYiü'3ngeachaitet are tanci the input (E) (Tea inverters (3) is connected to a signal alirapulsQuellc (Fig. 3.0; ·. 4 _O driver circuit nacii any one of claims 1 to>, characterized gekem: - SCii.cli3efc, da.3 "wipe the Eingan.g (EC) and the Signalimpulsquslle a fourth Xn ^Tf o"'t € i-utufe (1 ) is switched on, consisting of a Oberflächer ^ Peldüffeki "transistor (5Vj ₀₎ and L-iiner Lastimpedans (^ gi) besteh for it," - ux-id on one first Spaimungsquelle (Vqq) ßngeschlasRen iijft "u.nü tHe you sRSte , die- svreita and the third Xnverterstiiie (T ^ T ^ p, ⁵ i> T) ^ emeiKr? an 'with a wide source of energy (VV ^) v _: rbi.viden are (Pig * 8) _c 5 c driver circuit according to claim 4 _f thereby geicynßz-i «; .: with that lateral load impedances consist of surface-field transistors and that the errt ^ n, tnid third inverter stages also form oeii Tx ^ i ^ slstai'-tn surface- ^ PeIdeffiiict »transistors sindo 909828/1529 BAD ORkSfKAL Blank page