DE1807105B2 - Driver circuit for flip-flops - Google Patents

Description

1 2

The invention relates to a driver circuit and the output of the second inverter stage.

device for operating flip-flops, which consist of a sixth surface field effect transistor

Area field effect transistors exist. existing second trigger circuit solved in that

An attempt has already been made to represent flip-flops, the input of a third inverter stage using circuits with upper 5 inverters from the surface field effect tran area field effect transistors, such as sistor and the load impedance for it with the gate-metal-insulator-semiconductor-field-effect-transistorsjdie Electrodes of the third and the sixth surface hereinafter referred to briefly as MIS transistors field effect transistor and its output with the should be built. An example of a gate electrode of the second and fifth upper ones Flip-flops can be found in the USA, for example Patent 3 363 115. The advantage here is that and the input of the inverter with a signal a MIS transistor is readily connected into a single pulse source.

semiconducting substrate can be integrated and that with the help of the invention can be a transistori power requirement as a result of the voltage-controlled ized flip-flop build, the one with a voltage type is low. Accordingly, it also turns out to be operated with a low voltage source and without white Flip-flop that is implemented using MIS- teres than in integrated circuit technology Transistors is constructed as advantageous. Semiconductor body can be produced.

In the course of investigations by the inventor, the following explanation has now been found on the one hand, it has been shown that often when operating such of the objectives, features and advantages of the ErFlip-Flops, as described in the aforementioned U.S.A. invention, reference is made to the drawing patent are described, an incorrect statement is referred to; in this work can be observed, and on the other hand that F i g. 1 and 10 circuit diagrams for each from above Incorrect work on an unwanted time-area field-effect transistor existing flipple Relationship between a first, from a flop,

Pulse source supplied input signal pulse and 25 F i g. 2 shows a representation of the in these flip-flops a second, the inversion of the first input and output side occurring signal signal pulse representing input pulse back waveforms,

is to be fed. This state of affairs is shown below in FIG. 3 and 4 a schematic sectional illustration

with reference to the drawing in more detail of incorporated into an integrated semiconductor body

and explained in detail. 30 built in surface field effect transistors and

Based on this prior art, there is an equivalent circuit diagram for one in both figures The invention is based on the object of providing a driver circuit framed by dashed lines to indicate the trigger circle lying in error,

Working of a surface field effect transi- F i g. 5 shows a representation of the working area of a

prevent disrupting existing flip-flops. 35 flip-flops depending on the voltage

According to the invention, this object is achieved in a supply

Driver circuit for use in combination F i g. 6 a circuit diagram for a common driver

with a flip-flop, which is made up of a circuit in connection with a flip-flop,

cross-connection of the inputs and F i g. 7 shows a representation of the input side and

the outputs of a first and a second, 40 each of the output signal waveforms for the

from a surface field effect transistor and circuit according to FIG. 6,

an inverter stage consisting of a load impedance, from FIG. 8 a circuit diagram for a driver circuit

one with the output of the first inverter stage according to a first embodiment of the invention

and the input of the second inverter stage connected in connection with a flip-flop and

which and from a first surface field effect 45 F i g. 9 shows a representation of the input side and

Transistor, one with the current path between the output signal waveforms for the

its source electrode and its drain electrode circuit according to FIG. 8th.

between the drain electrode of the first surface In F i g. 1 is a common flip-flop circuit representing a field effect transistor and set the output of the first, which consists of MIS transistors. Inverter stage inserted second surface field 50 In such a flip-flop circuit, the effect transistor and one with the current path gate capacitance of the MIS transistors temporarily as between its source electrode and its drain storage element, so that one has a binary electrode between the gate electrode of the first count can achieve. Such a flip-flop scarf surface field effect transistor and the output device is a conventional, inserted from bipolar transistors of the first inverter stage, third upper-level binary flip-flop counter in this respect Surface field effect transistor is superior to the existing first than with a much lower one Trigger circuit and from one with the output of the number of required components gets by. A second inverter stage and the input of the first further advantage of such a flip-flop circuit Inverter connected and from a fourth is that their production in the form of an in Surface field effect transistor, a half current path implemented with integrated circuit technology between its source electrode and conductor body is much easier, since it is made of MIS-its Drain electrode there is transistors between the drain electrode, which are more suitable than of the fourth surface field effect transistor and all other transistors.

the output of the second inverter stage inserted in FIG. 1 denote the reference symbols T ₁ and

fifth surface field effect transistor and a 65 T ₅ inverter MIS transistors and the reference symbols

with the current path between its source electrode T ₉ and T ₁₀ load MIS transistors whose drain

and its drain electrode between the gate elec- trodes each via a connection terminal P with

trode of the fourth surface field effect transistor of a direct voltage source (voltage V _DD )

are bound. The reference symbols T ₄ and T ₈ belong to blocking MIS transistors, the gate electrodes of which are each connected to an input terminal E for the supply of a first input pulse. The reference symbols T ₃ and T ₇ relate to memory MIS transistors which are each set up to generate a memory effect with the aid of their gate capacitances C ₁ and C ₂ , respectively, and the reference symbols T ₂ and T ₆ denote trigger MIS -Transistors, the gate electrodes of which are each connected to a second input terminal E ' for the supply of a second input pulse.

By applying input pulses phase-shifted by 180 ° from one another, as shown in lines b and α in FIG. 2 are illustrated to the first and to the second input terminal E and E ' in FIG. 1, output pulses can be obtained at output terminals A and A ' , the repetition frequency of which is half the repetition frequency of the input pulses, as shown in lines d and c in FIG. 2 is illustrated. A flip-flop like the circuit of FIG. 1 is therefore capable of binary counting, and consequently any desired counter, any desired shift register and the like can be constructed by interconnecting such flip-flops to form a flip-flop chain.

However, for the attempt to construct such a flip-flop in the form of a semiconductor arrangement implemented using integrated circuit technology, it is very important that one ensures that the power consumption is reduced to a minimum. However, this is synonymous with the requirement that the flip-flop still work satisfactorily when the voltage V _{DD of} the supply voltage source is low.

If the voltage V _{DD of} the supply voltage source is low, the current flowing through the MIS transistors in the conductive state is also reduced, and thus the power consumption in the flip-flop itself is reduced. This is advantageous in that it increases the temperature in the can prevent semiconductor circuit implemented in integrated circuit technology. If a chain of such flip-flops is integrated in a single semiconducting substrate, it is necessary to reduce the power consumption to a minimum in order to prevent inadmissible heat generation, since the MIS transistors are packed together in such a single semiconducting substrate with high density . To meet this requirement, it should therefore be possible to operate the flip-flop with a low supply voltage.

On the other hand, the above-described flip-flop has a disadvantage in that the input pulse _{voltage V E} must be high in order to operate the blocking MIS transistors T ₄ and T _8.

This means that, disadvantageously, the gate voltage for the blocking MIS transistors T ₄ and T ₈ is more than twice as much as a reference potential, which is required to convert these transistors into the conductive state and which will be referred to below as the threshold voltage ( for example -13 volts) of the threshold voltage (of for example -6VoIt) for the memory MIS transistors T ₃ and T ₇ , since the source electrodes of the blocking MIS transistors T ₄ and T ₈ with the gate electrodes of the Memory MIS transistors T ₃ and T _{7 are} connected.

The reason for this is that, since the p-type regions 32 and 42 (FIG. 3) which form the source electrodes S of the transistors T ₃ and T ₄ , and the p-type regions 33 and 43, which form the drain electrodes D of these transistors are integrally formed in a single semiconducting substrate 31 made of η-conductive silicon and the semiconducting substrate 31 in the form shown in FIG. 3 via a connection terminal G ₂ with a reference

potential, such as the ground potential, the threshold voltages of the transistors T ₄ (or T ₂ ) and T ₈ (or T ₆ ), whose source electrodes 8 are not directly connected to the reference potential, through the semiconducting substrate 31 in the Way are influenced that they are higher than that of the transistor T ₃ (or T ₇ ), as can be seen from FIGS. It can be shown empirically that the threshold voltage increases essentially proportionally to the square root of the inverse voltage between the semiconducting substrate 31 and the respective source electrode 8. Accordingly, the threshold voltages of the blocking MIS transistor T ₄ (or T ₈ ) are influenced by the substrate 31 so that they are slightly more than twice the threshold voltage of the memory MIS transistor T ₃ (or T ₇ ), the source of which -Electrode is directly connected to the reference potential, as described above.

In contrast to this, the threshold voltages of the trigger MIS transistors T ₂ and T ₆ are not influenced by the substrate 31 and assume a low value (of, for example, -6 volts) because the switch-on process in which the trigger MIS transistor T ₂ or T _{6 is} conductive, is limited only to the case in which the memory MIS transistor T ₃ or T _{7 is} conductive, although the source electrodes of the MIS transistors T ₂ and T ₆ via the current path between the source -Electrodes and the drain electrodes of the memory MIS transistors T ₃ and T _{7 are} connected to the reference potential. Accordingly, the low for the recovery of the second input pulse required voltage V _E is than required to obtain the first input pulse voltage V _E (V _E is, for example half the value of the voltage V _E).

From the above it can be seen that the conventional flip-flop described above is disadvantageous in that, although the input pulse _{voltage V E} can be low, the input pulse voltage So voltage V _E must be high.

Accordingly, in order to be able to operate such a flip-flop with a low input pulse voltage V _E , an attempt has been made in the usual way to attach an inverter 1 in front of the flip-flop 2 and to pass _{the blocking MIS transistors T 4 and T 8} operate the output of this inverter, as shown in FIG. 6 is illustrated. The arrangement according to FIG. 6 is constructed so that when a low pulse voltage V _{E is applied} as an input signal to the inverter 1, which is connected to a supply voltage source for a high voltage V _GG , a high voltage V _E at an output terminal A ₁ for the operation of the Blocking MIS transistors T ₄ and T _{6 is} obtained.

In investigations by the inventor, however, it has been shown that with this conventional method of operating a flip-flop, there is the possibility that the inverter transistor T ₂₀ in the inverter 1 is an im

5 6

the following explained in more detail incorrect operation of the voltage F ₀₀ selectable range limited if the flip-flops 2 can cause. For example, voltage F ₀₀ is lower than by applying a pulse voltage V _E , such as -25 volts, and the operation of flip-flop 2 stops in line α in FIG. 7 is shown to the on when the voltage F ₀₀ becomes higher. The basic output terminal E _{1 of} the inverter 1 is an inverted 5 for it is that an increase in the span pulse voltage V _E generates, in which the level for the output voltage V _n den and the falling parts of the for the rise F ₀₀ Pulse one of the inverter 1 increases to the value -E ₂ , as this delay occurs, as shown in the line & in in the line b in FIG. 7 in dashed lines ver-Fig. 7 is illustrated. The rise time or the illustrative, so that the time segment t _off extends in the rise time segment between a point in time t _v to io in the manner indicated by the reference symbol t _of / (t _t proportional to t _s ) when the inverter transistor T _{20 is switched off} and so the possibility and a time t ₂ at which this transistor enlarges a wrong operation. This means that it is switched on, depends on the product of the reverse, that the voltage V _D p cannot be turned into a lower resistance of the inverter transistor T ₂₀ than up to a certain, switched! State and the input capacitance of the _{flip-flop 2 defined by the relationship to the voltage F 00} or the resulting time limit value, if the voltage F _{00 is} lower constant. This rise time is so great that it is, for example, -35 volts. Barrier MIS transistor T ₄ (or T _8), when the invention are the experiments and investigations voltage V _E is more negative than the threshold based on the voltage carried on the basis of the fact E _th of the locking MIS transistor T ₄ (T ₈ ), that this tends to transition a memory, during a time t _off (see FIG. 7) equal to the MIS transistors from the conductive to the non-conductive at the same time as the trigger MIS -Transistor T ₂ (or T ₆ ) state after applying a pulse voltage to the work, which results in a faulty work-blocking MIS transistor required time interval to a large extent. is greater than that for the transition of a trigger MIS

This mode of operation will now be based on FIG. 7 25 transistor from blocked to conductive state

to be examined more closely. For this purpose it is assumed that the required time interval, and characteristic of

At the time I ₁ the trigger MIS transistors T _{2 is} the invention that the trigger MIS transistors

and T _{6 go} into the conductive state, so that by the output signal of one of MIS transistors

the states of the inverter MIS transistors T ₁ existing inverters are operated and that the

and reverse T _5. If the inverter MIS-30 inputs of the blocking MIS transistors go with those of the

Transistor T ₅ are interconnected from the non-conductive state in the inverter,

conductive state, this means that the

Inverter MIS transistor T ₁ by becoming conductive for the sake of better understanding

the trigger MIS transistors T ₂ and T ₆ further explained in the time.

point t _t from the conductive state to the non- 35 In F i g. 8 is an embodiment of the invention to switch conductive state. Would now be illustrated, with components similar to those of the blocking MIS transistors T ₄ and T ₈ at time t _t F i g. 6, with the same reference symbols immediately switched off, this harmed the boles as indicated in this figure. The operation of the flip-flop is not normal for the invention. An additional inverter 3 is provided according to _{FIG. 4} , but the blocking MIS transistors T 4 and T ₈ , as a result of 40, have an inverter MIS transistor T ₃₀ and a load of delaying the signal voltage V _E during MIS transistor T ₃₁ . An output terminal of the time segment t _{o! I} in the switched-on state A _{2 of} the inverter 3 is to be held with the gate electrodes of the drain voltage (ie the trigger MIS transistors T ₂ and T _{6 of} the flip-flop 2) in the switched-off state) for the In- connected, and the gate electrodes of the blocking MIS-verter-MIS transistor T ₁ during this time- 45 transistors T ₁ and T _{8 of} the flip-flop are connected to the section t _of f over the blocking MIS transistor T _{4 is connected} to the input terminal E _{2 of} the inverter 3. Gate electrode of the memory MIS transistor T ₃ on, the method of operation of the invention so that this transistor is switched on will be explained in more detail next. The simplicity of the dar will. On the other hand, for the sake of the trigger position, it is assumed that at _{this point in time the input MIS transistor T 2 is} in the conductive 50 output terminal E _{2 of} the inverter 3 and the input state. As a result, the inverter MIS terminal E for the blocking transistors T ₄ and T _8, a transistor T _{1 occurs} again from the non-conductive to the conductive completely square- wave voltage V _E , state. This means, however, that the inverter as shown in FIG. 9 is illustrated in line b. MIS transistor T ₁ at time t _t from conductive to This pulse voltage V _E is converted to the non-conductive state by inverter 3, but reversed and delayed, so that at the off at time f ₄ , output terminal A _{2 is} returned to the conductive state of the inverter 3 returns a signal voltage, resulting in an erroneous operation V _E , as shown in FIG. 9 results in the line α varied flip-flops. is clear. The inverted signal voltage V _E becomes

As a result of such a faulty operation of the trigger MIS transistors T ₂ and T ₆ as a guide, the operating area of the flip-flop is fed to the output signal.

visibly reduced the supply voltage. Fig. 5- It is assumed that the inverter MIS illustration shows the working area 10 of the flip-flop 2, transistor T _{1 of} the flip-flop 2 between the times t _t , this working area being indicated by the hatched and t ₂ in F i G. 9 is switched on and therefore indicated in the lines and the supply voltage V _DD verter-MIS transistor T _{5 of} the flip-flop 2 is switched off in this time interval for the flip-flop 2 along the horizontal axis 65. Then arises at the and the supply voltage F ₀₀ for the inverter 1 ent-drain electrode of the inverter MIS transistor T ₅ are plotted along the vertical axis. a voltage F ₀ , and the drain electrode of the in-

As one can see from FIG. 5, the one for the Spanverter MIS transistor T ₁ is on a reference

potential held. At this time, since the barrier MIS transistors T ₄ and T lead _8, the inverter MIS transistor T ₁ in the gate capacitance C stored the drain voltage V _{0 2} of the memory MIS transistor T _1, whereby this transistor is turned on. In addition, the gate voltage for the memory MIS transistor T ₃ is reduced to zero. After the blocking MIS transistors T ₄ and T ₈ are switched off at time t ₂ , the trigger MIS transistors T ₂ and T _{6 are switched} on at time t _z . In this way, such an arrangement cannot lead to the type of malfunction that can be observed with the usual arrangement (cf. FIG. 7, lines α and b).

Between the times t ₃ and i ₄ , the trigger MIS transistors T ₂ and T _{6 are} switched on, so that the inverter MIS transistor T _{5 is} switched on, while the inverter MIS transistor T _{1 is switched on} by the transistors T becoming conductive ₆ and T ₇ becomes conductive. In this way, the states of the inverter MIS transistors T ₁ and T ₅ are reversed by the pulse voltage V _E supplied to the trigger MIS transistors T ₂ and T _6.

The trigger MIS transistors T ₂ and T ₆ are still in the conductive state between the times J ₄ and i ₅ , and at the time i ₄ , the blocking MIS transistor T ₄ (and the blocking MIS Transistor T ₈ ) applied the pulse voltage V _E and switched it on. Accordingly, one might suspect that there is a possibility that the memory MIS transistor T _{3 is} turned on while the memory MIS transistor T _{7 is} turned off. However, the time segment between the point in time when the pulse voltage V _{E is} actually applied to the input terminal E until the point in time when the memory MIS transistor T _{3 is} switched on (the sum of the time periods required to switch on the blocking MIS transistor T ₄ and the memory MIS transistor T _{3 are} required), larger than that in FIG. 9 illustrated time interval t _of f, so that the memory MIS transistor T _{3 is} switched on and the memory MIS transistor T _{7 is} switched off after the trigger MIS transistors T ₂ and T ₆ are switched off at time t _s. Accordingly, there is no faulty mode of operation in which the trigger MIS transistor T ₂ and the memory MIS transistor T ₃ would be switched on simultaneously between the times i ₄ and t _5.

According to the invention, it is therefore possible to prevent incorrect operation, as is the case with conventional arrangements occurs to prevent, since the flip-flop only then by transferring the trigger MIS transistors in the conductive state is reversed after the blocking MIS transistors are completely switched off are, and then the trigger MIS transistors turned off again, and after that the blocking MIS transistors are turned off like this is described above.

The in F i g. 5 framed with dashed lines working area 11 corresponds to the case of use of the invention to operate the flip-flop 2. From this figure it can therefore be seen that the invention, the working area of the flip-flop 2 can be made larger in terms of supply voltage than in the known arrangement, and that operation is possible even at low voltage. In this case, the lower limit for the voltage F ₀₀ corresponds to the minimum value at which the trigger MIS transistors of the downstream flip-flop can be operated in the arrangement of FIG. 8, and the lower limit for the voltage V _GG corresponds to the minimum value , in which the blocking MIS transistors of the downstream flip-flop can be operated in the arrangement in FIG.

The invention can therefore be used to advantage in those cases in which a flip-flop chain is to be constructed from a multiplicity of flip-flops 2. In such a flip-flop chain, it is necessary that the output pulse voltage V _E available at the output terminal A ″ of a flip-flop 2 is converted into a high pulse voltage V _E between successive flip-flop stages, since the subsequent flip-flop To meet this requirement, an inverter 1 and the inventive inverter 3 must be provided between a first flip-flop stage and one of these following second flip-flop stages operate satisfactorily with a lower value for the supply voltage V _DD for the flip-flop than is the case with a conventional arrangement, as can be seen from Fig. 5. This clearly shows that the power consumption in the flip-flop chain can be reduced and that the flip-flops can be easily built in integrated circuit technology.

Of course, the invention can also be applied to flip-flops 2 which use a single trigger MIS transistor T ₂ ', as shown in FIG.

Claims (4)

Patent claims: 1. Driver circuit for use in combination with a flip-flop that is constructed from a cross-wise interconnection of the inputs and the outputs of a first and a second, each made of a surface field effect transistor and an inverter stage consisting of a load impedance, one having the output of the first inverter stage and the input connected to the second inverter stage and composed of a first surface field effect transistor, one with the current path between its source and drain between the drain electrode of the first surface field effect transistor and the output of the first inverter stage inserted second surface field effect transistor and one with the current path between its source electrode and its drain electrode between the gate electrode of the first surface field effect transistor and the output of the first inverter stage inserted third surface field effect transistor consisting of the first trigger circuit and one with the output of the second inverter stage and the input of the first inverter stage connected and made up of a fourth surface field effect transistor, one with the current path between its source electrode and its drain electrode between the drain electrode of the fourth surface field effect transistor and the output of the second inverter stage fifth surface field effect transistor 009 513/158 and a sixth surface field effect transistor inserted with the current path between its source electrode and its drain electrode between the gate electrode of the fourth surface field effect transistor and the output of the second inverter stage, characterized in that the input (E ₂ ) of the inverter (3) representing a third inverter stage from the surface field effect transistor (T ₃₀ ) and the load impedance (T ₃₁ ) for this purpose with the gate electrodes of the third and sixth surface field effect transistor (T ₁ or T ₈ ) and its output (A ₂ ) are interconnected with the gate electrodes of the second and fifth surface field effect transistors (T ₂ and T ₆ ) and the input (E ₂ ) of the inverter (3) with a signal pulse source is connected (Fig. 8). 2. Driver circuit according to claim 1 for use in connection with a flip-flop, which is constructed from a cross-connection of the inputs and outputs of a first and a second, each of a surface field effect transistor and a load impedance therefor existing inverter stage from each with their drain electrodes connected to the output of the first inverter stage and the input of the second inverter stage, the first and second surface field effect transistors, of which the second surface field effect transistor at its gate electrode with the source electrode of the first surface Field effect transistor is connected, each with their drain electrodes connected to the output of the second inverter stage and the input of the first inverter stage third and fourth surface field effect transistors, of which the fourth surface field effect transistor at its gate electrode with the source electrode of the third surface field effect Transistor is connected, and of a fifth surface field effect transistor connected with its drain electrode to the source electrode of the second and fourth surface field effect transistor, characterized in that the input ^) of the inverter representing a third inverter stage ( 3) from the surface field effect transistor (T ₃₀ ) and the load impedance (T ₃₁ ) to the gate electrodes of the first and third surface field effect transistor (T ₄ or T ₈ ) and its output (A ₂ ) are interconnected with the gate electrode of the fifth surface field effect transistor (T ₂ ') and the input (E) of the inverter (3) is connected to a signal pulse source (Fig. 10). , ■ 3. Driver circuit according to claim 1 or 2, characterized in that between the input (E ₂ ) of the inverter (3) and the signal pulse source, a fourth inverter stage (1) is switched on, which consists of a surface field effect transistor (T ₂₀ ) and a load impedance (T ₂₁ ) and is connected to a first voltage source (F ₀₀ ), and that the first, the second and the third inverter stage (T ₁ , T ₅ , 3, T ₃₀ ) together with a second voltage source (V _DD ) are connected (Fig. 8). 4. Driver circuit according to claim 3, characterized in that all load impedances consist of surface field effect transistors and that also the first, second and third Transistors forming inverter stages are surface field effect transistors. For this purpose 2 sheets of drawings