JPS62216296A - Multilayer ceramic board - Google Patents
Multilayer ceramic boardInfo
- Publication number
- JPS62216296A JPS62216296A JP5853186A JP5853186A JPS62216296A JP S62216296 A JPS62216296 A JP S62216296A JP 5853186 A JP5853186 A JP 5853186A JP 5853186 A JP5853186 A JP 5853186A JP S62216296 A JPS62216296 A JP S62216296A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- multilayer ceramic
- holes
- ceramic
- ceramic green
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims description 34
- 239000000758 substrate Substances 0.000 claims description 15
- 238000010304 firing Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 description 20
- 238000005553 drilling Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000002994 raw material Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000002518 antifoaming agent Substances 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000012993 chemical processing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002270 dispersing agent Substances 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000004014 plasticizer Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電子回路に用いられる多層セラミック基板に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multilayer ceramic substrate used in electronic circuits.
従来の技術
近年、電子回路に用いられるセラミック基板は、小型化
、高集積化によって高密度な配線が要求される様になっ
ている。又、これに伴って、セラミック基板は、両面化
、多層化が進み、しかも、スルーホールやピアホールの
数は、非常に増加する傾向にあり、貫通穴の径も小さぐ
なって来た。2. Description of the Related Art In recent years, ceramic substrates used in electronic circuits are required to have high-density wiring due to miniaturization and high integration. Further, along with this, ceramic substrates have become double-sided and multilayered, and the number of through holes and peer holes has tended to increase significantly, and the diameter of the through holes has also become smaller.
２ベー。2 b.
従来の多層セラミック基板におけるスルーホールやピア
ホールの形状は、第６図に示す様に、セラミックグリー
ンシートの貫通穴がストレート形状で、その貫通穴の内
に導電材料を印刷法やメッキ法により形成したものであ
り、このセラミックグリーンシートを積層し焼成するこ
とにより上層と下層を電気的に導通させたものであった
。第５図中、１は内部導体層、２はスルーホールの導体
層、３はセラミック層、４はピアホールの導体層、５は
スルーホール、θはピアホールを示す。As shown in Figure 6, the shape of through holes and peer holes in conventional multilayer ceramic substrates is such that the through hole in the ceramic green sheet is straight, and a conductive material is formed inside the through hole by printing or plating. By stacking these ceramic green sheets and firing them, the upper and lower layers were made electrically conductive. In FIG. 5, 1 is an internal conductor layer, 2 is a through-hole conductor layer, 3 is a ceramic layer, 4 is a pier-hole conductor layer, 5 is a through-hole, and θ is a pier hole.
発明が解決しようとする問題点
しかしながら、従来の多層セラミック基板では、ストレ
ート形状の貫通孔に対して導体層を設けたセラミックグ
リーンシートを積層し焼成するものであるため、スルー
ホール、ピアホールの形状上、積層時には高い精度を必
要とする点、貫通穴のエツジ部分の導電体に亀裂を発生
しやすい点、上層の導電体と下層の導電体との接続が不
完全になりやすい点、貫通穴の径が小さくなればなるほ
ど上記の欠点により信頼性が著しく低下す、る点など、
多く形状による問題点を有していた。Problems to be Solved by the Invention However, in conventional multilayer ceramic substrates, ceramic green sheets with conductor layers are laminated and fired for straight-shaped through holes, so problems arise due to the shape of the through holes and peer holes. , high precision is required when stacking, cracks are likely to occur in the conductor at the edge of the through-hole, the connection between the conductor in the upper layer and the conductor in the lower layer is likely to be incomplete, and The smaller the diameter, the lower the reliability will be due to the above drawbacks.
Many problems were caused by the shape.
本発明の目的とするところは、上記の様な従来の問題を
除去し、高信頼性で高集積化を可態とする多層セラミッ
ク基板を提供することにある。It is an object of the present invention to provide a multilayer ceramic substrate which eliminates the above-mentioned conventional problems and which has high reliability and enables high integration.
問題点を解決するだめの手段
本発明の多層セラミック基板は、テーパ状の貫通孔の孔
壁および上記貫通孔の周辺の上下面に導体層を形成した
セラミックグリーンシートを多層に積層し焼成してなる
ことを特徴とするものである。Means for Solving the Problems The multilayer ceramic substrate of the present invention is produced by laminating and firing ceramic green sheets in multiple layers, each of which has a conductor layer formed on the hole wall of a tapered through hole and on the upper and lower surfaces around the through hole. It is characterized by:
作 用
本発明の多層セラミック基板は、スルーホール・ピアホ
ールの形状をセラミックグリーンシートの状態で、金型
やドリルによる機械的加工、溶剤や溶液を使用して行な
う化学的加工でテーパ状とすることができ、そのテーパ
状の貫通穴の上面と下面の異った寸法に導電材料を貫通
穴の内部に充填するか、又は、コーティングして形成す
ることができる。したがって、このグリーンシートを積
層・焼成して得られるスルーホール・ピアホールの形状
では積層時に精度を要求されることなく上下の導電体の
接続を完全なものとすることができ、またエツジ部分で
の亀裂の発生が少なく信頼性を高めることができる。Function: In the multilayer ceramic substrate of the present invention, the shape of the through hole/pier hole can be made into a tapered shape by mechanical processing using a mold or drill, or chemical processing using a solvent or solution in the state of a ceramic green sheet. The tapered through hole can be formed by filling or coating the inside of the through hole with a conductive material so that the upper and lower surfaces of the through hole have different dimensions. Therefore, the shape of the through hole/pier hole obtained by laminating and firing these green sheets allows perfect connection between the upper and lower conductors without requiring precision during lamination, and also allows for perfect connection of the upper and lower conductors at the edge portion. There are fewer cracks and reliability can be improved.
実施例
以下本発明の実施例について、図面を参照しながら説明
する。EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示し、セラミックグリーン
シートを積層して焼成したものである。FIG. 1 shows an embodiment of the present invention, in which ceramic green sheets are laminated and fired.
第１図中、１１は内部導体層、１２はスルーホールの導
体層、１３はセラミック層、１０はスルーホール、９は
ピアホール、８はピアホールの導体層である。まず、第
２図Ａに示すようにアルミナ主成分のセラミック原料に
有機結合剤・可塑剤・分散剤・消泡剤・溶剤を加えて混
合された原料液をドクターブレード法にてキャスティン
グし、一定の厚さのセラミックグリーンシート１４を作
り、これを一定の寸法に切断する。上記のセラミックグ
リーンシート１４に機械加工を行なってテーパ状の貫通
穴１０′を加工する。In FIG. 1, 11 is an internal conductor layer, 12 is a through-hole conductor layer, 13 is a ceramic layer, 10 is a through-hole, 9 is a pier hole, and 8 is a pier-hole conductor layer. First, as shown in Figure 2A, a raw material liquid made by adding an organic binder, plasticizer, dispersant, antifoaming agent, and solvent to a ceramic raw material mainly composed of alumina was mixed using a doctor blade method, and a uniform A ceramic green sheet 14 having a thickness of 100 mL is made and cut into a certain size. The ceramic green sheet 14 described above is machined to form a tapered through hole 10'.
５、＜−。5, <-.
上記の機械加工は第３図Ａ、Ｂに示すパンチ加工、第４
図Ａ、Ｈに示すドリル加工により、１回の加工で穴を開
けるか、又は、数回の加工によって穴を開ける方法によ
り貫通穴を形成する。The above machining includes the punching shown in Figures 3A and B, and the 4th
A through hole is formed by drilling a hole in one process or by drilling several times using the drilling process shown in Figures A and H.
上記の貫通穴１０’を有するセラミックグリーンシート
１４を第２図Ａ−Ｃの如く印刷法により、貫通穴の上部
に導電材料を印刷すると同時に貫通穴の下部より吸引を
行ない、貫通穴内部に導電材料を流入させることにより
、テーパ状の貫通孔の孔壁および貫通孔の周辺の上下面
に通電材料を塗布する。このグリーンシートを加熱乾燥
した後、ｆｉｌ・焼成して第１図のピアホール９．スル
ホール１０を有する多層セラミック基板を製造する。The ceramic green sheet 14 having the above-mentioned through-holes 10' is printed with a conductive material on the upper part of the through-hole by a printing method as shown in FIG. By flowing the material, the electrically conductive material is applied to the hole wall of the tapered through hole and the upper and lower surfaces around the through hole. After heating and drying this green sheet, it is filled and fired to form a pier hole 9 in FIG. A multilayer ceramic substrate having through holes 10 is manufactured.
上記の実施例で、セラミックグリーンシートの厚さが２
００μｍの貫通穴は上部径が２００μ弓下部径が３００
μｍで加工を行なっているが、とのテーパ比率はセラミ
ック材料の抗折強度と、セラミックグリーンシートの厚
さとの関係で決定され、上記比率は５チル６０％に設計
されることが望ましい。In the above example, the thickness of the ceramic green sheet is 2
00μm through hole has an upper diameter of 200μ and a lower diameter of 300μm.
Although processing is performed in μm, the taper ratio between and is determined by the relationship between the bending strength of the ceramic material and the thickness of the ceramic green sheet, and it is desirable that the above ratio is designed to be 5 chills and 60%.
６、、・
」二記の如く設計・製造された多層セラミック基板は、
スルーホールの導電体間の、接触面積を向上させ、電子
回路基板として非常に高効率であり、セラミック層の貫
通穴体積が小さくなる為に抗折強度を高める事が出来る
。6. The multilayer ceramic substrate designed and manufactured as described in 2.
It improves the contact area between the conductors in the through holes, making it extremely efficient as an electronic circuit board, and increasing the bending strength because the volume of the through holes in the ceramic layer becomes smaller.
発明の効果
以上のように本発明は、多層セラミック基板のスルーホ
ール・ピアホールの形状をテーパ状にする事により、電
子回路内の配線抵抗を大幅に低下させ、スルーホール・
ピアホール部分の抗折強度を向上させて高信頼性・高集
積度で高い歩留りを確立するものである。Effects of the Invention As described above, the present invention significantly reduces the wiring resistance in electronic circuits by tapering the shape of the through holes and peer holes of the multilayer ceramic substrate.
This improves the bending strength of the pier hole portion to ensure high reliability, high integration, and high yield.
第１図は本発明の多層セラミック基板の一実施例を示す
断面図、第２図Ａ−Ｃは同基板に使用するセラミックグ
リーンシートのスルーホール印刷工程の断面図、第３図
Ａ、Ｂは貫通穴を金型により加工する断面図、第４図Ａ
、Ｂは貫通穴をドリルにより加工する断面図、第６図は
従来の多層セラミック基板の断面図である。
９・・・・・・ピアホール、１ｏ・・印・スルーポール
１１・・・・・・内部導電体層、１２・・・・・・スル
ーホールの導電体層、１３・・・・・・セラミック層、
１４・・・・・・セラミックグリーンシート。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名鳴
（゛
第３図
（Ａ）
第４図
ＣＢ）
に
（ＢンFig. 1 is a cross-sectional view showing an embodiment of the multilayer ceramic substrate of the present invention, Fig. 2 A-C is a cross-sectional view of the through-hole printing process of a ceramic green sheet used in the same substrate, and Figs. 3 A and B are Cross-sectional view of processing a through hole with a mold, Figure 4A
, B is a sectional view of drilling a through hole, and FIG. 6 is a sectional view of a conventional multilayer ceramic substrate. 9... Pier hole, 1o... mark, through pole 11... internal conductor layer, 12... through hole conductor layer, 13... ceramic layer,
14...Ceramic green sheet. Name of agent: Patent attorney Toshio Nakao and one other person
(Fig. 3 (A) Fig. 4 CB)
Claims (1)
の孔の孔壁および上記の孔の周辺の下面、上面に通電体
を形成したセラミックグリーンシートを多層に積層し焼
成してなることを特徴とする多層セラミック基板。It has a mechanically and chemically formed tapered hole, and is made by laminating and firing ceramic green sheets in multiple layers, with current-carrying bodies formed on the hole wall of the hole and the lower and upper surfaces around the hole. A multilayer ceramic substrate characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5853186A JPS62216296A (en) | 1986-03-17 | 1986-03-17 | Multilayer ceramic board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5853186A JPS62216296A (en) | 1986-03-17 | 1986-03-17 | Multilayer ceramic board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62216296A true JPS62216296A (en) | 1987-09-22 |
Family
ID=13087013
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5853186A Pending JPS62216296A (en) | 1986-03-17 | 1986-03-17 | Multilayer ceramic board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62216296A (en) |
-
1986
- 1986-03-17 JP JP5853186A patent/JPS62216296A/en active Pending
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