JPS62216077A - Address generator - Google Patents

Abstract

PURPOSE:To produce addresses in response to plural modes without increasing the number of counters by outputting a control signal to control the working period, the working cycle and the stop period when the signal showing a process mode is inputted. CONSTITUTION:When a mode selection signal 1 showing a process mode is inputted to a mode control circuit 1A, the circuit 1A selects a certain mode. Here a control ROM address counter 2 starts counting in the circuit 1A and therefore a count-enable signal in the mode control signal 6 is outputted to a frame memory address counter 7 from a mode control ROM 4. Then the counter 7 starts counting. Thus a frame memory address 8 is produced from the counter 7 and inputted to a frame memory 9 as well as to a count reset logic circuit 13. When the counter 7 counts the final picture element, the circuit 13 outputs a reset signal to reset the counter 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address generator that accesses image data in a frame memory in accordance with a processing mode.

[Conventional technology]

A conventional example of reading out image data in a frame memory and performing image processing in response to multiple processing modes is shown in the third example.
This will be explained based on the diagram.

FIG. 3 is a block diagram showing the configuration of a multi-mode image processing device using a conventional address generator. In the figure, 1 indicates a mode select signal indicating a processing mode, and 4 indicates a processing mode based on the select signal 1. Selectors 7a, 7b, 7 for selecting the corresponding frame memory address counter
c is a frame memory address counter, 13a, 13b
.

13C is frame memory address counter 7a+7b,
Counter reset logic circuit for resetting 7c, 8
is a frame memory read address, 9 is a frame memory that stores image data, 10 is frame memory read data, 11 is an image processing system, 12 is a clock, 14a, 1
4b and 14c are frame memory address counter reset signals.

Next, the operation will be explained. In an image processing apparatus that performs processing in a plurality of modes, frame memory address counters 7a, 7b, and 7c are used during the operation period.

The counter reset logic circuit 13a has individual functions with different stop periods and operation cycles, and the functions correspond to the processing modes performed by the image processing system 11.

13b and 13c. The outputs of the frame memory address counters are each input to the selector 4 together with the mode select signal 1, and the outputs of the frame memory address counters 7a, 7b, 7c necessary for the processing mode are 1.
one is selected, and frame memo U9 is accessed as frame memory read address 8. Frame memory read data 10, ie, image data, is read from the frame memory and input to the image processing system 11.

A mode select signal 1 is also input to the image processing system 11, and processing in a plurality of modes is performed.

[Problem that the invention seeks to solve]

In conventional address generators, when supporting multiple modes, the circuit is configured as described above, so if more processing modes are required, it is necessary to add a separate address counter required for that mode. Therefore, the counter occupies a large amount of space in the circuit, and there are problems in that it is not easy to modify the processing contents.

This invention was made to solve the above-mentioned problems. It is possible to generate addresses that correspond to multiple modes without adding counters, and it also facilitates modification according to the processing content, making it a general-purpose The purpose of this invention is to obtain an address generator that is compatible with multiple modes.

[Means for solving problems]

Therefore, the address generator according to the present invention has an operation period when a signal indicating the processing mode is input.

Equipped with a mode control circuit that outputs a control signal for controlling the operating cycle and stop period, and an address counter that generates an address to the frame memory corresponding to the processing mode based on the control signal from the mode control circuit. It is characterized by:

[Effect]

The mode control circuit according to the present invention determines the operation period and operation cycle when a signal indicating the processing mode is input.

Outputs a control signal to control the stop period.

Based on this control signal, the address counter determines the operation period and operation cycle in accordance with the above processing mode.

Generate addresses with different stop periods. Therefore, image data corresponding to the processing mode is read from the frame memory.

〔Example〕

An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram of an address generator showing an embodiment of the present invention, where 1 is a mode select signal indicating a processing mode, 2 is a control ROM address counter, 3G;J, ゛+1p□4
Control iR output from JIIROM address counter 2
A mode control ROM 5 is a control ROM address counter 2 in which OM address 4 stores control signals for controlling the operating period, operating cycle, and stop period in accordance with the processing mode.
6 is a mode control signal output from the mode control@ROM 4, and 7 is a mode control signal that generates addresses for frame memories with different operating periods, operating cycles, and stop periods based on the mode control signal. a frame memory address counter; 8 is a frame memory read address output from the frame memory address counter 7; 9 is a frame memory storing image data; 10 is frame memory read data as image data read from the frame memory 9; 1
1 is an image processing system that processes image data read from the frame memory 9; 12 is a clock; 13 is a counter reset logic circuit; and 14 is a frame memory address counter reset signal.

Here, the control ROM address counter 2 and mode control ROM 4 together constitute a mode control circuit IA.

Next, the operation will be explained.

Here, for the sake of simplicity, one frame is assumed to have a total of 48 pixels (6×8) (see FIG. 2(a)). In addition, the frame memory 9 stores information for one frame in the raster direction, and the image processing system 11 stores information for one frame in the raster direction.
It has two modes (Mode 1 corresponds to Figure 2 (b) and Mode 2 corresponds to Figure 2 (C)) in which image data is serially output every clock in the raster direction in the format shown in Figure 1. shall be taken as a thing.

However, in FIG. 2(b), (the shaded part of C1 indicates blanking and the data value is 0. Here, the mode select signal 1 indicating the processing mode is the mode control circuit I
A, this mode control circuit selects LA mode 1.A.
Select one of Mode 2.

When the control ROM address counter 2 in the mode control circuit IA starts counting, a mode control signal 6 is sent from the ROM 4 to the frame memory address counter 7 based on the control ROM address counter 3 output from the control ROM address counter 2. Of these, count enable is output, and frame memory address counter 7 starts counting. System '4B ROM address counter 2 outputs 1 frame including blanking (
Since it also has the function of the pixel counter shown in Figure 2 (b) and (C1), the control i11RO from the mode control ROM4
The M address counter reset signal 5 resets the counter after counting the last pixel in each mode.

When the frame memory address counter 7 is activated, a frame memory read address 8 is generated from the frame memory address counter 7 and inputted to the frame memo U 9 and the counter reset logic circuit 13. Here, when the frame memory address counter 7 counts the last pixel of one frame (FIG. 2(a)) that does not include blanking,
The counter reset logic circuit 13 outputs a frame memory address counter reset signal 14 to reset the frame memory address counter 7. Further, frame memory read data 10, that is, image data, is sequentially read from the frame memory 9 using the frame memory read address 8, but since it is necessary to stop reading from the frame memory 9 during the blanking period, mode-based ill ROM is used. During a period corresponding to blanking, a mode control signal 6 for temporarily stopping the frame memory address counter 7 at a count immediately before blanking starts is output. The image processing system 11 receives frame memory read data 10 and mode select signals 1. A mode control signal 6 is also input, and the data is processed in the format of the selected mode. Note that the counter used in this circuit has synchronous load and synchronous reset functions.

〔Effect of the invention〕

As described above, the present invention can control the operation period and operation cycle when a signal indicating the processing mode is input.

Since it is equipped with a mode control circuit that outputs a control signal for controlling the stop period, and an address counter that generates an address to the frame memory corresponding to the above processing mode based on the control signal from this mode control circuit, it is possible to compare With a compact circuit configuration, the number of modes can be set according to the capacity of the mode control ROM, and an address generator that is space-saving and highly flexible for complex functions can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an address generator according to an embodiment of the present invention, FIG. 2 is a format of one image frame in each mode, and FIG. 3 is a multi-mode image processing device using a conventional address generator. FIG. In the figure, 1 is the mode select signal, 2 is the control ROM address counter, 3 is the control ROM address, and 4 bar E--)
"Control ROM, 5 is a control ROM address counter reset signal, 6 is a mode control signal, 7 is a frame memory address counter, 8 is a frame memory read address,
13 is a counter reset logic circuit, and 14 is a frame memory address counter reset signal. In addition, in the figure,
The same reference numerals indicate the same or equivalent parts. To the agent Masuo Oiwa (and 2 others) Ge 1 Figure 3 Procedure amendment form (self-effective Showa year month date address generator 3, person making the amendment Representative Moriya Shiki 4, agent 5, subject of amendment Detailed Description of the Invention Column. 6. Contents of the Amendment The text "FROM 5 is control" on page 6, line 6 of Tll Mei IIi is amended to read "FROM, 5 is control". (2) Book 7 of the same book Line 15: “The data value is θ.”
``The data value is 0.'' is corrected. (3) In the same book, page 7, lines 17 to 18, "The control circuit is in IA mode 1" is replaced with "The control circuit is in mode 1."
” he corrected. (4) In the same book, page 8, 1st and 2nd lines, correct the text "FROM address counter 3" to "FROM address 3." Written amendment to the above procedure (Horiki Showa year, month, day 1, indication of the case: Japanese Patent Application No. 61-4613 2, name of the invention address generator 3, relationship with the case by the person making the amendment: Moriya Shiki, representative of the patent applicant 4) , Agent 5, Date of amendment order: March 17, 1985 6, Subject of amendment: Procedural amendment written by Sumoyama dated January 19, 1988. 7. Contents of amendment (1) Date of January 19, 1988. Second amendment to the procedure for submission
In the 6th line of the page, "The data value is θ." is corrected to "The data value is 0."that's all

Claims (2)

[Claims] (1) In an address generator that generates addresses with different operating periods, operating cycles, and stop periods in response to a plurality of processing modes, and reads out image data corresponding to the processing mode from the frame memory based on the address, A mode control circuit that outputs a control signal to control the operation period, operation cycle, and stop period when a signal indicating a processing mode is input, and a mode control circuit that corresponds to the processing mode based on the control signal from this mode control circuit. and an address counter that generates an address to a frame memory. (2) The mode control circuit includes a mode control ROM that stores control signals for controlling the operation period, operation cycle, and stop period in correspondence with the processing mode, and a control ROM address counter that outputs an address signal for this mode control ROM. An address generator according to claim 1, characterized in that it is comprised of: