JPS61143876A - Picture processor for display of plural pictures - Google Patents

Abstract

PURPOSE:To switch quickly the positions of pictures for display by using an X and Y direction format converting circuits which supply the output of an address counter and changes the address of the picture data read out of a picture memory. CONSTITUTION:The X and Y direction format converting circuits 15a and 15b supply the output of an X or Y address counter 14a or 14b and outputs the output after converting it into another proper value. A conversion pattern is designated by a central processor 11. The X and Y address registers 16a and 16b supply and store the outputs of both circuits 15a and 15b, and the memory address is held temporarily for a period of time needed by a picture memory 12. Then the address is designated for the picture data read out of the memory 12.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to, for example, X-ray images, contrast-enhanced X-ray images,
Regarding an image processing device for displaying multiple images that simultaneously displays multiple images such as MCT images and electrocardiogram data of a patient, an image processing device for displaying multiple images that can quickly switch and display the positions of one image and another image. Regarding.

2. Description of the Related Art A conventional image processing device for displaying multiple images, as shown in FIG. ,
x, X direction address counters 4a, 4b, x, X direction address registers 5a*5b,) 5 converter 6,
It was configured with a display T. Then, an address progress signal created by appropriately dividing the TV synchronization signal of the Rusk scan method sent from the synchronization signal generator 3 is counted by address counters 4a and 4b in the X and Y directions, and based on this output, The address of the image data to be read out from the image memory 2 is specified by the address registers 5a+5b in the X and Y directions, and when the image data at the specified address is read out from the image memory 2, it is converted into an analog signal by the signal converter 6. After conversion, multiple images were displayed on the display 7 at the same time. At this time, the plurality of images are displayed on the screen of the display 7 in the same order as they were stored in the image memory 2.

Problems to be Solved by the Invention However, for example, when a doctor observes X-ray images, contrast-enhanced X-ray images, XICT images, electrocardiogram data, etc. side by side, if they are lined up in an order that has no medical relevance. Since this is inconvenient for diagnosis, there is a considerable demand for, for example, displaying the upper left image and the lower right image interchangeably on the screen. In such a case, in the conventional image processing device described above, "
The pixel data corresponding to the image “upper left” is sent to the central processing unit 1.
0 control, the image is read from the image memory 2 and temporarily stored in another storage device (for example, the magnetic disk 8 or the magnetic tape 9).
), the pixel data corresponding to the "lower right" image is also read out from the image memory 2 and stored in another storage device, and then the "upper left" image data is transferred back to the original "lower right". The "lower right" image data was written to the image memory 2 address corresponding to the original "upper left" image. In this state, the image data is sequentially read out from the image memory 2 in which the image data has been replaced in synchronization with the television synchronization signal, thereby displaying the replaced image data. In other words, it is necessary to replace and store the image data itself in the image memory 2 in the order of the images to be replaced and displayed. In this case, the reading and writing time for the image memory 2, the writing and reading time for another storage device, and the program control time in the central processing unit 1 are all estimated, and the replacement operation takes time. Therefore, for example, when a doctor performs a diagnosis by replacing and displaying images, the diagnostic efficiency is reduced.

Therefore, an object of the present invention is to solve such problems.

Means for Solving the Problems The means of the present invention for solving the above problems consists of an image memory that stores image data of a plurality of images, and an address progress signal created by dividing a television synchronization signal, which counts the address progress signal and stores the image data of the above-mentioned images. It has an address counter in the X and Y directions that specifies the address of the image data to be read from the memory, and under the control of the central processing unit, the image data in the image memory is divided into several parts, read out, converted into I)/A, and displayed on the display. In a multi-image display image processing device that simultaneously displays a plurality of images, the output of the address counter is input between each of the address counters in the X direction and the Y direction and the image memory, and image data is read from the image memory. This is performed by an image processing apparatus for displaying multiple images, which is characterized by being provided with a format conversion circuit in the X and Y directions for changing the address of the image.

Function: The image processing device for displaying multiple images configured in this way has the following features:
By providing a format conversion circuit in the X and Y directions between the address counters in the X and Y directions and the image memory, the image data stored in the image memory itself can be converted into a TV synchronization signal without being replaced. The address of the image data actually read out from the image memory is changed and read out using the output of the format conversion circuit for the address of the image data specified by the address counters in the X and Y directions in synchronization, and the result is +! The image is displayed by swapping the positions of the image and another image.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an image processing apparatus for displaying multiple images according to the present invention. This image processing device includes a central processing unit (CPU) 11, an image memory 12, a synchronization signal generator 13, and address counters 14a and 14 in the X and Y directions.
b and X.

Format conversion circuits 15a and 15b in the Y direction,
Y-direction address registers 16a, 16b and I)/A
It comprises a converter 17 and a display 18.

The image memory 12 stores image data of a plurality of images, and is, for example, a RAM having 1024×1024 pixels in the X and Y directions and 1c16 bits of information in the gradation direction.
(ram), etc., and for example, 16 images of 256×256 pixels are stored. The synchronization signal generator 13 outputs a television synchronization signal S1 consisting of a horizontal synchronization signal and a vertical synchronization signal to the display 18 so as to display an image on the display 18 using the rask scan method. A signal indicating which pixel data in the image memory 12 is to be read out is sent to the X address counter 14a in synchronization with S1.

This X address counter 14a inputs and counts an address progress signal S2 created by dividing the horizontal synchronizing signal of the synchronizing signal generator 13 into, for example, 1024 pieces.
This counting result becomes the address in the X direction of the image data to be read from the image memory 12. Then, the X address counter 14a is set to 1024 from O to 1023, for example.
After counting the number of address progress signals S2, the address progress signal S3 is sent to advance the address in the Y direction by +1. Y
The address counter 14b is the X address counter 1.
The address progress signal Ss sent from the image memory 12 is input and counted, and the result of this counting becomes the address in the Y direction of the image data to be read from the image memory 12.

The format conversion circuits 15a and 15b in the X and Y directions
inputs the output of the X address counter 14a or Y address counter 14b, changes it to another value as appropriate, and outputs it, as if it were the respective address register 1.
The output values of 4a and 14b are converted to each format conversion circuit 15.
It converts as if it were the output value from a and 15b. As a result, the address of the image data read from the image memory 12 is changed as appropriate. Note that the designation of the conversion pattern is performed by the central processing unit 11. X.

The Y-direction address register 168 I 16b inputs and stores the outputs of the X and Y-direction format conversion circuits 15a and 15b, temporarily holds the memory address for the time required by the image memory 12, and Image memory 1
This specifies the address of the image quality data to be read from 2.

The I)/A converter 17 converts the digital value of the image data read out by dividing the image memory 12 into several parts under the control of the central processing unit 11 into an analog signal. The display 18 receives the analog signal converted by the I)/A converter 17 and displays a plurality of images simultaneously. Note that the central processing unit 11
is for controlling each of the above components.

Next, the operation of the image processing apparatus of the present invention configured as described above will be explained. First, as shown in FIG. 2, the image memory 12 has, for example, 1024×1024 pixels, and 256
Assume that 16 x256 pixel images, numbered 1 to 16, are stored. For the sake of simplicity, exchanging image positions only in the Y direction will now be described. At this time, the addresses are divided into four address bands from ■ to ■ by dividing each 256 pixels in the Y direction.

That is, the first stage ■ is O ~ 255, and the second stage ■ is 256 ~
511, 3rd stage ■ is 512-767, 4th stage ■ is 768
~1023. And 210-1024 in the Y direction
To divide the pixel image memory 12 into the four address bands mentioned above, it is possible to express it using the binary coefficients (O or 1) of 2' (-256) and 29 (=512) of the Y address counter 14b. can. In other words, Y address counter 1
The output 28 of 4b has a coefficient of °O'' when the person's number of curls is less than 256, a coefficient of '1'' when 256 input curls are counted, and a coefficient of ``1'' when 256 input curls are counted. .

O''. In other words, O'' and 1'' are inverted every time 256 input pulses are counted. Also, for output 2?, when the manual pulse is less than 512, the coefficient is ° At 0°, if 512 input pulses are counted, the coefficient °
When 512 items are counted, the coefficient becomes "O". In this way, the Y address counter 14
The following Table 1 shows the operation of dividing 2''-e 1024 pixels into four address stages in b.

Table 1 The relationship between the operating times is shown in the timing diagram of FIG. 3.

28 and 2 from such Y address counter 14b.
The output of 9 is input to the Y format conversion circuit 15b. Here, when the contents of the Y format conversion circuit 15b are inputted with the outputs 28 and 29 shown in Table 1 above, a conversion pattern is specified in the central processing unit 11 so that the same value as that is outputted. do. Then, as shown in FIG. 2, the output contents of the Y address counter 14b are directly passed through to the Y format conversion circuit 15b.
The signal is output from the Y address register 16b and input to the Y address register 16b.

Therefore, at this time, the output of the Y address counter 14b is not changed and remains the output of the Y address counter 14b.
Address register 16b specifies the address of image data in image memory 12. That is, in this case, the images are read from the top in the Y-direction address order of the image memory 12, and a normal display in which images 1 to 16 are arranged in order is performed on the screen of the display 18.

Next, unlike the above, in order to convert the contents of the Y format conversion circuit 15b into another value for the output from the Y address counter 14b and output it, use the conversion pattern as shown in Table 2 below, for example. Assume that the central processing unit 11 specifies y5.

Table 2 shows that when the outputs 28 and 22 from the Y address counter 14b are (o, o), it is converted to (ttx), and (Xt
(0,0) when O) and (1,0) when (0°1)
Assume that you specify that (1, 1) be converted to (0, 1). Then, as shown in FIG. 4, the output of the Y address counter 14b is converted as shown in Table 2, output from the Y format conversion circuit 15b, and input to the Y address register 16b. Therefore, in this case, Y
The output of the address counter 14b is changed to another value by the Y format conversion circuit 15b, and the Y address register 16 is changed according to the output value of the Y format conversion circuit 15b.
b specifies the address of the image data in the image memory 12. The operation time relationship is illustrated in the timing diagram of FIG. 5. That is, in this case, the second
As is clear from the table and Figure 784, according to the progress of the addresses in the sum and Y address counter 14b, first the fourth stage ■ of the address register is read out, then the first stage ■, the second stage ■, and the third stage ■. It will be read out. As a result, as shown in FIG.
Images 3 to 16 are displayed, and the following are 1 to 4, 5 to 8, and 9.
12 images are displayed in this order, and the display positions of the images on the screen are switched. In this way, if the conversion pattern of the Y format conversion circuit 15b is appropriately specified by the central processing unit 11, images can be replaced and displayed at any position in the Y direction.

Note that in the above description, for the sake of simplicity, the image positions have been replaced only in the Y direction, but image positions can also be arbitrarily replaced in the X direction as well using the X format conversion circuit 15a in the same manner as described above. Therefore, by using the format conversion circuits 15a and 15b in the X and Y directions, any of the individual images 1 to 16 can be replaced and displayed at any position. Further, the format conversion circuit 15a in the X and Y directions,
15b may be configured with memory. Furthermore, in FIG. 1, format conversion circuits 15a and 15b in the X and Y directions are shown.
Although the X- and Y-direction address registers 16a and 16b are provided between the image memory 12 and the image memory 12, the present invention is not limited thereto, and the address registers 16a and 16b may be omitted. Further, the present invention is not limited to medical images such as contrast X-ray images and xmcT images, but can be similarly applied to various other types of images.

Effects of the Invention As explained above, the present invention is provided with format conversion circuits 15a, 15a, 15a, 15a, 15a, 15a, 15a, 15a, 15a, 15a, 15a, 15a, 20a, 20a, 30a, 30a, 30a, 40b, 50b, 50b, and 15a, 15a, 15a, 15a, 15a, 15a, 14a, 14a, 14b, 44a, 44a, 4b, e.g.
15b, these format conversion circuits 15a and 15b convert the address counters 14a and 15b to each other.
The contents of the output from the image memory 14b are converted appropriately and stored in the image memory 1.
The address of the image data to be read from 2 can be changed and read. Therefore, without replacing the image data itself stored in the image memory as in the past, the image data address designated by the address counters 14a and 14b in the X and Y directions in synchronization with the television synchronization signal is By simply changing the address of the image data read out from the image memory 12 and reading it out, it is possible to swap the positions of one image and another image and display them. As described above, in the present invention, since it is not necessary to completely replace the image data in the image memory 12, the appropriate image replacement operation is simple and the replacement display can be performed extremely quickly. It is possible to prevent a decrease in diagnostic efficiency when a doctor makes a diagnosis.Furthermore, there is no need for a conventional program for replacing image data.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an image processing device for displaying multiple images according to the present invention, Fig. 2 is an operation explanatory diagram showing normal display readout in the display operation in the Y direction, and Fig. 3 is the operation time relationship of the X address counter. FIG. 4 is an operation explanatory diagram showing the readout of replaced display in the display operation in the Y direction, FIG. 5 is a timing diagram showing the operation time relationship of the Y address register at that time, and the igS diagram is the FIG. 7 is a block diagram showing a conventional image processing device of the same type. 11--Central processing unit, 12--Image memory, 13--Synchronizing signal generator, 14a--X address counter, 14b--X address counter, 15a--X format conversion circuit, 15b--・X
Format conversion circuit, 1T...) converter, 18.-Display.

Claims (1)

[Claims] It has an image memory that stores image data of a plurality of images, and an address counter in the X and Y directions that counts address progress signals created by dividing a television synchronization signal and specifies the address of the image data to be read from the image memory. In an image processing device for displaying multiple images, the image data in the image memory is divided into several parts, read out, D/A converted, and displayed on a display at the same time under control from a central processing unit. A format conversion circuit in the X and Y directions is provided between each address counter and the image memory to input the output of the address counter and change the address of the image data read from the image memory. Image processing device for image display.