JPS63225874A - Picture processor - Google Patents

Abstract

PURPOSE:To obtain a special effect for smoothly changing an animation picture by providing a memory for previously maintaining the enlargement ratio and the reduction ratio of a picture and a means for transferring the values to registers for the enlargement and the reduction at a constant cycle. CONSTITUTION:According to the interruption of a joy stick 11, a CPU 10 initially loads an instructed address value to an initial value address register 18 and then, the enlarged/reduced value to a final value address register 19. After the load, a counter 20 receives an instruction from the CPU 10 and continues to count to the final value address. The output of the counter 20 goes to the input address of an enlargement/reduction table memory 16, the respective values are loaded to the reduction register 8, the enlargement regisster 9 at the constant cycle and an enlarged picture or a reduced picture is obtained according to the operation of a reduction circuit 3 and an enlargement circuit 5. Namely, in such a way, by providing the enlargement/reduction table memory 16, the values are loaded to the enlargement register 9 and the reduction register 8 at the constant cycle. Thereby, the size of a window is smoothly changed.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF THE INVENTION The present invention relates to an image processing apparatus that enlarges and reduces an image signal when digitizing and storing the image signal and displaying the image signal.

2. Description of the Related Art A conventional image processing apparatus is shown in the block diagram of FIG. 1 is the image signal, 2 is An2Llogto
Digital Converter (hereinafter referred to as A/D)
, 3: a reduction circuit for converting the digitalized image signal into a reduced image; 4: a frame memory for storing the image; 5: an enlargement circuit for enlarging the image output from the frame memory; 6: a digital to Analog
Converter (hereinafter referred to as D/person), 7 is a C RT (Cathod Ray Tube) that displays images.
8 is a reduction register that holds values that control the reduction circuit 3, 9 is an expansion register that holds values that control the expansion circuit 6, and 1o is a central process.
ingUnit (hereinafter referred to as CPU), 11 is a joystick for operating the window displayed on the CRT display 7, and 12 is an I10 interface for input/output equipment connected to the bus of CPtT10.

As an input/output device, for example, the joystick 11
applies. 13 is the computer data bus, 14
is an address bus, and 15 is a control bus.

The operation of the image processing apparatus configured as above will be explained. FIG. 3 shows a moving image displayed on the CRT displayer explained in FIG. 2. 30 is a screen, 31 is a window that displays the displayed rectangular moving image,
32ba Window B that displays the same rectangular video as 31
It is. If you want to reduce window A31 to window B32 while displaying a video, or
32 to a window person 31, an interrupt is sent from the joystick 11 to the CPU 10 via the % interface 12, data bus 13, address bus 14, and control bus 16. The CPU 10 loads values into the reduction register 8 and enlargement register 9 by interrupt processing.

The reduction circuit 3 and the enlargement circuit 5 enlarge or reduce the image signal 1 based on the values of the reduction register 8 and the enlargement register 9, respectively, and display it on the CRT display 7.

Problems to be Solved by the Invention However, in the above configuration, the reduction register 8 and enlargement register 9 are rewritten by software interrupt processing. Since the time required to determine the value of is varied and the values of both registers change discontinuously over time, changes in the window size lack smoothness, and the visual impression is not good. .

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide an image processing device that enables a special effect to smoothly change the entire moving image.

Means for Solving the Problems The present invention is an image processing apparatus that includes a memory that holds image enlargement and reduction ratios in advance, and means that transfers the values to a register for enlargement and reduction at regular intervals.

Effect of the present invention With the above-described configuration, when a value is loaded from the memory that holds the enlargement and reduction ratios into the enlargement/reduction register at a constant cycle, the value of the enlargement/reduction register changes continuously and the window is changed. The size of the window changes smoothly, resulting in smooth window changes.

Embodiment FIG. 1 shows a configuration diagram of an image processing apparatus in a first embodiment of the present invention. In Fig. 1, image signal 1
2 to the control bus 15 are the same as those shown in the conventional example shown in FIG. 2, so their explanation will be omitted. 16 is an expansion/reduction table memory that stores the values of the reduction register 8 and expansion register 9; 17u is a memory control circuit that controls the expansion/reduction table memory; 18 is an address that indicates the initial values of the expansion register 9 and reduction register 8; 19 is an initial value address register which is a register, 19 is a final value address buster which is an address register indicating the final value of the enlargement register 9 and reduction register 8, 20 is an address counter, and 21 is an address comparator. However, the thin timing signal line is omitted. FIG. 4 shows an overview of the processing in the CPU 1o. 6 and 6 show examples of the contents of the enlargement/reduction table memory 16, in which the left end shows the value of the reduction register 8, the right end shows the value of the enlargement register 9, and the table shows the magnification actually applied to the image.

The operation of the image processing apparatus of this embodiment configured as described above will be described below.

When the joystick 11 interrupts, the CPU 1o first stores the specified address value in the initial value address register 18.
Then, the expanded/reduced address value is loaded into the final value address register 19.

After loading, the counter 2Q receives an instruction from the CPU 10.
continues counting until the final value address. The output of the counter 20 becomes the input address of the enlargement/reduction table memo IJ 16, and the values are loaded into the reduction register 8 and the enlargement register 9 at a constant cycle according to the timing signal of the memory control circuit 1, and the values are loaded into the reduction circuit 3 and the enlargement circuit. An enlarged dog image or a reduced dog image is obtained by the operation in step 5.

As described above, according to this embodiment, by providing the enlargement/reduction table memory 16, values are loaded into the enlargement register 9 and reduction register 8 at regular intervals, thereby smoothly changing the size of the window.

As described in detail, according to the present invention, by adding a simple memory circuit, it is possible to easily change the size of a displayed image smoothly over time, which makes it easy to put it into practical use. The effect is significant.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an image processing device according to an embodiment of the present invention, Fig. 2 is a block diagram of a conventional image processing device, Fig. 3 is an explanatory diagram of an example of image display, and Fig. 4 is an explanation of the operation of CPH. FIG. 6 is an explanatory diagram of an example of an enlargement/reduction table memory. 1... Image signal, 2... A/D, 3.
...reduction circuit, 4...frame memory,
5... Enlargement circuit, 6... D/mu, 7.
... CRT display, 8 ... Reduction register, 9 ... Enlargement register, 10 ...
・C1PU, 11...Joystick, 12
...I10 interface, 13...
Datapath, 14...Address bus, 16...
... control bus, 16 ... expansion/reduction table memory, 17 ... memory control circuit,
18...Initial value address register, 19...
...Final value address register, 20...Counter, 21...Comparator. Name of agent: Patent attorney Toshio Nakao and one other person Takeshi Eiku 1 恢Figure 3 31 Window A Figure 4

Claims (1)

[Claims] A reduction rate setting means for setting a reduction rate N, and a constant cycle set to 1/1.
a first frequency dividing means that divides the frequency by N; a means for writing data obtained by converting an image signal into an analog-to-digital signal at a constant cycle into a memory using a pixel clock obtained by the first frequency dividing means according to the reduction rate setting means; means for setting an enlargement ratio K; means for dividing a constant period by 1/K; and a pixel clock obtained by the second frequency division means according to the enlargement ratio setting means when reading data from the memory. 1. An image processing apparatus comprising: a memory for storing the enlargement ratio and the reduction ratio in advance; and means for transferring the values to a register for enlargement/reduction at regular intervals.