JPH04493A - Display device for information equipment - Google Patents

Abstract

PURPOSE:To enable a CRT display and a liquid crystal display which has a half duty by setting plural display areas on a video RAM and inputting display data in order from the top of an image plane at intervals of IH(one horizontal scanning period) or two upper and lower divided image planes alternately according to modes. CONSTITUTION:The display area on the multi-port video RAM 2 is divided into upper and lower areas and set by a display area setting means 43 and an address generating circuit 3. Then, when a CRT mode is set in the setting register of a display equipment, the contents of the RAM 2 are supplied to a CRT 5 through a display converter 4 in order from the top of the image plane at intervals of IH according to the address from the circuit 3. When a liquid crystal mode is set in the register 41, on the other hand, IH data from the two upper and lower divided areas of the RAM 2 supplied to a liquid crystal display device 50 which has a half duty cycle alternately. This simple, small- sized constitution which requires no display frame memory switches the CRT display and liquid crystal display selectively.

Description

[Detailed description of the invention] [Industrial application field] It is installed in information equipment that has the function of driving different types of display bodies.

[Prior Art] Generally, displays in the field of information equipment use a method of displaying information by sequentially sweeping the screen from the edge of the display screen.

Figure 7 shows a CRT (cathode) as a display body as a conventional technology.
ray tube display) and a liquid crystal display. Dual Baud) RAki (Multi Baud I...
Random access memory) to video R to M
The video RAM 2 has an arithmetic unit 1 that reads and writes display data of 2 through a parallel data bus 6, and an address 7 is inputted to the video RAM 2 from an address generation circuit 3. Display data is output from the serial data bus 8 and input to the display data conversion circuit 4. CR from display data conversion circuit 4
Display data 9 is manually input to T5 and displayed on the screen of CRT5. On the other hand, the display data 9 is input to the frame buffer memory 49 corresponding to one screen of the liquid crystal display, and is connected to the data bus 45 for the upper half screen of the liquid crystal display 50 by the frame buffer address 48 from the frame buffer address generation circuit 47. It is separated into a data bus 46 for the lower half screen, and display data for the liquid crystal is taken out.

FIG. 8 shows an area set inside the video RAM 2 and a CRT
This is an example in which the images are combined and displayed on the screen of No. 5.

Set areas 10.11.12 on video RAM 2. Each area has consecutive addresses along the horizontal line of the CRT5 screen, and the capacity of each area is the number of horizontal lines that each area occupies on the CRT δ screen, with data for both screens minus the horizontal edge as a unit. Set by 40. The position setting of each area on the video RAM is the display data address 39 of the upper left corner of each area when each area is displayed on the screen.
This is done by

FIG. 9 shows the order in which display addresses are input to the video RAM 2 for display on the CRT 5.

Outputs the CRT5 screen in a horizontal line direction from the top left,
- For each horizontal line output, move to the horizontal line at the bottom of the screen, repeat this, and output the address of one screen. Since a multi-baud RAM is used as the video RAM 2, there is no need to input all the addresses of the screen to the video RAM in the horizontal line direction due to the function of the serial baud register. (Since the display addresses are continuous in the horizontal line direction, it is possible to extract continuous data from the video RAM > x 2 using only the serial clock from the serial port of the multi-board RAM.) Figure 10 shows the video RAM. 2 illustrates the output order of address 7 and display data 8 to CRT 2 and display data 9 to CRT. Address 7 in Figure 0 ignores the access from the arithmetic unit 1; in reality, the address for access by the arithmetic unit 1 is interrupted, but in this figure, only the address for display is shown. . address 25
The display data 31 from the video RAM is output,
Similarly, 27 to 33 and 29 to 35 are output. 3
The display data 1, 33, and 35 are sequentially input to the display data conversion circuit 4, and display data 9 is generated on the CRT. The display data 9 has the same symbols 31, 33, .
35, but 31.33. of display data 9.
35 are data converted from display data 31, 33, and 35 by the display data conversion circuit 4, respectively.

[Problems to be Solved by the Invention] As an example, the problem is to construct a low-cost and compact information device that can display on both a CRT and a liquid crystal display. In the conventional address generation technology for the video RAM for the CR7 display, the data from the video RAM 2 is transferred to the liquid crystal display, which needs to be driven at a duty that is half the number of horizontal lines of the CRT. It cannot be output as is. Because the liquid crystal display
Due to display quality issues such as contrast and viewing angle, the driving duty of the liquid crystal display is limited, so it becomes necessary to drive half the number of horizontal lines of a CRT. Only half of the number of lines can be displayed. Therefore, in order to ensure the same number of horizontal lines as CRT, two of the above liquid crystal display bodies were combined vertically and γα
A crystal display body 50 is configured. Therefore, it is necessary to manually input display data to the upper half screen and the lower half screen alternately or simultaneously. This may be the reason why the conventional address generation technology for the video RAM cannot directly use the data from the video RAM 2 for the iα crystal display. For this reason, in an information device that can display on both the conventional CRT 5 and the liquid crystal display 50 that is configured with a liquid crystal display that needs to be driven at half the duty of the CRT 5, the order in which the display data 8 from the video RAM 2 is It outputs the CRT display data 9 as it is to the CR-T, stores the display data 9 for one screen in the frame buffer 49, and inputs the display address 48 from the LCD display address generation circuit 47 to the frame buffer 49. The output order of display data is converted according to the order, and the display data for the liquid crystal display is 45.46
is output from the frame buffer 49) and displayed on the liquid crystal display 5.
It was displayed as 0.

The main object of the present invention is to make it possible to display on a CRT 5, as an example, and also on a liquid crystal display 50 composed of a liquid crystal display with half the duty.Furthermore, according to the present invention, - For example, the conventional frame buffer memory 49 required for displaying on a liquid crystal display is not required, and therefore, the purpose is to reduce the size and cost.

[Means for Solving the Problems] The present invention includes a video RAM (random access memory) that stores display data, and an arithmetic device that can read and write the display data of the video RAN1. Display device--An information device that displays information based on display data has means for setting a plurality of display areas in the video RAM, and simultaneously displays the plurality of set display areas on the screen of the display device. There is a mode in which the human input of the display data to the display device is performed sequentially from the upper line of the screen in one horizontal line, and a mode in which the screen is divided into two in the vertical direction and between each of the two divided screens. It has a horizontal line, especially a mode for inputting display data,
The present invention is characterized by comprising means for switching the mode depending on the type of display device to be connected.

[Function] It has means for setting multiple display areas within the video RA, and has a function of simultaneously displaying the plurality of display areas set above on the screen of the display device, and displays display data on the display device. There is a mode (CRT mode) in which human power is applied to each horizontal line sequentially from the top line of the screen, and a mode in which the screen is divided into two in the vertical direction, and data is displayed alternately for each horizontal line between the two divided screens. The information device has a mode (liquid crystal display mode) in which the horizontal lines of the upper and lower screens are manually input at the same time, and has means for switching depending on the type of display device to be connected.

[Example] FIG. 1 shows an example of the present invention. A multi-board RAM is used as the video RAM2. It has an arithmetic unit 1 for reading and writing display data through a parallel data bus 6 of a video RAM 2, and an address 7 is inputted to the video RAM 2 from an address generation circuit 3. Display data is output from the serial data bus 8 of the video RA ki 2 and input to the display data conversion circuit 4. For example, if the CRT mode is set in the setting register 41 of the display device, the mode will be such that display data is input to the display device one horizontal line at a time, starting from the horizontal line at the top of the screen, and the display data will be input in the above order. The signal is converted by the conversion circuit 4, output to the CRT 5, and displayed on the CRT 5.

The order of display data output to the CRT 5 is the order shown in FIGS. 7 and 8. For example, when the liquid crystal display mode is set in the setting register 41 of the display device, the display screen is divided into two in the vertical direction, and display data corresponding to the horizontal lines of each divided screen is alternately input to the display device manually. becomes. The display data conversion circuit 4 shown in FIG. 1 outputs liquid crystal display data alternately as liquid crystal display data 9 for the upper half screen and liquid crystal display data 13 for the lower half screen.

FIG. 2 explains the address generation circuit 3 that realizes two modes, the CRT mode and the liquid crystal display mode, which are the above-mentioned examples. The address generation circuit 3 has horizontal line counters 14 and 15, and display address generation circuits 16 and 17 that generate a display address based on information in the display area setting register 43 of the video RAM. Display address generation circuits 16 and 17 correspond to horizontal line counters 14 and 15, respectively, and the counter value of the horizontal line counter (counts the number of horizontal lines from the top of the screen).
specifies the horizontal line position on the screen where the address should be generated. Information 44 from the display area setting register 43 indicating the display i1a set on the video RAM 2 while counting up the horizontal line counter (on the screen occupied by the display area indicating the start address of each display area and the capacity of each display +1@) The display address of the horizontal line indicated by the horizontal line counter is generated by taking in the number of horizontal lines at any time. When the liquid crystal display mode is set in the display device setting register 41, the display atmos generation circuit 1
6.17 both take in the start address of the first display area and become the display address of the horizontal line at the top of the screen. Next, as the horizontal line counter counts up, the display address is counted up by the difference from the address one horizontal line below on the screen, and the display address for one line below is generated by the number of horizontal lines indicating the capacity of the display area. The above count-up is repeated to complete display address generation for one display 1avi. Thereafter, the start address of the next display area is taken in, and the display address is generated while counting up the address in the same manner as above. Each of the horizontal line counters 14 and 15 always starts counting from the horizontal line at the top of the screen, without being aware of the division of the screen into two, but after counting up to half the screen, the horizontal line counter 14 counts up to half the screen and then waits for the vertical retrace period of the display. and counts up the remaining horizontal lines on the screen during the vertical retrace period, returning to the horizontal line at the top of the screen. On the other hand, horizontal line counter 1
5, counts up the horizontal lines of the upper half of the screen in advance during the vertical retrace period, and at the beginning of the display period, counts up to a count value indicating the topmost horizontal line of the lower half of the screen. At the beginning of the display period, the horizontal line counter 14 indicates the horizontal line at the top of the screen, and the horizontal line counter 15 indicates the horizontal line at the top of the lower half of the screen.

During the display period, the horizontal line counter 14 counts up the horizontal lines in the upper half of the screen, and the horizontal line counter 15 counts up the horizontal lines in the lower half of the screen. Along with the above count-up, the display address generation circuit 16 generates a display address for the upper half of the screen, and the display address generation circuit 17 generates a display address for the lower half of the screen. FIG. 3 shows the relationship between the count-up of the horizontal line counters 14 and 15, the display period, and the vertical retrace period in the liquid crystal display mode.

When the CRT mode is set in the display device setting register 41, the horizontal line counter]4 and display address generation port #i1
6 becomes valid, and the horizontal line counter 15 and display address generation circuit 17 have no meaning. The display address is generated in the same way as in the liquid crystal display mode, but the horizontal line counter counts up all the horizontal lines on the screen during the display period, and the 1 display address generation circuit 16 displays all the lines on the screen. generate a file. FIG. 4 shows the relationship between the count up of the horizontal line counter 14, the display period, and the vertical retrace period in the CRT mode.

Returning to FIG. 2, the address generation circuit 3 outputs a display address 22 which is the output of the display address generation circuit 16, a display address 23 which is the output of the display address generation circuit 17, and a signal for accessing the video RAM 2 of the arithmetic unit. Address 24, which is the output from address generation circuit 18, is multiplexed by address multiplex circuit 19 and output as address 7 of video RAM 2.

In CRT mode, address 23 is never selected.

5 and 6, the relationship between address 7, display data 8, and converted display data 9.degree. 13 in the single alpha crystal display mode will be explained in relation to the positions on the screen. The atsis corresponding to the top horizontal line 25 of the upper half screen area in FIG. 5 is outputted first to address 7, and then the address corresponding to the top horizontal line 26 of the lower half screen area is outputted. .

Next, the address corresponding to the second horizontal line 27 from the top of the upper half of the screen is output to the screen, and then the address corresponding to the second horizontal line 28 from the top of the lower half of the screen is output. Ru.

Similarly, the addresses corresponding to the horizontal lines of the upper half screen and the lower half screen are alternately output to address 7, and the address of the entire screen is output. Then the first horizontal line 2 above
Return to address 5 and repeat this cycle. FIG. 6 shows the correspondence between the above AFL/SFF and display data 8 and display data 9 and 1o after conversion. Display data corresponding to addresses 25, 26.27.28.29.30 of the video RAM are respectively 31. 32. 33. 34. 35
．． 36 shows how the display data corresponding to the upper and lower screens are alternately output to the display device (liquid crystal display).
38 shows how the display data for the upper and lower parts of the screen are simultaneously output. In this embodiment, the signals are output alternately as shown at 37, and displayed on two liquid crystal displays connected to each other with a duty half that of a CRT.

[Effects of the Invention] The present invention makes it possible to simultaneously display a plurality of configurable areas in a video RAM on different types of display bodies, and has the effect of widening the scope of use of information equipment, and meets the demand for reducing power consumption. In such situations, only the liquid crystal display can be operated. Furthermore, since it does not require memory as a frame buffer, which was required in the past for displaying on both a CRT and a liquid crystal display, power consumption is reduced, equipment space is reduced, and manufacturing costs are reduced. I can do it.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram according to the present invention, FIG. 2 is an internal block diagram of FIG. 1 and 3 in FIG. 1 according to the present invention, and FIG. 3 is a horizontal line counter in liquid crystal display mode according to the present invention. FIG. 4 is a timing chart showing the operation of the horizontal line counter in the CRT mode according to the present invention, and FIG. FIG. 6 is a timing chart showing the display system of the present invention and the output order of display data to a display device, FIG. 7 is a block diagram showing the entire conventional system, and FIG. 8 is a conventional video RAM.
The correspondence between the block diagram of the display area set in the display screen and the display screen (Figure 9 is a diagram showing the system, Figure 9 is a diagram showing the output order of the display atom on the screen when displaying on a conventional CRT, Figure 10 The figure is a timing chart showing the output order of display addresses and display data to a CRT in a conventional display on a CRT. 102. Arithmetic unit 2, 3, 4, 5, 6, 7 , , . 8, , . 9, , . 13, . 41, . 42, . 43, . 44, . 50, . 14, . 15, . 16, . 17, . 18, . 19, . Video RAM address Generation circuit display data Conversion circuit display (CRT) Discrete data bus address Serial data bus (display data) Display data after conversion Display data after conversion Display device setting register Display device setting information Display area setting register Display area setting Information display (liquid crystal display) Horizontal line counterHorizontal line counter displayAddress generation circuitDisplay address generation circuitAddress generation circuit for arithmetic unitAddress multiplex circuitHorizontal line count valueHorizontal line count value displayAddress displayAddress screen for address arithmetic unit Display address of the upper horizontal line Display address of the uppermost horizontal line in the lower half area of the screen 27, Display address of the horizontal line immediately below .25, Display address of the horizontal line immediately below 26 29 , display address 30 of the horizontal line immediately below .27, display address 31 of the horizontal line immediately below .28, display data 32 corresponding to the display address of .25, display data 20 corresponding to the display address of .26.゜21゜22゜23゜24゜25. 26゜33゜34゜35゜36゜37゜38゜45゜46゜47゜48゜49゜10゜, display data corresponding to the display address of 27, Display data corresponding to the display address, display data corresponding to the display address 29, display data corresponding to the display address 30, timing chart when display data is alternately manually input to the display device, display data is simultaneously input to the display device Timing chart for manual operation, data bus for the upper half screen of the liquid crystal display. Data, data bus for the lower half screen of the liquid crystal display. Data, frame buffer address generation circuit, frame buffer address, frame buffer memory, Third display area 11° 12° 39° 40° Second display area First display area Start address of each display area Number of horizontal lines indicating the capacity of each display area Applicant Seiko Epson Co., Ltd. Agent Attorney Kisabe Suzuki et al. Figure 3 Figure 5 Figure 6 Figure 8

Claims (1)

[Scope of Claims] A video RAM (random access memory) that stores display data, and an arithmetic unit that can read and write the display data of the video RAM, the video RAM
An information device that displays information on a display device based on display data, the information device having means for setting a plurality of display areas in the video RAM, and displaying the plurality of set display areas simultaneously on the screen of the display device. There is a mode in which the display data is input to the display device sequentially from the upper line of the screen for each horizontal line, and a mode in which the screen is divided into two in the vertical direction and the input data is inputted between each of the two divided screens. A display device for information equipment, comprising a mode for inputting display data for each horizontal line, and means for switching the mode depending on the type of display device to be connected.