JPS6221555U - - Google Patents

Info

Publication number
JPS6221555U
JPS6221555U JP11389085U JP11389085U JPS6221555U JP S6221555 U JPS6221555 U JP S6221555U JP 11389085 U JP11389085 U JP 11389085U JP 11389085 U JP11389085 U JP 11389085U JP S6221555 U JPS6221555 U JP S6221555U
Authority
JP
Japan
Prior art keywords
field effect
effect transistors
coil
source
series
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11389085U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11389085U priority Critical patent/JPS6221555U/ja
Publication of JPS6221555U publication Critical patent/JPS6221555U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48092—Helix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例の平面図、第２図は
第１図のＦＥＴモジユールの等価回路図、第３図
は本考案の別の実施例の平面図である。 １：ＭＯＳＦＥＴ、２：金属基板、３：ソース
共通端子、４：ゲート共通端子、５：Ａｌ線、６
：メタライズ絶縁板、７，７１：コイル。 1 is a plan view of one embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of the FET module of FIG. 1, and FIG. 3 is a plan view of another embodiment of the present invention. 1: MOSFET, 2: Metal substrate, 3: Source common terminal, 4: Gate common terminal, 5: Al wire, 6
: Metallized insulating plate, 7, 71: Coil.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 並列接続された電解効果トランジスタを備える
ものにおいて、電界効果トランジスタのそれぞれ
のソースにコイルが直列接続されたことを特徴と
する電界効果トランジスタモジユール。 A field effect transistor module comprising field effect transistors connected in parallel, characterized in that a coil is connected in series to each source of the field effect transistors.
JP11389085U 1985-07-25 1985-07-25 Pending JPS6221555U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11389085U JPS6221555U (en) 1985-07-25 1985-07-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11389085U JPS6221555U (en) 1985-07-25 1985-07-25

Publications (1)

Publication Number Publication Date
JPS6221555U true JPS6221555U (en) 1987-02-09

Family

ID=30996113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11389085U Pending JPS6221555U (en) 1985-07-25 1985-07-25

Country Status (1)

Country Link
JP (1) JPS6221555U (en)

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