JPS6221555U - - Google Patents
Info
- Publication number
- JPS6221555U JPS6221555U JP11389085U JP11389085U JPS6221555U JP S6221555 U JPS6221555 U JP S6221555U JP 11389085 U JP11389085 U JP 11389085U JP 11389085 U JP11389085 U JP 11389085U JP S6221555 U JPS6221555 U JP S6221555U
- Authority
- JP
- Japan
- Prior art keywords
- field effect
- effect transistors
- coil
- source
- series
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48092—Helix
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
第1図は本考案の一実施例の平面図、第2図は
第1図のFETモジユールの等価回路図、第3図
は本考案の別の実施例の平面図である。
1:MOSFET、2:金属基板、3:ソース
共通端子、4:ゲート共通端子、5:Al線、6
:メタライズ絶縁板、7,71:コイル。
1 is a plan view of one embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of the FET module of FIG. 1, and FIG. 3 is a plan view of another embodiment of the present invention. 1: MOSFET, 2: Metal substrate, 3: Source common terminal, 4: Gate common terminal, 5: Al wire, 6
: Metallized insulating plate, 7, 71: Coil.
Claims (1)
ものにおいて、電界効果トランジスタのそれぞれ
のソースにコイルが直列接続されたことを特徴と
する電界効果トランジスタモジユール。 A field effect transistor module comprising field effect transistors connected in parallel, characterized in that a coil is connected in series to each source of the field effect transistors.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11389085U JPS6221555U (en) | 1985-07-25 | 1985-07-25 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11389085U JPS6221555U (en) | 1985-07-25 | 1985-07-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6221555U true JPS6221555U (en) | 1987-02-09 |
Family
ID=30996113
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11389085U Pending JPS6221555U (en) | 1985-07-25 | 1985-07-25 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6221555U (en) |
-
1985
- 1985-07-25 JP JP11389085U patent/JPS6221555U/ja active Pending
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