JPS62214467A - Multiprocessor instruction control system - Google Patents

Abstract

PURPOSE:To prevent the processing of a vector instruction from being kept waiting for a long time by giving the use right of a vector unit to a scalar unit where the processing is suspended when the waiting time of the processing reaches a prescribed value. CONSTITUTION:If a vector instruction is taken out in a scalar unit 21 and the unit 21 is set to the state waiting for start when the vector instruction from a scalar unit 20 is executed in a vector unit 1, a vector timer 122 corresponding to the scalar unit 21 is started. When a specific time elapses thereafter, an instruction switching control circuit 123 gives the use right of the vector unit 1 to the scalar unit 21 by the change of the value of a specific bit in the timer 122. As the result, the vector instruction in the waiting state in the scalar unit 21 is supplied to the vector unit 1 and is processed.

Description

[Detailed Description of the Invention] (Table of Contents) Overview Industrial Application Fields Prior Art and Problems to be Solved by the Invention Means for Solving Problems Action Embodiments Effects of the Invention [Overview] At least scalar instructions A plurality of scalar units (SUo, t) that process
In a multiprocessor system consisting of a vector unit (VU) that processes vector instructions sent from (UO, l), the vector unit (VU)
An instruction switching control circuit (ICC) for changing the right to use the vector unit given to one of the plurality of scalar units (SU.+1), and each scalar unit (SU.
A vector timer (VUTO, νUT) that counts the waiting time for vector instruction processing for each
I), each vector timer (VLI
When a change in a specific bit of the vector timer (VUTo, VIIT+) is detected, the scalar unit (SUoy) corresponding to the vector timer (VUTo, VUTo) is given the right to use the vector unit l-(VU). It is something.

[Industrial application field]

The present invention relates to a multiprocessor instruction control system, and in particular, a plurality of scalar units (SU) that process scalar instructions.
In a multiprocessor system consisting of a vector unit (VU) that processes vector instructions sent from these scalar units (SO), each scalar unit (SU) has the right to use the vector unit I-(VU). Concerning a control method that dynamically changes the

In general, in multiprocessor systems for science and technology that are composed of a scalar unit (SU) and a vector unit (VU), the scalar unit (SU) By providing a plurality of , it is possible to optimize the processing of scalar instructions and vector instructions.

In this case, control for switching the plurality of scalar units (SO) is required.

On the other hand, with recent advances in computer technology, there is a trend toward online multiprocessor systems for science and technology, and in order to improve the man-machine interface, as the number of terminals increases, response times are becoming increasingly shorter. Improvement is now required.

In addition, with the recent diversification of the amount of data processed, the amount of programs is also increasing, and file memory (FM
) and other input/output devices (Ilo) are increasing, and it is necessary to improve the responsiveness of the input/output devices (Ilo) to data input from the above-mentioned terminals, as well as countermeasures against overrun errors in the input/output devices (■10). is required.

Since control over the terminal 7 input/output device (Ilo) is executed by the input/output instruction (SIO) issued in the scalar unit I-(SIJ), a plurality of scalar In a multiprocessor system in which units (SO) are connected and the right to use the vector unit (Vtl) is switched to each scalar unit (SO), the vector unit (VU) is assigned to each scalar unit (SU). Therefore, effective measures have been required to prevent the issuance of input/output commands to the terminal/input/output device (Ilo) E from having to wait.

[Prior art and problems to be solved by the invention] FIG. 5 is a diagram showing an example of the configuration of a conventional multiprocessor system for science and technology.

In this figure, 1 is a vector unit (VU) that processes vector instructions, 20.21 is a scalar unit (SU'o, t) that processes scalar instructions, 3 is a main storage unit (MSU), and 4 is a storage control unit. (MCU)
, 11 is a unit (VEU) that executes vector instructions.
A load pipeline (LOAD) 110 that transfers data to and from the main storage unit (MSU) 3, and a store pipeline (STOI?) 111. and a vector register (VR) 112 that holds vector data, and addition for executing a vector instruction that reads vector data from the vector register (VR) 112, performs an operation, and writes the result to the vector register (VR) 112. Pipeline (ADD) 113, Multiplication pipeline (MULIT) 114. Division pipeline (D
IVIDE) 115 is provided. And 12
is a unit (VCU) that controls vector instructions, and controls the vector instruction execution unit (VEU) 11 described above.

In general, with conventional technology, depending on the structure of the science and technology program, the usage rate of vector unit (VU) 1 may become extremely small. ) (VU), multiple (in this example, two) scalar units (S
Uo, 1) Connect 20 and 21 and create a vector unit (
A multiprocessor system has been developed that improves the utilization of the vector unit (VU) 1 by increasing the number of vector instructions input to the vector unit (VU) 1.

However, in such a multiprocessor system, one scalar unit (Sue, or 5UI
) uses one vector unit (VU) for a long time, the processing of the other scalar unit (SUI or 5UO) is made to wait for a long time, and the other scalar unit (SUI)
, or 5Uo), or an input/output internal ff
There were problems in that the response time of (Ilo) was slow and there was a risk of an overrun error occurring.

In view of the above conventional drawbacks, the present invention provides a plurality of scalar units (5 units) for one vector unit (VU).

, ~) are connected, the purpose of this is to provide a multiprocessor instruction control method that does not require the processing of vector instructions in each scalar unit (SUo, t~) to wait for a long time. It is.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of a multiprocessor system according to the present invention.

In the present invention, at least a plurality of scalar units (SUO, I) 20.21 that process scalar instructions, and these scalar units (SUO, l) 20.21
In a multiprocessor system consisting of a vector unit (V[I) 1 that processes vector instructions sent from a vector unit (V[I) 1, the vector unit (VU) 1
within, the plurality of scalar units 1-(suo, t)
20. Vector unit (VU) given to one of 21
) Instruction switching control circuit (IC
C) 123 and each scalar unit (SO(1,1)
20. Every 21 cycles, a vector unit (VU) 1 is not given the right to use, so a VU timer (VUT
o, Vt1T+) 121°122, and the above vector tie? (VUTO, VUTI) In each of 121.122, due to a change in a specific bit,
Its vector timer (VUT, , VUT1) 121,
122 D Corresponding SCARA unit (SUO, 1) 20
．． 21 is configured to give usage rights to the vector unit (VU) 1.

[Effect]

That is, according to the present invention, at least a plurality of scalar units (SIJo, +) that process scalar instructions, and a vector unit (VU) that processes vector instructions sent from these scalar units (SUO1+). In the multiprocessor system, the vector unit (VU) includes an instruction switching control circuit (ICC) for changing the right to use the vector unit given to one of the plurality of scalar units (SUo, t). )and,
By providing a vector timer (VUTo, VUT1) for each scalar unit (SUo, +) to count the time that vector instruction processing is waited, it is possible to detect when a specific bit of each vector timer (VUTo, VUTO has changed). When this is detected, the vector timer (VUT
o, VUTI) corresponding to the scalar unit (SUO, l
) is given the right to use the vector unit (VU), so the processing of subsequent scalar instructions does not have to wait for a long time while waiting for vector instruction processing, and the terminal, This has the effect of making it possible to construct a multiprocessor system with less adverse effects on the input/output device (Ilo).

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a diagram showing an embodiment of the present invention, showing details of a vector instruction control unit (VCU), and FIG. 3 is a diagram showing details of a vector timer change detection circuit. FIG. 4 is a diagram showing an example of instruction processing according to the present invention, in which the instruction switching control circuit (IC) in FIG.
C) 123a, b, and vector timer (VUT(+
, VUTυ121.122 and its related mechanisms are the necessary means for carrying out the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

First, a vector instruction is sent from the scalar unisoto (SUo) 20 to the vector fetch storage register (hereinafter referred to as VFSRo) 1241.

At this time, if there is no instruction in both the vector predecode storage register (hereinafter referred to as VPSR) 1245 and the vector fetch buffer (hereinafter referred to as VFBO) 1242, the VPSR,
The vector instruction is moved to 1245.

Vl''SR, +245 or when a vector instruction is contained in VFBO 1242, the vector instruction is buffered from VIISRO 1241 to VFBO 1242.

When the preceding instruction exits from VPSR, 1245, VF
When a vector instruction enters BO1242, the corresponding VFI
The vector instruction is input from lo 1242 to VPSR 1245 at the next timing via selector (SEL) 1244.

The above control is referred to as fetch control O (hereinafter referred to as FC).

), 1243.

Above (7) VPSRo 1425 is a decoder (DEC)
This is an instruction register for decoding vector instructions by 124B and performing exception checking by an exception check circuit (ECo) 1249.

Also, the above FC, 1243 is VFBO1242, and VP
The number of instructions in SRO1245 is counted, and VF
When RO1242 is full, OR game) (OR) 1
246, the VU FULL signal is sent to the scalar unit (SUo) 20, and the scalar unit (SUo)
) Functions to inhibit the sending of instructions from 20.

The above operation is performed in exactly the same way for vector instructions sent from the scalar unit (SU+) 21.

In the instruction switching control section (ISC) 123b,
Scalar unit (su1) 20 and Scalar unit (
Set/reset latch (SR) 1234 and 1 determines the right to use SUO21 vector unit (VU) 1
235, each scalar unit (SUO, I)
20.21.

When the output of latch (SR) 1234 is 0°, it indicates that SCARA unit l-(suo) 20 is not granted VU usage rights. At this time, through the above OR gate (OR) 1246, VU FULL (7)
A signal is sent to the scalar unit (Sue) 20, and the sending of instructions from the scalar unit (Sue) 20 is suppressed.

When the output of latch (SR) 1234 is 1'te, VP
An instruction code is sent from the SR01245 to the vector queue stage register (hereinafter referred to as VQSR) 126 through the AND circuit 1200.

At the same time, a decode signal from a decoder (DEC) 1248 passes through an AND circuit 1202 to vector instruction management (
VIS) VEU Core Troll Unit (V
HU CU) 1274.

The vector instruction management (VIS) 127 manages the start and execution of vector instructions, and the register 1273 holds the instruction code being executed.
An instruction code is sent to the vector instruction execution unit (VEU) 11 shown in the figure.

Above VEIJ: 17 Troll Unit (VEU CO)
At 1274, the instruction being executed is managed by the instruction code in the register 1273 and a control signal (not shown) sent from the vector instruction execution unit 1-(VEU) 11.

The above operation functions in exactly the same way even when the latch (SR) 1235 is 1.

Latch (SR) 1234 and 1235 are in an exclusive relationship, and the output of latch (SR) 1234 is
1, the vector timer change detection circuit (hereinafter referred to as VT
When a set signal 1231 is sent from the CD (CD) 123a, the output of the AND circuit 1239 becomes "1", the latch (SI?) 1234 is reset, and the latch (SR) 1235 is set. (SR) The output of 1235 becomes 1.

Next, when the cent signal 1230 is sent from the VTCD 123a, the output of the AND circuit 1238 becomes l', the latch (SR) 1235 is reset, and the latch (SR) 1234 is set. The same operation is repeated thereafter.

Next, a detailed example of the vector timer change detection circuit (VTCD) 123a will be described with reference to FIG.

A 1-bit value sent from vector timer O (hereinafter referred to as vuTo) 120 is input to latch 123a0. If the value of the bit node changes from "1" to 0', the output of the AND gate 123a becomes 1', and the output 1230 of the OR gate 123az becomes 1'.

Similarly, if the value of the above bit changes from °O' to °1, the output of the AND gate 123as will be °1°.
Then, the output 1230 of the OR gate 123az is.

It becomes 1′.

The same applies to the operation mode of the output 1231 of the OR gate 123a6.

Next, an example of instruction processing according to the present invention will be explained with reference to FIG. 4 while referring to FIG.

First, in the scalar unit (SUo) 20 and the scalar unit (SU1) 21, scalar instructions (S+, Sz and SI'+SZ'+Sff') are processed as shown.

Soshite, the aforementioned Nora y Chi (SR) 1234 (SUo
Assuming that the correspondence) is set to "1", a vector instruction (vl) is sent from the scalar unit (suo) 20 to the vector unit (VU) 1 at the timing To.

If the present invention is not implemented, the vector timer)
In the (VU) 1, vector instructions up to V, -V0 are processed, while on the scalar unit (SU+) 21 side,
The next vector instruction (VI') after the scalar instruction (sio)
) will have to wait.

However, when the present invention is implemented, the scalar unit (
su+) In 21, the above vector instruction (V+')
When the vector instruction is fetched and is in a state of waiting for startup, a signal VIW indicating that the vector instruction is waiting for startup is output, and the vector timer (VUT) corresponding to the scalar unit (su1) 21 is output by the AND circuit 129.
1) When +22 is activated and the timing of T1 is reached after a specific time has elapsed, the value of the specific bit changes, causing the output line 1231 of the VTCD 123a to become 1.
°, reset the latch (SR) 1234,
Set latch (SR) 1235 and use right of vector unit (VU) 1 becomes scalar unit (SU+)
It can be switched to 21.

As a result, the vector instruction (V+") that was in the waiting state in the scalar unit (SO,) 21 is transferred to the register 127.
3, and input to the vector unit (VU) 1 for processing.

In FC, 1253, the vector instruction (v+')
is input to the vector unit (VU) 1, and by recognizing that the processing has ended at timing T2 and detecting that there is no subsequent vector command, the latch (SR) 1234 is activated by the switching control signal C31. Operates to set vector unit (VU)
1 is again passed to the scalar unit (SUO) 20, and the vector instruction Vl+""V! . functions so that the processing is executed.

Next, another example of the vector timer change detection circuit (VTCD) 123a will be explained with reference to FIG. 3(b).

This vector timer change detection circuit (VTCD) 123a
In this case, a specific bit of the vector timer (VUTo) 121 changes, and the output of the OR gate 1238z becomes “
When it becomes 1, latch (sR) 123bo is set.

Then, the vector timer (VUTO) 121
When a specific bit changes, the output line 1230 of the VTCD 123a is set to "1".

The latch (SR) 123bo is the signal VIW indicating waiting for activation of the vector instruction described above. It is reset when becomes 0''.

Therefore, this vector timer change detection circuit (VTCD) 1
23a, the above vector timer (VU
TO) The switching signal 123 is activated within a time period that is at least 1 to 2 times the time period that the 121 is counting.
The feature is that it functions to bias 0.

The same applies to the vector timer (VUTI) 122 side.

In this way, the present invention allows multiple scalar units (e.g., SUo, +) to form one vector unit (VU).
In a multiprocessor system connected to
When the execution of the vector instruction continues in each scalar unit l-(SUO, l), when the execution of the vector instruction ends within the specific time after counting the passage of a specific time, the completion signal is sent. The feature is that the right to use the vector unit (VU) is alternately switched by detecting the vector unit (VU).

〔Effect of the invention〕

As described above in detail, the multiprocessor instruction control method of the present invention includes at least a plurality of scalar units (SUo, +) that process scalar instructions and instructions sent from these scalar units (SUo, 1). In a multiprocessor system composed of a vector unit (VU) that processes incoming vector instructions, the plurality of scalar units (VU) described above are included in the vector unit (VU).
An instruction switching control circuit (ICC) changes the right to use the vector unit given to one of the scalar units) (Sυ., υ), and counts the time during which vector instruction processing is waited for for each scalar unit) (Sυ., υ). Vector timer (VU
TO, VUTI), when it is detected that a specific bit of each vector timer (VUT, VUT1) has changed, the vector timer (VUTo, VUTI)
In the scalar unit (SUO, +) corresponding to UTI),
Since the right to use the vector unit (VU) is granted, the processing of subsequent scalar instructions does not have to wait for a long time due to waiting for vector instruction processing, and terminals, input/output devices ( This has the effect of making it possible to construct a multiprocessor system that has less negative influence on Ilo).

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of a multiprocessor system according to the present invention. FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a diagram showing details of the vector timer change detection circuit. FIG. 4 is a diagram showing an example of instruction processing according to the present invention. FIG. 5 is a diagram showing an example of the configuration of a conventional multiprocessor system for science and technology. It is. In the drawing, 1 is a vector unit (VU). 11 is a vector instruction execution unit (VEU). 110 is a load pipeline (LOAD). 111 is a store pipeline (STORE). 112 is a vector register (VR). 113 is an addition pipeline (ADD). 114 is multiplication pipe life (MULTI). 115 is the division pipe life (DIWIDE). 12 is a vector instruction control unit l-(VCU). 120 is a selector (St!L). Is 121 a vector tie? (VUTO) Is 1122 a vector tie? (VUTl) +123 is an instruction switching control circuit (IOC). 123a is a vector timer change detection circuit (VTCD)
. 1230 and 1231 are output lines or switching signals of the VTCD 123a. 123b is an instruction switching control unit (ISC). 1234 is a latch (SR) for the scalar unit (su1) 20; 1235 is a launch (SR) for the scalar unit (SO,) 21. 20 is a scalar unit (SUo). 21 is a SCARA unit (SU+). 3 is the main storage unit (MSU). 4 is a storage control unit (MC1l). (A Tsube 2F Le 9A Macross 4 Exit name O details 1 Hanging Otsu 2 early
3. (b) Details of vector timer differentiation key 42 and +'CL2>
3 Z (7 no 2)

Claims (3)

[Claims] (1) Consists of at least a plurality of scalar units (20, 21) that process scalar instructions, and a vector unit (1) that processes vector instructions sent from these scalar units (20, 21). In the multiprocessor system, the vector unit (1) includes an instruction switching control circuit (123) that changes the right to use the vector unit (1) given to one of the plurality of scalar units (20, 21). ), and a vector timer (121, 122) for each scalar unit (20, 21) that counts the time that the processing of the vector instruction is kept waiting because the right to use the vector unit (1) is not granted. ), and due to the time countover (1230, 1231) in each of the vector timers (121, 122), the vector is stored in the scalar unit (20, 21) corresponding to the vector timer (121, 122). A multiprocessor instruction control method characterized by granting usage rights to a unit (1). (2) As the vector timer (121, 122),
A signal (VIW) indicating that the above vector instruction is waiting for startup.
2. The multiprocessor instruction control system according to claim 1, wherein the counting of the waiting time is interrupted when VIW_1) becomes "0". (3) When a change is detected in a specific bit of the vector timer (121, 122), a specific latch (123
b_0 or 123b_1), and the latch (1
23b_0 or 123b_1) is set, only when a change is detected in the above specific bit again.
The multiprocessor instruction control system according to claim 1, characterized in that the multiprocessor instruction control system is configured to perform the count over (1230 or 1231).