JPS62214348A - Smoothing circuit for sampling data - Google Patents

Abstract

PURPOSE:To increase a sampling frequency and obtain smoothing data effectively by subtracting daily data and adding new data at every sampling period, and moving and adding a specific addition number of sampling data. CONSTITUTION:The output value of an adding circuit 4 to which sampling data are inputted successively; is held in registers 5 and 12 and outputted to a CPU and the circuit 4 respectively. A memory 8 is stored with a specific addition number of sampling data and a multiplexer 3 switches and supplies sampling data to be added and readout data of the memory 8 to be subtracted to the circuit 4. Further, a multiplexer 10 switches complements, the data read out of the memory 8 is inverted and supplied to the circuit 4, and a complement is supplied when the data is subtracted. A controller 9 generates a readout address of the memory 8 and also controls input and output data of the circuit 4. Then the circuit 4 subtracts the old data and adds the new data at every sampling period, and moves and adds a specific addition number of sampling data, thereby outputting smoothing data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sampling data smoothing circuit that adds a predetermined number of points to sampling data.

[Conventional technology]

FIG. 5 is a diagram showing an example of the configuration of a mass spectrometer, in which 11 is an ion source, 12 is an electric field, 13 is a magnetic field, 14 is a collector,
15 is an acceleration power source, 16 is an electric field power source, 17 is a magnetic field power source, 1
8 is a preamplifier, 19 and 20 are DACs, 121 is an ADC,
22 is a display, 23 is a data processing unit (CPU)
, 24 indicate memory.

In FIG. 5, DACs (digital/analog converters) 19 and 20 convert digital signals into analog signals in accordance with control commands from a data processing device 23 to power each power source of an acceleration power source 15, an electric field power source 16, and a magnetic field power source 17. It is something to control. The ADC (analog/digital converter) 21 converts the mass peak signal detected by the collector 14 from an analog signal to a digital signal in order to send it to the data processing device 23 . The data processing device 23 controls the acceleration power source 15, the electric field power source 16, and the magnetic field power source 17 through the DACs 19 and 20 to set the source of the analysis system % to be measured and sweep the magnetic field strength.

Then, the mass peak signal detected by the collector 14 is taken in through the preamplifier 18 and the ADC 21 and subjected to predetermined processing, and the data is stored in the memo I 74 and further displayed on the display 22.

In the data processing system of a mass spectrometer configured as described above, the A
/D conversion, the data processing device performs comparison judgment with the Surenshirodo level using software, and further integrates the sampling data to obtain the area value within the peak.
It performs peak determination and other processing by calculating the center of gravity and determining valleys between peaks.

[Problem that the invention seeks to solve]

In the data processing system of a conventional mass spectrometer configured as described above, the sampling data of the ADC is processed one point at a time, so the sampling period depends on the processing capacity of the data processing device and exceeds this processing capacity. The sampling period cannot be shortened, so the number of sampling points within one peak is limited, and the area value within one peak becomes low, resulting in poor peak determination sensitivity.

In addition, noise is a problem in mass peak processing, and the means to reduce noise is often by using analog filters. However, analog filters change the frequency characteristics by switching elements such as capacitors and resistors, so the frequency The number of parts for setting increases. Further, smoothing processing may be performed by software in a data processing unit (CPU), but in this case, it becomes impossible to increase the acquisition sampling frequency of the mass peak. In particular, when software processing is used, there is a problem in that it is difficult to increase the processing speed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a sampling data smoothing circuit that can increase the number of sampling cycles and effectively smooth sampled data.

[Means for solving problems]

Therefore, the sampling data smoothing circuit of the present invention includes an adding means to which sampling data is sequentially inputted from an ADC, a data holding means for holding the output value of the adding means and supplying the held data to the adding means as an added value, and a predetermined storage means for storing sampling data of added points;
a data selection-f stage for switching between sampling data to be added and read data from the storage means to be subtracted and supplying the data to the adding means; an output means for outputting smoothing data;
and a control means that generates a read address of the storage means and controls the input/output data of the addition means, and subtracts old data and adds new data every sampling period to move and add the sampled data of a predetermined number of addition points. death,
This is characterized in that it is output as smoothing data.

[Effect]

In the sampling data smoothing circuit of the present invention,
The sampling data of a predetermined number of addition points is stored in the storage means, and the selection means switches between the old data and the new sampling data stored here and supplies the selected data to the addition means, so that the data can be added every sampling period. The old data is subtracted by the adding means, and then new sampling data is added to obtain smoothing data with a predetermined number of addition points. Therefore, high-speed processing is possible, and since smoothing data obtained by adding sampling data of a predetermined number of points is obtained for each sampling period, peaks can be detected with high accuracy.

〔Example〕

Examples will be described below with reference to the drawings.

Fig. 1 is a diagram showing the configuration of one embodiment of the sampling data smoothing circuit according to the present invention, Fig. 2 is a time chart for explaining the operation of the circuit shown in Fig. 1, and Fig. 3 is an output by smoothing processing. FIG. 4 is a diagram for explaining the read/write address of the memory when the number of additions is set to four.

The sampling data smoothing circuit of the present invention smoothes sampling data by adding a predetermined number of points. Smoothing here means adding sampling data using an unweighted moving addition method. For example, the result of smoothing using the number of smoothing points m for the n-th data is Σ D, -2. Therefore, m- 4, as shown in Figure 3, I), -3+D11-2 "Da-1+[], =Σ
It becomes D-E2. To achieve this, it is necessary to memorize the previous data and perform additions and subtractions. Therefore, in the sampling data smoothing circuit according to the present invention, data equal to the number of smoothing points (D=4 to D,
-1) in memory and accumulates (ΣDn-*iP
4-1), and when inputting the next new data, first the old data D n that deviates from the point number due to movement
-4 is read from the memory and the cumulative value (ΣDa-t i
p=3 to 1), and then new data D7 is stored in the memory and the data is added to the cumulative value. The cumulative value after this addition (ΣDa-pif""3 to O) becomes the smoothing result at the new sampling point.

Next, the present invention shown in FIG. 1 will be explained in detail.

In FIG. 1, l is an ADC, 2, 5, 7, and 11 are registers, 3 and 10 are multiplexers, 4 is an addition circuit, 6 is a counter, 8 is a memory, and 9 is a controller.
DCI, for example? The analog data sent from the j1 analyzer is converted into digital data using a start pulse.

The register 2 holds the AD (analog-digital) conversion output from the ADC 1. The memory 8 stores data on the number of smoothing points. Register 7 is a smoothing point register, and the number of smoothing points is set here. The counter 6 generates a write/read address for data stored in the memory 8 according to the number of smoothing points set in the register 7. The multiplexer 3 switches between the data held in the register 2 and the data read from the memory 8 and supplies the data to the adder circuit 4 . The multiplexer 10 performs complement switching, inverts the data read from the memory 8, supplies the inverted data to the adder circuit 4, and supplies the complement when subtracting. Registers 5 and 12 hold the output value of the adder circuit 4, and the data held in register 5 is sent to the data processing device (CP
The data held in the register 12 is output to the adder circuit 4. Therefore, when the addition value of the data of the number of smoothing points is held in the register 12, the adder circuit 4 uses the inverted value of the old data read from the memory 8 and obtained through the multiplexer 3, and the complement obtained through the multiplexer IO. The old data is subtracted by adding it to the data in the register 12. When this data is held in the register 12, new data in the register 2 obtained through the multiplexer 3 is added to the data in the register 12 to obtain smoothing data.

Next, the overall operation will be explained using the time chart shown in FIG. Note that here, the number of adder circuits is 4, and the A
It is assumed that the D conversion process has been completed. The register 2 holds data Dn, the memory 8 stores data D11-3 to D11-3 as shown in FIG. 4, and the register 12 stores the cumulative value ( ΣD++-+s: p=3~l
), that is, the cumulative value (ΣD,, -p; which is the smoothing data at the previous sampling point).
The value obtained by subtracting the old data D, .
) is in the addition mode that outputs (1) At time T1, the controller 9 sends a set pulse to the registers 5 and 12, and smoothing data (ΣD-p if' = 3 to 0) is retained.

(2) At time T2, when the conversion start pulse ST is input manually, ADCl raises the signal EOC and outputs the sampling data D0. ．． Start the conversion process.

(3) At time T, when ADCl finishes the AD conversion process, it lowers the signal EOC. Due to this fall, the sampling data D n +
1 is held, and the counter 6 is shifted to count 11" data D1-3 as shown in FIG. 4 (al).
, the memory 8 goes into read mode, multiplexer 3 and 1ofJ<subtraction mode. That is, the multiplexer 3 outputs the old data D1-1 in the memory 8.
The inverted data of is selected, and the complement "1" is selected by the multiplexer 10. Therefore, the data (ΣDa-pip
=2 to 0) is output.

As is well known, for example, the complement is the subtraction of r5-3J (0101-0011 in binary notation) and the inverted data rllo.
Addition processing of OJ and complement "1" 1100...inversion +) l...It is used for calculation by complement.

(4) At time Vt T 4, when the set pulse of the register 12 is sent from the controller 9, the adder circuit 4
The output data (ΣDn-p;l)"2 to 0) is held in the register 12.

(5) At time T, the subtraction mode is switched to the addition mode, and the memory 8 is also switched to the write mode. As a result, in multiplexer 3, data D in register 2,
1.1, the multiplexer IO selects the complement rOJ, and the adder circuit 4 selects the data DR+1 of the register 2.
and the data of register I2 (ΣDh-p; p=2~O) are added, and new smoothing data (ΣD, , -p
il)=2 to -1) is obtained. At the same time, data D I,+1 of the register 2 is written to the specified address A3 of the memory 8 as shown in FIG. 4, 1bl.

(6) At time T, a set pulse is sent from the controller 9 to the registers 5 and 12,
Smoothing data (ΣD-p; p-2 to -1) is held.

At time T, the same process as that at time T2 described in (2) above is performed, and the same process is repeated thereafter. In this case, the addresses generated by the counter 6 circulate from A3→A2→Al-AO and back to A3 as shown in FIG.

Note that the present invention can be modified in various ways and is not limited to the above embodiments.

(Effects of the Invention) As is clear from the above description, according to the present invention, smoothing data obtained by adding a predetermined number of points to the sampling data for each sampling period is obtained, so smoothing can be performed in real time without delaying the AD sampling period. It can be carried out.

Therefore, it is possible to detect the peak position of a noisy peak with high accuracy. Furthermore, since the processing is performed not by software but by a logic circuit using memory and addition means, high-speed processing can be performed.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the configuration of one embodiment of the sampling data smoothing circuit according to the present invention, Fig. 2 is a time chart for explaining the operation of the circuit shown in Fig. 1, and Fig. 3 is an output by smoothing processing. Figure 4 is a diagram to explain the memory read/write address when the number of additions is set to 4. Figure 5 is an example of the configuration of a quantity analyzer. FIG. 1...ADC, 2, 5, 7 and 11...Register, 3
and 10...multiplexer, 4...addition circuit, 6...
...Counter, 8...Memory, 9...Controller. "l)-, II":)) Figure 2 ■Register 2n Dn+l
rl+2■nu(pug (')R/N -hi
Read - To Read Light D5 ■Memo °) 'il 'f-5・-,,7
Figure 3 Figure 5

Claims (4)

[Claims] (1) Addition means into which sampling data is sequentially input;
Data holding means for holding the output value of the adding means and supplying the held data to the adding means as an addition value, a storage means for storing sampling data of a predetermined number of addition points, and read data from the storage means for subtracting the sampling data to be added. and a data selection means for supplying smoothing data to the addition means, an output means for outputting smoothing data, and a control means for generating a read address of the storage means and controlling input/output data of the addition means. A sampling data smoothing circuit characterized in that the circuit subtracts data and adds new data to move and add sampling data of a predetermined number of addition points, and outputs the result as smoothing data. (2) The sampling data smoothing circuit according to claim 1, wherein the old data is read from the storage means, and after being supplied to the addition means as subtracted data, the new sampling data is stored in the storage means. (3) When added data obtained by adding sampling data of a predetermined number of addition points is held in the data holding means, read old data in the storage means from the added data and subtract it, and store the subtracted data in the data holding means. 3. The sampling data smoothing circuit according to claim 1, wherein new sampling data is added after the data is held. (4) The sampling data smoothing circuit according to any one of claims 1 to 3, characterized in that the inverted data and complement of the data read from the storage means are supplied to the addition means as subtraction data.