RU1781625C - Device for measurement of rms value of signal - Google Patents

Abstract

The invention relates to electrical measurements and allows high-precision measurements in a wide frequency range of variable arbitrary waveforms. SUMMARY OF THE INVENTION: high measurement accuracy is achieved by eliminating the frequency component of the error, which is achieved by changing the spectrum of the input signal, resulting in a measurement of the input signal in a narrow fixed frequency range. 7 ill.

Description

The invention relates to electrical measurements and can be used in the construction of high-precision measuring instruments,

A device for measuring the rms value of a signal is known. It consists of a control device, an electronic switch, a pulse generator, a compensating voltage source, a pulse counter, a decoder, a recording device, a zero-element, a controlled divider and a programming unit. In this device, the alternating input voltage is first converted to constant and then measured. An average value converter has been used to convert the AC voltage to DC.

The constant voltage is measured as follows. When a start pulse is received from the control device, an electronic key is opened and the pulse generator signals are sent to the source of the compensating voltage, which are simultaneously recorded by the pulse counter. The compensating voltage source generates a compensating voltage Ux, which changes to Dichs by the arrival of each pulse from the pulse generator. The measurement process is reduced to counting the number of pulses by the counter that passed through the electronic switch in a certain time. When a null-organ is triggered, when their input voltage converted to a constant AC input to the null-organ via a controlled divider becomes equal to the compensating voltage Ux, the key closes, AUx generation and pulse counting cease, the pulse counter after decryption is transmitted to the recording device.

A disadvantage of this RMS signal measuring device is the low accuracy of the measurement. This is due to the fact that the AC / DC converter used in the device is not designed to convert arbitrary waveforms.

Of the known devices for measuring the rms values of a signal, the closest to the technical nature of the device is a device for measuring rms values of a signal. It consists of a shaper of the measured signal, a shaper of zero-crossing pulses, a pulse generator, a frequency divider, a counter, registers, a recording interval shaper, triggers, an address counter, analog-to-digital and digital-to-analog converters, groups of AND elements, elements AND, groups of elements AND -OR, memory units, RMS driver, read signal driver, recording unit, and control driver.

The measurement of the rms value of the signal is as follows. The alternating signal The accelerator of the measured signal is fed to the pulse shaper of the transition through zero and the analog-to-digital converter. Based on the signals of the pulse generator of the transition through zero, the driver of the control signals generates signals that synchronize the operation of the entire device.

Using a pulse generator, a frequency divider, a counter, a decoder, a register and a recording interval generator, the triggering signals of the analog-to-digital converter are generated. The trigger frequency of the latter determines the number of samples of the instantaneous values of the input signal for the observation interval. The maximum number of samples in a given observation interval depends on a given measurement accuracy.

The information converted by an analog-to-digital converter is fed alternately to two memory blocks through a group of AND-OR elements at the addresses formed by the address counter. At the same time, the information received in the previous clock cycle is read from the memory blocks. The information being read is received and the register. Discrete information, storage - with a register, is converted by a digital-to-analog converter into an alternating signal. This signal after the RMS converter and amplifier is fed to the registration unit.

The disadvantage of this device for measuring the rms value of the signal is its low accuracy of measurement (1-2)% over a wide frequency range. This is due to the fact that when operating in the high-frequency region, the level of the input signal changes during the measurement time more than the allowable value. Therefore, the bit analog-to-digital converter does not have time to encode the current sample value with a bit code, i.e. Provide a predetermined measurement accuracy.

The aim of the invention is to improve the accuracy of measuring the rms signal.

The goal is achieved in that

to a device for measuring the rms value of the signal; containing a shaper of the measured signal connected by the input to the input scale, the shaper of the root mean square

values, the output of which is connected through an amplifier to the input of the registration unit, the first register and decoder, connected by inputs to the first and second outputs of the control signal generator, a counter connected to the zero input and the resolution input, respectively, with the third and fourth outputs of the control signal generator, the second register connected

the control input to the fifth output of the driver of the control signals, the first and second elements And connected by the first inputs to the sixth output of the driver of the control signals,

an analog-to-digital converter connected by a triggering input to the seventh output of the control signal generator, an address counter connected by a zero INPUT with an EIGHT FORMIRO OUTPUT;

control signal driver, a trigger connected by a counting input to the ninth output of the control signal generator, a recording interval shaper connected to the tenth output and the first input of the control signal generator respectively, the zero-pulse shaper connected between the output of the driver of the measured signal and the second input of the driver of the control signals, the digital-to-analog converter connected by the output to the input of the driver of the rms value and, chysoani signal generator, third register, third and fourth

AND elements, first, second, third, fourth and fifth groups of AND-OR elements, first and second groups of AND elements, first and second memory units, frequency divider, pulse generator and OR element, wherein the control signal generator is connected to the seventh output to the counting input of the address counter connected by the outputs to the first groups of inputs of the first and second groups of AND-OR elements, the output of the frequency divider is connected to the first input of the read signal generator, which is connected by the first, second and third outputs to the input of the third reg and to the read inputs of the first and second memory units, connected by the fourth and fifth outputs to the first and second inputs of the first group of AND-OR elements, connected by the sixth and seventh outputs to the first and second inputs of the second group of AND-OR devices, connected by the eighth and the ninth outputs with the first and second inputs of the third group of AND-OR elements and is connected by the second input to the first output of the trigger connected to the output of the first group of AND elements and with the second input of the first AND element connected by the output to the recording input of the first memory block the first is connected by address inputs to the outputs of the first group of AND-OR elements and connected by information inputs to the outputs of the first group of AND elements, the outputs of the second group of AND elements are connected to the information inputs of the second memory unit, which is connected by address inputs to the outputs of the second group of AND-OR elements and connected to the recording input to the output of the second element And, connected by the second input to the second output of the trigger, connected to the input of the second group of elements And, the input of the digital-to-analog converter is connected to the output of the third register connected by information inputs to the outputs of the third group of AND-OR elements, connected by the first and second groups of inputs to the outputs of the first and second memory blocks, respectively, and the output of the measured signal shaper is connected to the measuring input of the analog-to-digital converter connected by the clock input to the second output of the frequency divider, which is connected by the input to the output of the pulse generator, is connected by the third output to the counting input of the counter and connected by a group of outputs to the first group of inputs s shaper recording interval, the second group connected to the outputs of the first input register connected to the outputs of a group of inputs of the decoder, a group of inputs which

connected to the outputs of the counter, a third memory unit is additionally introduced, connected by address inputs to the outputs of the first group of AND-OR elements and connected by a read input to the output of an OR element connected by the first input to the tenth output of the read signal generator and connected by the second input to the output third element And first

0 the input of which is connected to the eleventh output of the driver of control signals connected to the first input of the fourth element And connected by the second input to the first output of the trigger,

5 connected to the first input of the fourth group of AND-OR elements, connected by outputs to the information inputs of the second register and connected by the second input to the second output of the trigger, connected to the second input of the third AND element, the fourth memory block, connected by the outputs to the inputs of the fourth group of AND elements -OR and to the inputs of the fifth group of AND-OR elements, connected by outputs 5 to another group of inputs of the third register and connected by the first and second inputs to the eleventh and twelfth outputs of the signal driver with ityvani, fifth and sixth AND gates,

0 connected by the first inputs with the twelfth output of the driver of the control signals, the third and fourth groups of elements And, connected by groups of inputs to the outputs of the analog-digital

5 converter, an additional analog-to-digital converter connected by a clock input to the second output of the frequency divider, connected by a trigger input to the seventh output of the control signal generator and connected by outputs to the input groups of the first and second groups of elements I. an additional OR element, connected by the first and the second inputs to the output of the fourth element And and to the thirteenth output of the driver of the read signals, an additional digital-to-analog converter connected by inputs to the outputs a second register, subtractor, podsoe0 union of the first input to the output of the formation rovatel measured signal. read address generator connected to the first output of the frequency divider by the first and second inputs

5 to the thirteenth output of the driver-control signal, connected by a group of inputs to the outputs of the address counter and connected by outputs to other groups of inputs of the first and second groups of AND-OR elements, the first output of the trigger being connected to the input of the third group of AND elements and to the second input of the fifth element And, connected by the output to the recording input of the third memory block, connected by information inputs to the outputs of the third corpus of AND elements, the second trigger output is connected to the input of the quarters of the group of And elements and to the second input of the sixth AND element, connected by the output to the recording input of the fourth memory block, which is connected by information inputs to the outputs of the fourth group of AND elements, the output of the additional digital-to-analog converter is connected to the second input of the subtraction unit, connected by the output to the signal input of the additional analog-to-digital converter, the outputs of the third block the memory is connected to other input groups of the fourth and fifth groups of AND-OR elements, and the output of the additional OR element is connected to the read input of the fourth rtogo memory block.

The increase in the accuracy of measuring the rms values of variable signals by an order of magnitude compared with the prototype is due to the phased encoding of the input signal. In the i period of the input signal, the high order bits are encoded, and in 0 + 1) the period is the low order bits of the input signal. In the (1 + 1) period, a difference signal is encoded, obtained by subtracting the converted signal from the input signal after digital-to-analog conversion of the high-order code of the i period.

To encode the least significant bits in the (i + 1) period of the input signal, two memory blocks, two groups of AND-IL elements, two groups of AND elements, digital-to-analog, analog-to-digital converters, a register, and a subtraction block are introduced.

The control signals necessary for coding low-order bits are generated by the control signal generator, the read signal generator, AND elements and OR elements,

Eeyore FIG. 1 is a block diagram of an apparatus for measuring the rms value of a signal; in FIG. 2 - time diagrams of the operation of the driver of control signals; in FIG. 3 is a block diagram of a read signal driver; in FIG. 4 is a timing diagram of a read signal driver; in FIG. 5 is a block diagram of a driver of control signals; in FIG. 6 is a block diagram of a recording interval shaper; in FIG. 7 is a block diagram of a read address generator.

The proposed device for measuring the rms value of the signal consists of a shaper of the measured signal 1, a pulse shaper through zero 2, a pulse generator 3, a frequency divider 4, a counter 5, a decoder 6, a register 7, a shaper of the recording interval 8, a trigger 9, an address counter 10 , analog-to-digital converter 11, groups of elements AND 12, 13, elements AND 14, 15, memory blocks 16, 17, group of elements AND-OR 18, register 19, digital-to-analog converter 20, shaper of mean-square values 21, block p wizard 22, AND-OR element groups 23, 24, read signal shaper 25, read address shaper 26, control signal shaper 27, divider 28, AND-OR 29 element groups, register 30, digital-to-analog converter 31, subtractor 32, analog a digital-to-digital converter 33, memory units 34, 35, AND-OR 36 element groups, AND 37, 38 element groups, AND 39, 40, 41, 42 elements and OR 43,44 elements.

The read signal generator 25 has two inputs 45.46 and thirteen outputs 47-59, The control signal generator 27 has two inputs 60-61 and thirteen outputs 62-74.

The read signal generator 28 (Fig. 3) consists of a frequency divider 75, an AND element 76, a delay element 77, an HE element 78, an AND elements 79, 80, elements NOT 81.82. In FIG. Figure 4 shows the timing diagrams of the operation of the read signal driver 25.

The control signal generator 27 (Fig. 5) consists of a counter 83, which includes a trigger 84.85.86.87, an element 88 and a decoder 89, which includes a shaper of duration 90, elements AND 91-95, element OR 96, formers of duration 97 -99, OR element 100, AND element 101, shaper of duration 102, AND elements 103, 104, OR element 105 and delay element 106. In FIG. 2 shows timing diagrams of the operation of the driver of control signals 27.

Shaper recording interval 8 (Fig.6) consists of elements And 109-112 and element OR 113,

The read address generator 26 (FIG. 7) consists of a register 114, a group of AND elements 115, a delay element 116, reversible counters 117,118, a trigger 119, AND elements 120, 121, an OR element 122, an AND-OR 123 element group, and a delay element 124 .

The input of the device is connected to the input of the driver of the measured signal 1. The output of the driver of the measured signal 1

connected to the input of the pulse generator of the transition through zero 2, the measuring input of the analog-to-digital converter 11 and the first input of the subtracting unit 32. The output of the pulse generator of the transition through zero 2 is connected to the first input 61 of the driver of the control signals 27. The output of the pulse generator 3 is connected to the input of the divider 4. The first output of the frequency divider 4 is connected to the counting input of the counter 5. The second output of the frequency divider 4 is connected to the first 46 input of the read signal generator 25 and the first input of the address generator readings 26. The third output of the frequency divider 4 is connected to the clock input of the analog-to-digital converter 11 and the clock input of the analog-to-digital converter 33. The fourth outputs of the frequency divider 4 are connected to the first inputs of the recording interval 8. The zero input of the counter 5 is connected to the first output of the controller 27 signals, the second output of which is connected to the enable input of the counter 5. The outputs of the counter 5 are connected to the first inputs of the decoder 6, the second input of which is connected to the third 73 output of the generator control signals 27. The outputs of the decoder 6 are connected to the inputs of the register 7, the outputs of which are connected to the second inputs of the shaper recording interval 8, the second input of which is connected to the fourth 69 output of the shaper control signals 27. The output of the shaper recording 8 is connected to the second 60 input of the shaper control signals 27. The second input of the register 7 is connected to the fifth 72 output of the driver of control signals 27.

The counting input of trigger 9 is connected to the sixth 64 output of the driver 27 of the control signal. The first output of trigger 9 is connected to the first input of the group of elements I-IL1L 29, with the first inputs of the groups of elements And 12, 37 and the first inputs of elements And 15, 39, 40. The second output of trigger 9 is connected to the second input of the group of AND-OR elements 29, with the first inputs of the groups of elements AND 13, 38, the first inputs of the elements AND 14, 41, 42 and the second 45 input of the read signal generator 25.

The zero input of the address counter 10 is connected to the seventh 68 output of the control signal generator 27. The counting input of the address counter 10 is connected to the eighth 62 output of the control signal generator 27, which triggers the input of the analog-to-digital converter 11 and the trigger input of the analog-to-digital

converter 33. The outputs of the analog-to-digital converter 11 are connected to the second inputs of the groups of elements And 12, 13. The outputs of the groups of elements And 12 are connected to

information inputs of the block 16. The outputs of the groups of elements And 13 are connected to the information inputs of the block 17. The second inputs of the elements 14, 15 are connected to the ninth 65th output of the driver 27 of the control signals. The output of the element 14 is connected to the recording input of the block memory 17. The output of the AND element 15 is connected to the recording input of the memory unit 16. The address inputs of the memory unit 16 are connected to the outputs of the group of AND-OR elements 24 and the address inputs of the memory unit 34. The address inputs of the memory unit 17 are connected to the outputs group of AND-OR elements 23 and address inputs and a memory unit 35. Log x ti

The read 0 of the memory unit 16 is connected to the output of the OR element 43. The read input of the memory unit 17 is connected to the output of the OR element 44. The outputs of the memory unit 16 are connected to the first inputs of the group of 5 AND-OR elements 18 and the third inputs of the group of AND-OR elements 29, the fourth inputs of which are connected to the outputs of the memory unit 17 and the second inputs of the groups of AND-OR elements 18.

0 The third input of the groups of AND-OR elements 18 is connected to the first 51 output of the read signal generator 25, the second 52 input of which is connected to the fourth input of the group of AND-OR elements 18. The outputs of the group of OR-OR elements 18 are connected to the first information inputs of the register 19, the control input of which is connected to the third 59 output of the read signal generator 25.

0 The outputs of the register 19 are connected to the information inputs of the digital-to-analog converter 20, the output of which through the RMS 21 generator and the amplifier 28 is connected to

5 by the registration unit 22.

The first input of the group of AND-OR elements 23 is connected to the fourth 49 output of the read signal generator 25, the fifth 50 output of which is connected to the second input of the group of AND-OR elements 23. The third (/ the inputs of the group of AND-OR 23 elements are connected to the third inputs of the group elements / AND-OR 24, the address inputs of the shapers read address 26 and the outputs of the counter 5 address 10. The fourth inputs of the group of elements AND-ULI 23 are connected to the fourth inputs of the group of elements AND-OR 24 and the outputs of the shaper read address 26. The first input of the group elements AND- OR 24 with of the connections 47 to the sixth output

iJ OpMUfiOfVHRJiH SIGNAL.ME) S, CHIPLM I 25,

with a blueprint 4B the output of the second city of the second year is from the j / icMfUiTon group AND- OR 24.

The eighth 54 output of the read signal generator 25 is connected to the first input of the OR element 44. The ninth 55 output of the read signal generator 25 is connected to the read input of the memory unit 35. The tenth 56 output of the read signal generator 25 is connected to the first input of the AND-OR 35 element group the second input of which is connected to the eleventh 57 output of the read signal generator 25. The twelfth 58 output of the read signal generator 25 is connected to the read input of the memory unit 34. The thirteenth 53 output of the read signal generator 25 is connected to the first input of the OR circuit 43.

The tenth 71 output of the driver of the control signals 27 is connected to the recording input of the driver of the read address 26. The eleventh 66 output of the driver of the signals 27 is connected to the first inputs of the elements 39. 42. The twelfth 67 output of the driver of the control signals 27 is connected to the first inputs of the elements AND 40, 41. The thirteenth 63 output of the driver of control signals 27 is connected to the control input of the register 30.

The outputs of the groups of AND-OR elements 29 are connected to the information inputs of the register 30. The information outputs of the register 30 are connected to. the inputs of the digital-to-tax converter 31. The output of the digital-to-analog converter 31 is connected to the second input of the subtraction unit 32, the output of which is connected to the measuring input of the analog-to-digital converter 33.

The outputs of the analog-to-digital Converter 33 are connected to the second inputs of the groups of elements And 37, 38.

Information inputs of the memory unit

34 are connected to the outputs of the AND group of circuits 37. The recording input of the memory unit 34 is connected to the output of the AND 40 element. The outputs of the memory unit 34 are connected to the third inputs of the AND-OR 36 element group, the fourth inputs of which are connected to the outputs of the memory unit 35. Information inputs the memory unit 35 is connected to the outputs of the group of elements And 38. The input entry of the memory unit

35 connected to the output of the element And 41.

The output of AND element 39 is connected to the second input of OR element 44. The output of AND element 42 is connected to the second nxorn-f of OR element 43. IPV outputs

Comrade AND-OR 36 connected to the second information inputs of the register 19.

The operation of the device for measuring the mean square value of the signal is as follows.

The variable signal Ux from the shaper of the measured signal 1 is supplied to the pulse shaper of the transition through zero 2 and the measuring input of analog-digital

0 Converter 11. According to the input signals of the pulse shaper of the transition through zero 2, arriving at 61 input, the shaper of control signals 27 generates signals that synchronize the work

5 total devices. The temporal positions of the signals of the driver 27 of the control signals are shown in FIG. 2.

Using a pulse generator 3, frequency divider 4, counter 5, decoder

0 6, register 7, and recording interval generator 8, triggering signals of the analog-to-digital converter 11 are generated.

Counter 5 counts the number of pulses that are generated by the generator

5 pulses 3 and a frequency divider 4 for one period of the input signal. To do this, the counter 5 is set to zero state by the signal coming from the output 70 of the driver of control signals and

0 counts the pulses arriving at it during a single input voltage period. Permission for the passage of pulses to the counter 5 comes from the output 74 of the shaper control signals 27. Indications

5 of the counter 5 are analyzed by the decoder 6 and, if there is a control signal at the output 73 of the driver of the control signal 27, the decoder 6 provides a signal to the register 7, which is stored in it.

0 Shaper of the recording interval 8 according to the state of the register 7 and the signals of the frequency divider 4 corresponding to these states generates signals of a certain frequency, which are input 60

5 control signal generator 27. Based on these signals, the control signal generator 27 generates triggering signals of the analog-to-digital converter 11 and the analog-to-digital converter

0 33, which, from the output 62 of the driver of control signals 27, are supplied to start analog-to-digital converters 11, 33.

The information converted by analog-to-digital converter 11 (high order bits of the code) into the i-period of the input signal, is sequentially fed to memory blocks 16, 17. Separation of this information gg, o / .; d / tc trigger 9, control

: f. c.

which is connected to its counting input from the output 64 of the shaper of control signals 27.

The control signal from the first output of trigger 9 allows information to pass from the output of the analog-to-digital converter 11 through a group of elements 12 to the information input of the memory unit 16. Information does not come from the output of the analog-to-digital converter 11 to the information input of the memory block 17, since a group of elements And 13 receives the inhibitory potential from the second output of trigger 9.

At the same time, the address counter 10 code arrives at the address input of the memory unit 1, which generates the recording address by counting the start signals of the analog-to-digital converter 11. The write address code generated by the address counter 10, through the group of AND-OR 24 elements goes to the address the input of the memory unit 16. Information is recorded in the memory unit 16 by the signal from the 65 output of the control signal generator 27. which passes through the AND element 15 to the recording input of the memory unit 16.

At this time, information (high and low order codes) coming from them in the previous clock cycle is read from memory blocks 17, 35. The read address generator 26 from the write address generated by the address counter 10 generates an address for continuously reading information (high and low bits) from the memory blocks 17, 35 necessary to restore the variable input signal. The read address generated by the read address generator 26 is fed to the address inputs of the memory blocks 17.35 through the group of AND-OR 23 elements. The read signal from the output of the OR element 44, which receives the control signal from the 54 output of the read signal generator 25, from the memory unit 17 through the group of elements AND-OR 18 receives information on the first inputs of the register 19. At this time the passage of signals through the group of AND-OR elements 18, 23 is controlled by the signals from 50, 51 outputs of the read signal generator 25. To the second information inputs of the register 19, the signal at 59 the output of the read signal generator 25 through the group of AND-OR elements 36 t information from the memory unit 35, the enable signal on the passage of information through a group of AND-OR elements 36, 57 is output from the read signal shaper 25. Recording information in the register 19 is produced control signal,

coming from the 59 output of the read signal driver 25. After restoring the variable input signal, the digital-to-analog converter 20

this signal is converted by the rms converter 21 and the measurement results are displayed by the recording unit 22.

In the subsequent (1 + 1) input period

At 0 voltage, the signal generated by the subtractor 32 and the digital-to-analog converter 31 is encoded. The input signal Ux is received at one input of the subtractor 32 after the measured signal adjuster 1 is formed. The restored analog signal encoded by the analogue signal is received at the second input of the subtractor 32. a digital Converter 11 in the I period of the input signal.

0 V (i + 1) period of the input signal, the information stored in the memory unit 16 is read out according to the signals received through the OR element 43 from the AND element 42 at the time of the signal

5 with 66 output of the driver of control signals 27.

This information, having passed through the group of AND-OR elements 29, is stored in register 30, and then fed to a digital-to-analog converter 31, where it is converted into an analog signal supplied to the second input of subtraction unit 32. Difference signal Di Uex-dcd (where UBX - input signal, UCAP restored 5 input signal) is fed to the analog-to-digital Converter 33.

According to the trigger signal coming from the 62 output of the driver 27 of the control signals, in an analog-to-digital converter:

0 leZZ, the output signal of the subtracting unit 32 is encoded.

The control signal from the first output of trigger 9 allows the passage of code information from the output of analog-digital

5 of the converter 33 through the group of elements AND 37 to the information input of the memory unit 34. The information input of the memory block 35 does not receive code information from the output of the analog-to-digital converter 33, since the inhibiting potential from the second output of the trigger 9 arrives at the group of elements AND 38 .

At this time, the address code from the counter ad5 of address 10 arrives at the address input of the memory unit 34, which generates the recording address by counting the start signals of the analog-to-digital converter 33. The write address code generated by the address counter through the group of AND-OR 24 elements is transmitted to address input of the memory unit 34. Information is recorded in the memory unit 34 by the signal from the output 67 of the driver 27 of the control signal, which passes through the AND element 40 to the recording input of the memory unit 34.

When a second pulse arrives at the counting input of the trigger 9 from the control signal generator 27, it changes its state. In this case, information is recorded in the memory block 17, and information is read from the memory blocks 16, 34. In this case, the information from the output of the analog-to-digital converter 11 through the group of elements 13 is fed to the information input of the memory block 17. since the resolving potential arrives at the second input of the group of elements And 13 from the second output of trigger 9. The address code generated by the address counter io passes through the group of elements AND-OR 23 neither the address input of the memory unit 17. Writing information to the memory unit 17 produced by si the signal coming from the 65th output of the driver of the control signals through the AND element 14 to the recording input of the memory unit 17,

At the same time, the information received in the previous cycle is read from the memory units 16, 34. The read address generated by the read address generator 25, through the group of AND-OR 24 elements, is supplied to the address input of the memory unit 16. According to the read signal coming from the output of the OR 43 element, the information from the memory block 13 through the group of AND-OR 18 elements arrives at the first information inputs of the register 19. The information from the memory unit 34 is supplied to the second information inputs of the register 19 by the read signal at 56 the output of the read signal generator 25 through the group of AND-OR 36 elements.

In the subsequent operation cycle of the device, the information stored in the memory unit 17 is read out according to the signals received through the OR element 44 from the And 39 element, at the time of receipt of the signals from the 66 output of the control signal generator 27. This information passed through the group of elements AND-OR 29 is stored in register 30 and then fed to a digital-to-analog converter 31, where it is converted into an analog signal fed to the second input of subtractor 32.

According to the trigger signal coming from the 62 output of the driver of the control signals27, in the analog-to-digital converter 33, the output signal of the subtracting unit 32 is encoded.

The control signal from the second output of trigger 9 allows information to pass from the output of the analog-to-digital converter 33 to the information input of the memory unit 35. To the information input of the memory unit 34, information from the output of the analog-to-digital converter 33 is not received, since the group of elements And 37 the inhibitory potential comes from the first output of trigger 9.

At this time, the address code from the address counter 10 arrives at the address input of the memory unit 35, which generates a recording address by counting the triggering signals of the analog-to-digital converter 33. The write address code generated by the address counter 10 passes through the group of AND-OR 33 elements to address input of the memory block 35. Information is recorded in the memory block 35 by the signal from the output 67 of the driver 27 of the control signals, which passes through the element 41 to the input of the recording of the memory block 35

The digital information stored in register 19 is converted by digital-to-analog converter 20 into an alternating signal. This signal after the RMS converter 21 and the divider 28 is fed to the registration unit 22.

The claimed object has technical advantages compared with the prototype, reducing by up to (0.1-0.2)% the measurement error in a wide frequency range. This is because the input signal is encoded in stages. In the i-period of the input voltage, the high order bits are encoded, and in the (1 + 1) period, the low order bits are encoded.

At the Institute of Electrodynamics of the Academy of Sciences of the Ukrainian SSR, a mock-up of a variable-voltage voltmeter was made, which implements the structure of the proposed device for measuring the rms signal value. ;

Technical documentation for the claimed i /. Acquisition is made at the level of outline drawings, allowing reproducing the proposed device for measuring the rms value of the signal.

Claims (1)

Shadow Formula Formula A device for measuring the rms value of the signal, comprising a shaper of the measured signal connected by an input to the input scale, a shaper of rms value, the output of which is connected through an amplifier to the input of the recording unit, a first register and a decoder connected by inputs to the first and second outputs of the control shaper, respectively signal counter connected to zero BUM input and enable input, respectively, with the third and fourth outputs of the driver control signal c, the second register connected to the control input to the fifth output of the control signal generator, the first and second elements And connected to the first inputs with the sixth output of the control signal generator, an analog-to-digital converter connected by the trigger input to the seventh output of the control signal generator , an address counter connected to the eighth output of the driver of the control signals by a zero input, a trigger, connected to the ninth output of the driver of the control signals, The recording interval specifier connected to the tenth outputs by the input and output, respectively, of the control signal driver, the zero-pulse shaper connected between the output of the measured signal driver and the second input of the control signal driver, and the digital-to-analog converter connected by the output to the input of the driver rms value, read signal generator, third register, third and fourth elements AND, first, second, third, fourth and fifth group py of the AND-OR elements, the first and second groups of AND elements, the first and second memory blocks, the frequency divider, the pulse generator and the OR element, and the control signal generator is connected by the seventh output to the counting input of the address counter connected by the outputs to the first groups of inputs of the first and the second group of AND-OR elements, the output of the frequency divider is connected to the first input of the read signal form, which is connected by the first, second and third outputs to the input of the third register and to the read inputs of the first and second memory blocks and, connected by the fourth and fifth outputs to the first and second inputs of the first group of AND-OR elements, connected by the sixth and seventh outputs to the first and second inputs of the second AND-OR elements, connected by the eighth and ninth outputs to the first and second inputs of the third group AND-OR and connected to a second input. 1 to the first trigger output connected to the output of the first group of AND elements and to the second input of the first AND element connected to the output of the recording input of the first memory block, which is connected by address inputs to the outputs | C, this group of AND-OR elements and connected. h with irrational entrances with exits the first group of AND elements, the outputs of the second group of AND elements are connected to the information inputs of the second memory block, which is connected by address inputs to the outputs of the second group of AND-OR elements and connected to the recording input to the output of the second AND element, connected by the second input to the second trigger output connected to the input of the second group of AND elements, the input of the digital-to-analog converter is connected to the output of the third register connected by information inputs to the outputs of the third group of the AND-OR element connected to the first 5 by the second group of inputs to, the outputs of the first and second memory blocks, respectively, and the output of the measured signal driver is connected to the measuring input of the analog-to-digital converter connected by the clock input to the second output of the frequency divider, which is connected by the input to the output of the pulse generator, connected to the third the output to the counting input of the counter and is connected by a group of outputs to the first group of inputs of the shaper of the recording interval, connected by the second group of inputs to the outputs of the first register connected by group of inputs with decoder outputs, the group of inputs of which 0 is connected to the outputs of the counter, characterized in that, in order to increase the accuracy of measurement, a third memory unit is added, connected by address inputs to the outputs of the first group 5 AND-OR elements and is connected by a read input to the output of an OR element connected by the first input to the tenth output of the read signal generator and connected by the second input to the output of the third AND element, the first input of which is connected to the eleventh output of the control signal generator connected to the first mu input of the fourth AND element, connected by the second input to the first output of the trigger, connected to the first input of the fourth group of AND-OR elements. connected by outputs to the information inputs of the second register and connected by the second input to the second output of the trigger connected to the second input of the third AND element, the fourth memory block connected by the outputs to the inputs of the fourth group of AND-OR elements and to the inputs of the fifth 5 groups of AND-OR elements, connected-outputs to another group of inputs of the third register and connected by the first and second inputs to the eleventh and twelfth outputs of the read signal generator, the fifth and sixth AND elements, connected by the first inputs to the twelfth output of the driver of the control signals, the third and fourth groups of elements And connected by groups of inputs to the outputs of the analog-to-digital converter, an additional analog-to-digital converter connected by the clock input to the second output of the divider, the frequency connected by the trigger input to the seventh output of the driver control signals and connected by the outputs to the input groups of the first and second groups of AND elements, an additional element 1 / 1L1L, connected by the first and W by the other inputs to the output of the fourth AND element and to the thirteenth output of the read signal generator, an additional digital-to-analog converter connected by inputs to the outputs of the second register, a subtraction unit connected by the first input to the output of the measured signal generator, a read address generator connected by the first and second inputs to the first the output of the frequency divider and the thirteenth output of the driver of the control signals connected by a group of inputs to the outputs of the address counter and the connected output Ami to other groups of inputs of the first and second groups of elements AND - INR. moreover, the first output of the trigger is connected to the input of the third group elements And and the second input of the fifth element And, connected by the output to the recording input of the third memory block, connected by information inputs to the outputs of the third group of elements And, the second trigger output is connected to the input of the fourth group of AND elements and to the second input of the sixth AND element, connected by the output to the recording input of the fourth memory unit, which is connected by information inputs to the outputs of the fourth group of AND elements, the output of the additional digital-to-analog converter is connected to the second input of the block of subtraction connected by the output to the signal input of an additional analog-to-digital converter, the outputs of the third memory block are connected to other input groups: inputs of the fourth and fifth groups elements AND-OR, and the output of an additional element OR is connected to a read input of a fourth memory unit. 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