SU1675789A1 - Device for measurement of characteristics of superconducting specimen - Google Patents

Abstract

The invention relates to a measurement technique and can be used to determine the characteristics of superconducting samples. The aim of the invention is to improve the accuracy and reduce the time for measuring the characteristics of superconducting samples. Device for measuring the characteristics of superconducting samples

Description

The invention relates to a measurement technique and can be used to determine the characteristics of superconducting samples.

The aim of the invention is to improve the accuracy and reduce the time for measuring the characteristics of superconducting samples.

FIG. 1 shows a functional diagram of the device; in fig. 2 shows time diagrams of the device operation in the measurement mode; in fig. 3 - functional block diagram of the measurement of the critical current; in fig. 4 - time diagrams of his work; in fig. 5 is a functional diagram of a random access memory.

The device (Fig. 1) contains a direct current driver 1, an alternating current driver 2, a solenoid current driver 3, a mixer 4, a cryostat 5 with a sample, a calibration signal driver 6, an amplifier 7 with a synchronous detector, an analog switch 8, element 9, analog-to-digital converter (ADC) 10, elements AND 1T, multiplexer 12, digital-to-digital converters (DAC) 13 and 14, random access memory (RAM) 15, one-shot 16, register 17, element OR 18, unit 19 for measuring the critical current , delay element 20, elements AND 21-25, lementy OR 26 and 27, RS-triggers 28-30, AND gates 31 and 32, the counter-divider 33 and 34, the oscillator 35 clock pulses, a current amplifier 36, an OR gate 37, AND gate 38.

The critical current measurement unit 19 (Fig. 3) contains comparators 39 and 40, shapers 41 and 42, element OR 43, RS-trigger 44, element AND 45, elements OR 46 and 47, RS-triggers 48 and 49, counting trigger 50 , RS-flip-flops 51 and 52, one-shot 53, elements AND 54-57, element OR 58, RS-trigger 59, counter 60, reversible counter 61, element AND 62 and shapers 63 and 64. RAM 15 (Fig. 5) contains reversible counters 65 and 66, shaper 67, elements And 68 and 69, RS-flip-flops 70 and 71, multiplexer 72, shapers 73 and 74, elements-OR 75-77, matrix 78 RAM, RS-flip-flop 79, element And 80, element 81 delay, register 82, lement 83 delays, RS-flip-flop

84, the element OR NOT 85, the driver 86, the element 87 delay.

The device operates in three modes: registration of the current-voltage characteristic, registration of the field repair and registration of the dependence kr (H).

Each of the characteristics is recorded and stored in RAM 15. The memory of RAM 15 (in this case, 4Kx11 bits) is divided into four blocks of 1000 cells each. The first block with addresses 0–999 records the forward path of the current – voltage characteristic, the second block with addresses 2023–1024 records the reverse stroke of the current – voltage curve, the third block with addresses 2048–3047 records the VPH, and the fourth block with addresses 3072 ± 4071 shows the dependence of (N).

The timing diagrams (Fig. 2) of the device operation in the registration mode of the IVC are the following voltage plots: on the bus Starting the device (a), at the output of the delay element 20 (b), at the output

element And 22 (c), at the output of the trigger 28 - the trigger of the current-voltage characteristic (g), at the output of the element OR 37 (d), at the inverse output of the trigger 70 RAM 15 (e), at the inverse output of the trigger 71 RAM 15 (g), trigger output 84 RAM 15 (h), on

the output of the element And 80 RAM 15, the start of the ADC (s), the output of the element 87 delay RAM 15 (K), the output of the former 2 AC (l) and the output of the analog switch 8 (m).

In the initial state, the RAM is in read mode and on the oscilloscope screen you can observe the selected part of the RAM memory (two blocks), in this case, the forward and reverse branches of the previously recorded curve

IVC, After the Start signal (Fig. 2a), the initial, second and third current drivers are entered into the initial code located at the inputs D. The output signal of the delay element 20 (Fig. 26), passed through the element 22 (Fig. 2c) , set 1 trigger 28 of the IVC mode (Fig. 2d). RAM 15 runs from now on in two modes:

Reading and Writing determined by the state of the trigger 84 of RAM 15. A write mode is turned on only when the counter 65 is in addition mode, the code 1000 is formed at the outputs, and the transfer appears in the subtraction mode. Counter 65 is controlled by a read mode trigger 70 (Fig. 2e). This trigger changes the counting direction of the counter 65 and, at the same time, connects to the address portion of RAM the high bit of the block (n + 1). The multiplexer 72 of RAM 15 connects to the address part either the code of the read counter 65 or the code of the write counter 66. In the initial state, the counter 66 is in the addition mode and is reset to zero (Fig. 2g). The first 1000 read pulse (Fig. 2d) sets the trigger 84 to 1, triggers the A / D converter 10 (Fig. 2i) and when receiving a signal. The end of the measurement of the A / D converter with the output signal of the OR-NE 85 element records the A / D code in the first cell of the RAM (Fig. 2h). ), adding 1 to the record counter 66 (Fig. 2k). At the same time, the counter code in the AC shaper 2 increases by 1 and its amplitude increases by 0.1% (Fig. 2n). The matrix 78 of RAM enters the reading mode of the second part of the RAM (addresses 2023-1024). When a pulse appears at the transfer output of the counter 65, the second cell of the RAM is recorded, the counter code 66 is increased, and the amplitude of the alternating current driver 2 is increased. The procedure continues until a record is written in the 1000 cell of RAM. At this point, the trigger 71 changes its state and switches the counter 66 to the subtract mode. The next write pulse records in the cell with the address 1024 + 999 2023, since 1 from the output of the trigger 71 is transmitted through the multiplexer as (n + 1) RAM (for this example, 11 is the address bit). At the same time there is a decrease in the current at the output of the shaper 2 AC. The last entry in this mode occurs in the cell with the address 1024, after which the transfer signal of the counter 66 resets the triggers 71, 28 and the trigger 79 of the RAM record.

To calibrate the device at the beginning of the recording, the calibration signal is recorded in the first (or several first) RAM cell. At this time, the sample under study is in the superconducting state. A known signal is supplied to the input of amplifier 7 from a driver 6 of the calibration signal, which is a step-down transformer with two equal output windings, the time of which is determined by the duration of operation of a single vibrator 16, which permits the passage of voltage from the driver AC 2 to the input of the driver 6 calibration signals (Fig. 2m).

The TPC recording mode is characterized in that 5 the value of the alternating current is set at the initial recording and does not change later. The current through the coil of the solenoid increases after writing to the next RAM cell. This current is provided by the shaper 3 of the solenoid current due to the fact that the clock input of the shaper 3 receives pulses from the fifth output of the RAM 15, previously passed through the AND 32 element and the OR 18 element. In this 15 mode, the recording is performed in the cells with addresses 2048-3047.

The write mode kf f (H) is provided by the unit 19 for measuring the critical current (Fig. 3), and the timing diagrams for its operation 0 (Fig. 4) represent the voltage plots: at the first input of the unit (a), at the second input of the unit (b ), the current through the sample (c), the output of the comparator is 39 (d), the output of the comparator is 40 (d), the output of the trigger 48 (e), the output 5 of the trigger 49 (g), the unit output of the trigger 59 (h) , at the output of the element OR 58 (s), at the output of the trigger 52 (k), at the output of the single-vibrator 53 (l), at the sixth output of the block (m), at the output of the element And 57 (n), at the second 0 output of the block (o) on the third exit block a (n) and the first output block (p).

The critical current measurement unit 19 operates as follows.

The voltage from the output of the amplifier 7 is supplied to the first inputs of the comparators 39 and 40, to the second input of the comparator 39 a voltage of the first threshold is applied that exceeds the value of the noise voltage, to the second input of the comparator 40 a voltage of 0 is applied The IVC on the abscissa line between its intersection point with the abscissa line and the first threshold value and between the two threshold values would be equal to 5 between them.

After the Start signal (Fig. 4a) and the initial entry into the first, second and third current drivers, the clock pulses are fed to the constant-current driver 1, the information is recorded in the last quarter of RAM, Tek starts to increase through the sample (Fig. 4c) and a voltage appears at the output of amplifier 7 (Fig. 46). When this voltage exceeds a predetermined level of the first threshold, the comparator 39 is triggered and through the driver 41 sets to 1 the trigger 48 of the first comparator (Fig. 4e). From this moment on, the clock pulses of the generator 35 clock pulses from the fourth input of the block pass

elements 47 and 54, OR 58 and arrive at the counting input of the reversible 61 counter (Fig. 4i), which is in the initial state in the addition mode from flip-flop 59, when the voltage at the output of the amplifier 7 reaches the second value (Fig. 46), the second comparator 40 (FIG. 4d) is triggered and, through the shaper 42, flushes the triggers 48 and 59 to zero and sets the triggers 49 and 51 to 1. The counter 61 switches to the subtraction mode and simultaneously switches to the DC shaper 1 unit . The pulses from the output of the counting trigger 50 through the element And 55 and the element OR 58 are fed to the counting input of the reversible counter 61 with a frequency half as large as the frequency of the clock pulses. The moment when the counter 61 goes to zero is considered the instant of determination of the critical current. At this moment, from the transfer signal of the counter 61 by the shaper 64 a pulse is generated, which passed the element 62 and (necessary to block the possible transfer in the add mode), is supplied as a strobe entry of the counter code of the direct current driver 1 to the register 17 (Fig. 4o). The code from register 17 through multiplexer 12 is fed to write to RAM 15. With the same signal, trigger 52 is set to 1 (FIG. 4k) and allows the passage of a predetermined number of clock pulses to counter 60 input through AND 56. This number is determined by the value of the current through the sample, to which it is necessary to reduce it, so that the sample goes into the superconducting state. This value is determined by the discharge of the counter 60, which is connected to the driver 63. For example, with a delay of 16 pulses, the fifth discharge of the counter 60 is connected to the input of the former 63. The signal from the former 63 (FIG. 4m) resets Triggers 52.51 and 44, triggers a one-shot 53 (Fig. 4L) and adds 1 to the current generator counter 3 solenoid currents. FIG. 4p shows the blocking signals that are generated when the comparators 39 and 40 are triggered. At these moments, a zero signal is recorded in RAM, since And 11 elements are blocked. FIG. 4p shows the signal at the inverse of the output of the trigger 51, controlling the mode of the direct current driver 1.

Claims (1)

1. An apparatus for measuring the characteristics of superconducting samples, comprising a direct current driver, an alternating current driver, the outputs of which are connected to the inputs of a mixer connected to the terminals for connect the sample, the potential outputs of which are connected through the driver of the calibration signal to the amplifier inputs with a synchronous detector, a solenoid, a current driver of the solenoid, the current outputs of which are connected to the solenoid winding, and a cryostat, in order to increase the accuracy and reduce the measurement time, An analog-to-digital converter is inserted into it, 5 critical current measurement unit, random access memory, clock pulse generator, two divider counters, two digital-to-analog converters, delay element, three 0 trigger, analog switch, register, one-shot, AND, OR elements, current amplifier, with the Start bus connected to the installation inputs of direct and alternating current and current drivers 5 solenoid, and through the delay element is connected to the first inputs of the first, second and third elements AND and the installation input of the first trigger, the first reset input of which is connected to the first reset inputs of the second and third triggers, with the seventh critical current measuring unit, with fifth an input of a random access memory block, with a bus Reset, as well as with dump inputs of DC and AC shapers and solenoid current, whose initial loading inputs are connected to the recording buses, output preamplifier connected to the input of analog-to-digital preobra0 zovatel and the second input of the critical current measurement unit, a third input coupled to a critical current mode bus and a second input of the first AND gate whose output is connected to the first input unit 5 measure the critical current and to the first input of the first element OR, to the second and third inputs of which are connected respectively the outputs of the second and third elements AND and the installation inputs of the second 0 and third triggers, the outputs of which are connected respectively to the first inputs of the fourth and fifth elements AND, the second inputs of which are connected to the fifth output of the operational storage unit, the sixth output of which is connected to the second reset inputs of the first and second triggers and the first input of the second the OR element, the second and third inputs of which are connected to the outputs of the sixth and seventh elements AND, the first inputs of which connected respectively to the tires of the measurement modes of the volt-field characteristics and critical current, and the second inputs are connected to the second fault input of the third trigger and the seventh output of the random access memory, the first and second outputs of which are connected respectively to the inputs of the first and second digital-analog converters, and the third the output of the random access memory is connected to the input of the ADC start, the output. The end of the measurement of the ADC is connected to the first input of the random access memory, to the second inputs the outputs of the multiplexer are connected to the first inputs of which through the element I are connected the outputs of the analog-digital converter, to the second inputs of the multiplexer are the outputs of the register whose information inputs are connected to the code output of the dc generator, and the input of the recording unit of the critical current measuring unit whose sixth output is connected to the first input of the third OR element, the second input of which is connected to the output of the fifth AND element, and the output of the third OR element is connected to the clock m input of the current coder of the solenoid, the output of the clock pulse generator is connected to the input of the first counter-divider and the first input of the tenth element AND, the second input of which is connected to the inverse output of the first trigger, and the output is connected to the first input of the fourth element OR, the output of the first counter-divider connected to the fourth input of the critical current measurement unit and to the input of the second counter-divider, the output of which is connected to the first input of the ninth And element, the second input of which is connected to the forward output of the first trig Ser and to the input of the current amplifier, the output of which is connected to the output of the device, the output of the ninth element AND is connected to the second input of the fourth OR element, the output of which is connected to the fourth input of the operational memory block, the third input of which is connected to the output of the first OR element and through the one-shot to the control input of the analog switch, the input of which is connected to the output of the driver. AC, and the output is with the calibration signal generator input, the output of the fourth element I is connected to the clock input of the alternating current generator, the output of the second element OR is connected to the sixth input of the random access memory, the third output of the critical current measurement unit is connected to the second inputs of the eighth element I. the fourth outputs of the critical current measurement unit are connected to the control inputs of the multiplexer, the fifth output of the critical current measurement unit 5 is connected to the clock input of the direct current driver, the first output of the critical current measurement unit and the fourth output of the operational memory unit 10 are connected respectively to the inputs of the operation mode of the direct and alternating current drivers, 2, the apparatus according to claim 1, characterized in that the critical measurement unit 15 current is made in the form of two comparators, RS-flip-flops, a counter, drivers, a reversible counter, a counting trigger, a one-shot, AND, OR elements, and the first installation input of the first trigger is connected to the first input of the unit, the combined first inputs of the first and second comparators are connected with the second input of the block, the combined second inputs of the third seventh And elements are connected to the third 5 input of the block, the combined second input of the first element And the first input of the second element And connected to the fourth input of the block, the second in the moves of the first and second comparators are connected respectively to the fifth and sixth inputs of the block, the combined first input of the first element OR, the second fault inputs of the first, second and third flip-flops are connected to the seventh input of the block, the inverse output 5 of the third trigger, the output of the third element OR is connected to the first and third outputs of the block, the combined output of the fourth element AND, the setup input of the second trigger and the second input of the first element 0 OR are connected to the second output of the block, the direct and inverse outputs of the first trigger are connected to the fourth outputs of the block, the combined output of the first element AND, the clock input of the counting trigger and 5, the first input of the fifth element I is connected to the fifth output of the unit, the combined output of the third driver, the one-shot input and the first fault inputs of the first, second and third flip-flops are connected to 0 by the sixth output of the block, the direct output of the first trigger is connected to the first input of the first element I, the outputs of the first and second comparators are connected to the inputs of the first and second drivers, the output 5 of the first shaper is connected to the first input of the third IL-I element and the setup input of the sixth trigger, the output of the second shaper is connected to the second input of the third OR element and the first input of the seventh And element, the output of which is connected to the second reset input of the sixth trigger, the third, and fifth installation inputs triggers, the fault input of the fourth trigger, the output of the first element OR is connected to the first fault input of the sixth trigger, the fault input of the fifth trigger, the setup input of the fourth trigger, with Rosov input counting trigger input of fault counter, down counter, counting trigger output connected to a second input of the sixth AND gate having a first input connected to the output of the fifth flip-flop, the output of the sixth flip-flop coupled to a second input of the fifth AND gate, outputs of said fifth and the sixth elements And are connected respectively to the first and second inputs of the second element OR, the output of which is connected to the clock input of the reversible counter, the input mode of operation of which is connected to the direct output of the fourth trigger, the transfer output of the reversible counter through the fourth driver is connected to the first input of the fourth element I, the second the input of which is connected to the inverse output of the fourth trigger, the output of the second trigger is connected to the second input of the second element I, the output of which is connected to the clock input of the counter, the output of which connected to the input of the third shaper. & "3 Figz FIG 4