JPS62213578A - Control circuit for pwm inverter - Google Patents

Abstract

PURPOSE:To limit a current ripple in a constant range at switching time of a PWM inverter by limiting the range of a carrier data to be corrected when switching from an arbitrary phase synchronous PWM mode to a stationary phase synchronous PWM mode. CONSTITUTION:A frequency converter 1 outputs a clock responsive to an inverter output frequency command to a microcomputer 2. The microcomputer 2 outputs a PWM data and carrier pulse to an interval timer 15 for outputting a PWM signal. A carrier data limiter 8 is provided in the microcomputer 2, and when shifting from an arbitrary phase synchronous PWM mode to a stationary phase synchronous PWM mode, carrier data corrected by a carrier data corrector 8 is limited to a predetermined range on the basis of the table value of a carrier table 6.

Description

[Detailed Description of the Invention] [Extra-industrial Field of Application] This invention is a control circuit for a PWM (pulse width modulation inverter device), in particular, a control circuit having an asynchronous PWM mode region and a synchronous PWM mode region, and a control circuit for variable DC power. The present invention relates to a control circuit for a PV/M inverter device that converts power into a frequency and variable voltage power flow.

[Conventional technology]

Asynchronous PWM refers to a case in which the ratio of the reference wave sine wave frequency to the carrier frequency is not an integer, and synchronous PWM refers to a case in which the ratio between the reference wave sine wave frequency and the carrier frequency is an integer.

The selection of these modulation methods depends on the application, but for example, in low-speed ranges, carrier harmonics can be used to easily avoid mechanical vibrations and to reduce unpleasant noise caused by carrier fluctuations. Asynchronous PWM is used. In addition, in the region where the carrier pulses in the high-speed region are small, stable rotation of the motor can be achieved using a synchronous method with no fractional harmonics. This is a professional rib diagram showing a control circuit for an inverter. ) is output from y,=
Convert the frequency of the base mOK and convert the frequency of the first clock 11. ri f, O
Frequency converter outputting as K, (2) C code (3),
(4), (5), (6), (9), C1O,
(11), C10, Ht marked T, which has the functions of each component, is a 11. Select one of the reference ON signals according to the selection signal, and output the output signal.
The data selector that outputs K and the data selector (to) is 1st, which is output from the rib microcomputer (2) and 7: PWM data, carrier pulse, and the second clock from data selector α4.
fc-(This is an interval timer that creates the l'WM signal based on ML.

Next, each component of the one-chip microcomputer (2) will be explained. (3) is a ring counter, and the first
(4) A phase counter that counts the clocks f and OfL of
(5) is a phase corrector that corrects the phase shift that occurs when carrier data is changed according to the mode command and carrier station wave number command (hereinafter referred to as fc command); In the case of , the sin of 8 phases is
A sine table that stores data and obtains sine data for 8 phases by converting 1 phase data obtained from the phase counter (3) through the phase corrector (4) into 6, and (6) is a mode command; A carrier table that obtains one carrier data according to the fc command. (7) is an arbitrary phase synchronization in which the phase relationship between the carrier waveform and the reference sine wave waveform is arbitrary when the mode command switches from asynchronous PWM mode to synchronous PWM mode. P
Once the mode is switched to WM mode, when switching from this arbitrary phase synchronization PWM mode to the fixed phase synchronization PWM mode in which the phase relationship between the carrier waveform and the reference sine wave waveform is always constant, in order to keep the phase relationship between the carrier and the sine wave constant, A carrier data corrector that corrects carrier data obtained from the carrier table (6) based on the count result of the count value. (
9) is an fc-(AL selector) which is determined according to a mode command specifying the asynchronous PWM mode or a synchronous PWM mode and outputs a selection signal; αG is a carrier data corrector (
The carrier data obtained from [7] is compared with the output of the data selector α4, that is, the count value of the carrier counter α that counts the second clock fc-C, and if they match, the carrier outputs a carrier pulse. Count value comparator, (6
), (13 is a multiplier.

Next, the dynamic f'l-sζ will be explained. The count value of the carrier counter (6) and the value of the +37 count value comparator αO match 7%, and before they match, the carrier data, PWI information information 9 communication, carrier Set the count value comparator αO, interval timer similar, and data selector αO, respectively. Next, take in the phase count value θ. Next, a selection signal to be sent from the fc-ON selector (9) to the data selector α4 is determined.

When the operation mode of the currently output PWM signal is the synchronous PWM mode, the data selector α4 is configured to strike the carrier counter and input the phase counter (3) in order to maintain the relationship between the carrier phase and the reference sine wave phase in a synchronous state. Kuro I/
To make 7 equal, select f, OK.

On the other hand, in the case of the asynchronous PWM mode, the relationship between the carrier phase and the reference sine wave phase is made irrelevant, and reference ON is selected.

A selection signal for selecting this data selector is determined according to a mode command.

Next, carrier data is taken from the carrier table (6) in response to the fc command and a mode command for determining whether the mode is asynchronous PWM mode or synchronous PWM mode.

At this time, when the mode command switches from asynchronous PWM mode to synchronous I'WM mode, the carrier data corrector (7) temporarily switches the phase relationship between the carrier waveform and the reference sine wave waveform to arbitrary phase synchronous PWM mode. In contrast, from this arbitrary phase synchronization PWM mode, the phase relationship between the carrier waveform and the reference sine wave waveform is corrected by the carrier data obtained from the carrier table (6) using the count result of a constant fixed value.

In addition, the phase corrector (4) adjusts to 1 in response to the mode command and fc command.
This corrects the phase shift that occurs when carrier data is changed. With this corrected phase count value θ,
From the sin table (5), sine wave data sin θ of the same phase as γ is obtained according to the phase count value θ. Then, from ζ, the inverter output voltage command V at that time is set to V using the multiplier @.
Find -5ina.

Next, a multiplier (
To) carrier data imported earlier and the above V-sin
PWM information is calculated by multiplying by θ.

In this way, one selection signal and carrier data are obtained.

As mentioned above, the PWM information is the carrier counter αυ
When the count value of the carrier count value comparator αO matches the set value of the carrier count value comparator αO, they are output to the key, IJA count value comparator αG, and the interval timer αSI data selector α station, respectively. This information is then used as the P for this career section.
It becomes a WM signal.

Next, in the above operation, particularly the case where the mode command is changed will be explained with reference to FIGS. 5 and 6.

FIG. 5 is a flowchart showing the processing within the microcomputer. FIG. 6 is a time chart of the above processing, where A is the base sine wave, B is the counter counter, C is the phase count value, D is the carrier counter value, T1 is the asynchronous PWM mode, and T2 is the arbitrary phase synchronized PWM mode. , T3 is a fixed phase synchronization f'WM mode.

Always keep the phase of the sine wave and carrier constant during synchronization1
Therefore, the phase of the carrier is always changed at a constant phase. ・When moving from asynchronous mode to synchronous mode, for the first time in the synchronous loop, switch to arbitrary phase synchronous mode where the phase relationship between the carrier and the sine wave is not one step, and change the phase counter (3 ) and the input clock to the carrier counter αυ to the value of f”OR−, and make the count values of the phase counter (3) and carrier counter u1) equal. From the second time onwards, the carrier and the fundamental a sine wave Whether it is fixed phase synchronization mode where the phase relationship of the force is one force)
to judge.

If it is not in fixed phase synchronization mode, determine how much the current phase differs from the phase at which the carrier ends on the reference sine wave in fixed phase synchronization mode.
WM calculation takes in 0-phase count value is fixed phase PWM
So that the acquisition phase is on the reference sine wave in mode,
Change your current carrier data. At this time, if the nz data is changed to be shorter than in the normal fixed phase synchronization P to VM mode, the carrier period will be shortened, and there is a possibility that necessary processing cannot be performed during that period. In this T, the changed carrier data is the normal carrier data I (,
Phase difference E between the current phase and the carrier end phase at fixed phase
The carrier data corresponding to ζ is generated and becomes fkob. Therefore, the carrier cycle at the time of change is more than one time and less than twice the normal time.

However, when calculated using the initial phase count value of the carrier, T
When this information becomes the next (b) PWM signal, the output phase and the phase count value are 1 key, 1 key on the reference sine wave.
There is a phase thread equivalent to 7 minutes.

If the phase of one carrier is the same at N+, no problem will occur, but when changing the key rear period as described above (1) (ζ is changed by the phase of 1 k Je 117,
The degree of phase thread changes. At this point, the continuity of the output phase is lost. To prevent this, before using the value taken in by the phase count value for PWM information calculation calculation, the phase compensator (4) is used to calculate the phase k for one carrier.
Phase correction is performed to prevent phase shifts due to changes in Kirlia data. Switch to fixed phase synchronization PWM mode in this way.

FIG. 6 is a time chart at the time of switching.

After one switching, the mode commands are synchronized) If the WM mode continues to be commanded, the l'WM signal is created while maintaining a fixed phase relationship without changing the carrier data and data selector α slope selection signals. I will do it.

Also, Fig. 7 is a time chart of one cycle of PWM calculation, where A is the basic sine wave, B is the carrier, C is the phase count value, D is the carrier count (71%, D+ is the expanded value of the carrier count value, E is the processing content, and F is the PWM signal.

[Problem that the invention seeks to solve]

Since the control circuit of the conventional PWM inverter device is configured as described above, when changing from the arbitrary phase synchronization mode to the fixed phase synchronization mode lζ, the current -l pull at the time of switching is constant depending on the switching timing i. However, the reproducibility of the output current is poor and the output current is low.

In addition, in the worst case, the current pull value during switching is approximately twice the normal value, resulting in an increase in the peak value of the output current, and there is no margin for the overcurrent value of the inverter main circuit, resulting in an overload. Tolerance decreased. However, there are other problems, such as the need to increase the capacity of the inverter.

This invention was made with the aim of solving the above-mentioned problems, and allows smooth switching from arbitrary phase synchronization mode to fixed phase synchronization mode, and reduces current and I during switching.
An object of the present invention is to obtain a control circuit for a PWM inverter device that can suppress pull.

[Top means to solve problems]

The control circuit of the l'WM inverter device according to the present invention includes:
A carrier data limiter is provided to limit the carrier data corrected by the carrier data corrector to a certain range.

[Effect]

When the carrier data limiter in this invention switches from arbitrary phase synchronization PWM mode to fixed phase synchronization PWM mode,
G. The carrier data to be corrected is limited within a certain range so that the relationship between the IJA waveform and the reference sine wave waveform is constant, and the correction is performed multiple times.

[Embodiments of the invention]

An embodiment of the present invention will be explained below.

In the first factor, (8) is the table value m obtained from the carrier data corrected by the carrier data corrector (7) and the carrier table (6) when moving from the arbitrary phase synchronization PWM mode to the fixed phase synchronization PWM mode. times (m is 1<
If it is within the range of m < 2), the corrected γ carrier data is used for the current calculation, and if it is greater than m times, the corrected carrier data is re-corrected and the carrier data is increased to m times the table value. It is a vessel. The circuit other than this carrier data limiter (8) is completely the same as the conventional circuit shown in FIG.

FIG. 2 is a flow chart of the microcomputer (2).

Figure m8 is a time chart diagram of the above processing, where human is a reference sine wave, B is a carrier, C is a phase count value, D is a carrier count value, T1 is an asynchronous PWM mode, T2 is an arbitrary phase synchronous PWM mode, T3 is fixed phase synchronization PWM
mode. When switching from arbitrary phase synchronization PWM mode to fixed phase synchronization PWM mode, first, it is determined whether the mode is fixed phase synchronization PWM mode. In the case of arbitrary phase synchronization PWM mode, the carrier data is corrected and a transition to fixed phase synchronization PWM mode is attempted.

However, if the corrected carrier data is within m times the carrier data before correction, that value is adopted and the fixed phase synchronization P
Transition to WM mode f. Also, if it is larger than m times,
In this PWM calculation process, the corrected carrier data is made m times the carrier data before correction, and the fixed phase synchronization P
Do not switch to WM mode. This T rice, next rwmH
Also, the process following the above-mentioned determination is performed until the fixed phase synchronization PWM mode is established. As described above, the arbitrary phase synchronization PWM mode is gradually shifted to the fixed phase synchronization PWM mode while correcting the xeria synchronization within a certain range.

In the above embodiment, the fa-OL selector is implemented by microcomputer software, but π can also be configured with a read circuit using free, I, flow, and 1 blocks. However, instead of the data selector, a frequency converter can be used.

〔Effect of the invention〕

As described above, according to the present invention, when switching from arbitrary phase synchronization PWM mode to fixed phase synchronization PWM mode, the range of carrier data to be corrected is limited. A PWM inverter that can limit the output current to a range of one foot, improve the reproducibility of the output current, prevent an increase in the output current B value, and suppress the decline in overload capacity. This has the effect of providing a control circuit for mounting.

[Brief explanation of drawings]

Fig. 1 is a diagram showing a control circuit of a PWM inverter device according to an embodiment of the present invention, Fig. 2 is a flowchart of an embodiment 1 of the present invention, and Fig. 3 is a flowchart showing a control circuit of a PWM inverter device according to an embodiment of the present invention. An example of the operation mode when switching from the asynchronous mode to the synchronous mode at this time and a schematic time chart of PWM calculation, Fig. 4 is a pro-life diagram showing the control circuit of a conventional PWM inverter device, and Fig. 5 is its operation. FIG. 6 is a time chart for switching from asynchronous mode to synchronous mode, and the seventh factor is a time chart for PWM calculation-cycle. In the figure, (2
) is a 1-chip microcomputer, (3) is a phase counter, (4) is a phase corrector, (6) is a carrier table, (7) is a carrier data corrector, (8) is a carrier data limiter, ( 9) is a fa-OK selector, αO is a carrier count value comparator, (6) is a yearly rear counter, α4 is a data selector, and (to) is an interval timer.

Claims (1)

[Claims] In a control circuit of a PWM inverter device that has an asynchronous PWM mode region and a synchronous PWM mode region and converts DC power into AC power with variable frequency and variable voltage, a first clock proportional to an inverter output frequency command; a second clock independent of the output frequency command;
a data selector that selects and outputs the first clock or the second clock according to a mode command instructing asynchronous PWM or synchronous PWM, and a phase that counts the first clock to determine the phase of the inverter output waveform. a counter; an output clock selector that determines a selection signal for the data selector according to the mode command; a carrier table that determines carrier data from the mode command and carrier frequency command; and a carrier counter that counts the output clock of the data selector. A carrier data corrector that corrects carrier data obtained from the carrier table based on the count result of the phase counter when switching modes; and a carrier meter that outputs a matching signal when the output of the carrier data corrector matches the output of the carrier counter. A carrier data limiter that limits carrier data to a certain range by comparing carrier data corrected by a numerical comparator and the carrier data corrector with a table value obtained from the carrier table; and a carrier data limiter that receives the output of the carrier data limiter. a one-chip microcomputer equipped with a phase corrector that corrects the phase data obtained from the phase counter; and PWM data and carrier pulses output from the one-chip microcomputer and an output clock output from the data selector. and an interval timer for creating a PWM signal, and when the mode command switches from asynchronous PWM mode to synchronous PWM mode, the phase data is output from the phase counter and the carrier table according to the next output timing of the carrier counter. Then, at the next output timing of the carrier counter, the data selector selects a change from the second clock to the first clock, and sets the difference value between the predetermined phase and the timing phase within a certain range. A control circuit for a PWM inverter device, characterized in that the above series of operations is performed a plurality of times by adding new carrier data by adding a limited value within the carrier data, and performing a predetermined phase correction in accordance with a change in carrier data.