JPS62213279A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62213279A JPS62213279A JP5732686A JP5732686A JPS62213279A JP S62213279 A JPS62213279 A JP S62213279A JP 5732686 A JP5732686 A JP 5732686A JP 5732686 A JP5732686 A JP 5732686A JP S62213279 A JPS62213279 A JP S62213279A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas
- doped
- type
- superlattice structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 41
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 34
- 239000010931 gold Substances 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 11
- 239000011651 chromium Substances 0.000 claims description 8
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 1
- 230000007423 decrease Effects 0.000 abstract description 8
- 239000007772 electrode material Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 5
- 238000005275 alloying Methods 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 4
- 229910052738 indium Inorganic materials 0.000 abstract description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 abstract description 3
- 241001101998 Galium Species 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 239000000969 carrier Substances 0.000 description 7
- 239000013078 crystal Substances 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 7
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 5
- 238000013139 quantization Methods 0.000 description 4
- 239000002784 hot electron Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 101000960224 Clarkia breweri (Iso)eugenol O-methyltransferase Proteins 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
Abstract
Description
【発明の詳細な説明】
〔概要〕
この発明は、砒化ガリウム／砒化アルミニウム超格子構
造から供給される２次元電子ガスをチャネルとする半導
体装置にかかり、
オーミックコンタクト電極を砒化インジウムガリウム層
に接して配設することにより、合金化熱処理を行うこと
なく良好なコンタクトを得て、電子密度の低下等の熱劣
化を防止するものである。[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor device in which a two-dimensional electron gas supplied from a gallium arsenide/aluminum arsenide superlattice structure is used as a channel, and an ohmic contact electrode is connected to an indium gallium arsenide layer. By providing this, good contact can be obtained without performing alloying heat treatment, and thermal deterioration such as a decrease in electron density can be prevented.
本発明は半導体装置、特に空間分離ドーピングと界面量
子化による高移動度のキャリアをチャネルとする例えば
高電子移動度電界効果トランジスタ（ＩＩＥＭＴ）等の
半導体装置の改善に関する。The present invention relates to improvements in semiconductor devices, particularly semiconductor devices such as high electron mobility field effect transistors (IIEMTs) that use high-mobility carriers as channels through spatial separation doping and interface quantization.
例えばＨＨＭＴは、ノンドープの砒化ガリウム（ＧａＡ
Ｓ）層とｎ型砒化アルミニウムガリウム（ＡＩＧａＡｓ
）Ｆ［等のへテロ接合界面近傍に２次元状態の電子を形
成し、不純物をドーピングする領域とキャリアが移動す
る領域とを空間的に分離してキャリア移動度を増大し、
高速デバイスとして強い期待が寄せられている。For example, HHMT is made of undoped gallium arsenide (GaA
S) layer and n-type aluminum gallium arsenide (AIGaAs
) F[, etc., to form electrons in a two-dimensional state near the heterojunction interface, and spatially separate the region where impurities are doped and the region where carriers move to increase carrier mobility,
There are strong expectations for it as a high-speed device.
空間分離ドーピングとキャリアの界面量子化により高移
動度を実現している半導体装置の例として、ＨＥＭＴの
一例の模式側断面図を第２図（ａｌ、（ｂｌに示す。As an example of a semiconductor device that achieves high mobility through spatial separation doping and interfacial quantization of carriers, a schematic side sectional view of an example of a HEMT is shown in FIGS.
同図（ａ）に示すｌ（ＥＭＴの従来例では、半絶縁性Ｇ
ａＡｓ基板１１上にノンドープのｉ形ＧａＡｓ層１２と
、これより電子親和力が小さく例えば濃度２ ＸＩＯ”
ｅｌｌ−”程度のドナー不純物がドープされたｎ型Ａ
１ｘＧａ 、 ＋ 、Ａｓ層１３と、これと同程度以上
にドナー不純物がドープされたｎ型ＧａＡｓ層１４とが
設けられ、ｎ型ＡｌＧａＡｓ層１３からｉ形ＧａＡｓ層
１２へ遷移した電子によってペテロ接合界面近傍に２次
元電子ガス１２ｅが形成される。この２次元電子ガス１
２ｅは不純物散乱による移動度低下が殆どなく、格子散
乱が低下する例えば７７に程度以下の低温において最も
高い移動度が得られる。l shown in (a) of the same figure (in the conventional example of EMT, semi-insulating G
A non-doped i-type GaAs layer 12 is formed on the aAs substrate 11 and has a lower electron affinity than the non-doped i-type GaAs layer 12, for example, at a concentration of 2XIO".
n-type A doped with donor impurities of the order of ell-”
A 1xGa, +, As layer 13 and an n-type GaAs layer 14 doped with donor impurities to the same extent or higher are provided, and electrons transferred from the n-type AlGaAs layer 13 to the i-type GaAs layer 12 form a Peter junction interface. A two-dimensional electron gas 12e is formed nearby. This two-dimensional electron gas 1
In 2e, there is almost no decrease in mobility due to impurity scattering, and the highest mobility can be obtained at a low temperature of, for example, 77 degrees or lower, where lattice scattering decreases.
この半導体基体のｎ型ＧａＡｓ層１４上にソース、ドレ
イン電極１５を例えば金ゲルマニウム／金（ＡｕＧｅ／
＾Ｕ）を用い、ｎ型ＡｌＧａＡｓ電子供給層工３上にゲ
ート電極１６を例えばチタン／白金／金（Ｔｉ／ＰＬ／
Ａｕ）を用いて設け、ゲート電極１６によるショットキ
空乏層で２次元電子ガス１２ｅの面密度を制御してトラ
ンジスタ動作が行われる。なお１５Ａはソース、ドレイ
ン電極１５と半導体基体との間に形成された合金化領域
である。Source and drain electrodes 15 are formed on the n-type GaAs layer 14 of this semiconductor substrate, for example, using gold germanium/gold (AuGe/
For example, a gate electrode 16 is formed on the n-type AlGaAs electron supply layer 3 using titanium/platinum/gold (Ti/PL/
A Schottky depletion layer formed by the gate electrode 16 controls the areal density of the two-dimensional electron gas 12e to perform transistor operation. Note that 15A is an alloyed region formed between the source/drain electrode 15 and the semiconductor substrate.
この構造のｎ型ＡＩＨＧａＩ−ＸＡｓ電子供給層１３と
ｉ型ＧａＡｓチャネル層１２との伝導帯のエネルギー準
位差が少ない場合には２次元電子ガス１２ｅの面密度Ｎ
ｓが小さくなるために、通常伝導帯の準位差を０．２５
ｅＶ程度以上、従ってｎ型＾１３（Ｇａ＋−ＪＳ電子供
給層１３の＾ｌｉ成比Ｘを０．３程度以上とすることが
望ましい。When the energy level difference in the conduction band between the n-type AIHGaI-XAs electron supply layer 13 and the i-type GaAs channel layer 12 in this structure is small, the areal density N of the two-dimensional electron gas 12e is
In order to reduce s, the level difference in the conduction band is usually set to 0.25.
It is desirable to set the ^li ratio X of the n-type ^13 (Ga+-JS electron supply layer 13 to about 0.3 or more).
しかしながら他方において、ＡＩ＞ＩＧａＩ−ｘＡｓ混
晶のＡＩ組成比Ｘが０．２５程度より大きいときには、
ドープしたシリコン（Ｓｔ）等のドナー準位が急激に深
くなる。この深いドナー準位は、２００に程度以下で赤
外線が入射すれば電子が伝導帯に励起され、光照射を停
止しても伝導電子がドナー準位に落ちないＰＰＣ（ｐｅ
ｒｓｉｓｔｅｎｔ ｐｈｏｔｏ ｃｏｎｄｕｃｔｔｖｉ
ｔｙ）等の現象を示してＯｘセンターと呼ばれるが、こ
れにより、ドーピング量を増加しても高いキャリア濃度
が得られず、特に低温における２次元電子ガス面密度Ｎ
ｓの低下、従って伝達コンダクタンスｇ、の低下を招い
ている。また光が入射したり、ホットエレクトロンがチ
ャネルからＡｌＧａＡｓ層に飛び込むことにより、２次
元電子ガス面密度Ｎｓ、電子移動度μ７及び閾値電圧Ｖ
い等が変動する現象が現れ、低周波雑音の原因ともなっ
ている。However, on the other hand, when the AI composition ratio X of the AI>IGaI-xAs mixed crystal is larger than about 0.25,
The donor level of doped silicon (St) etc. becomes deep rapidly. This deep donor level is a PPC (pe
rsistent photo conducttvi
However, due to this phenomenon, even if the amount of doping is increased, a high carrier concentration cannot be obtained, and the two-dimensional electron gas areal density N is particularly low at low temperatures.
This results in a decrease in s and therefore a decrease in transfer conductance g. In addition, when light enters or hot electrons jump from the channel into the AlGaAs layer, two-dimensional electron gas surface density Ns, electron mobility μ7 and threshold voltage V
A phenomenon in which the frequency of noise fluctuates appears, which is also a cause of low-frequency noise.
このＡｌＧａＡｓ混晶内の深いドナー準位に起因する問
題に対処するものとして第２図（ｂ）に示す従来例があ
る。本従来例では前記従来例のｎ型＾１．Ｇａ１−。There is a conventional example shown in FIG. 2(b) that deals with the problem caused by the deep donor level in the AlGaAs mixed crystal. In this conventional example, the n-type^1. Ga1-.
Ａｓ層１３に代えて、電子供給層をＧａＡｓ層２３ａと
ＡｌＡｓ層２３ｂとからなる超格子構造２３とし、Ｇａ
Ａｓ層２３ａに例えば濃度５×ＩＯ”Ｃ１１−’程度に
ドナー不純物をドーピングし、ＡｌＡｓ層２３ｂはノン
ドープとしている。Instead of the As layer 13, the electron supply layer is a superlattice structure 23 consisting of a GaAs layer 23a and an AlAs layer 23b.
The As layer 23a is doped with a donor impurity to a concentration of, for example, about 5×IO''C11-', and the AlAs layer 23b is undoped.
この改善により、ＡｌＧａＡｓ混晶層を電子供給層とす
るＨＥＭＴが、例えば温度７７Ｋにおいて電子移動度μ
ｎ ’ Ｉ Ｘ １０’ｃｍ”／ν、Ｓ、２次元電子ガ
ス面密度Ｎｓ’ｑ１．２ Ｘ １０” ｃｎ＋−”程度
であるのに対して、ＧａＡｓ／ＡｌＡｓ超格子構造を電
子供給層とする同等のＨＥＭＴは、２次元電子ガス面密
度Ｎｓ ”＝ ３．０ Ｘ １０” ｃｍ−”程度が同
等の電子移動度μ７で得られ、闇値電圧Ｖいの変動等の
問題も改善されると報告されている。With this improvement, HEMTs with an AlGaAs mixed crystal layer as an electron supply layer have an electron mobility of μ at a temperature of 77K, for example.
n' I An equivalent HEMT can obtain a two-dimensional electron gas surface density Ns "= 3.0 x 10" cm with an equivalent electron mobility μ7, and problems such as fluctuations in the dark voltage V can also be improved. It has been reported.
上述の如＜ ＧａＡｓ／ＡｌＡｓ超格子構造によりＡｌ
ＧａＡｓ混晶における深いドナー準位に起因する問題が
改善されるが、ＨＥＭＴ素子を実際に完成した状態では
、エピタキシャル成長直後の半導体基体に比較して、２
次元電子ガス面密度Ｎｓの低下、従ってシート抵抗の増
大などの劣化を層化ずる。As mentioned above, Al
Although the problem caused by the deep donor level in the GaAs mixed crystal is improved, in the actually completed state of the HEMT device, compared to the semiconductor substrate immediately after epitaxial growth, the
This results in layered deterioration such as a decrease in the dimensional electron gas areal density Ns and therefore an increase in sheet resistance.
製造プロセス中のこの劣化の最大要因は熱処理である。The biggest factor in this degradation during the manufacturing process is heat treatment.
すなわちｎ型ＧａＡｓ層１４上にオーミックコンタクト
電極材料として、例えば金ゲルマニウム合金（ＡｕＧｅ
）を厚さ２０ａｍ、金（Ａｕ）を厚さ２８０ｎｍ程度積
層被着、バターニングし、温度４５０℃、１分間程度の
熱処理により電極材料と半導体基体とを合金化して、ソ
ース、ドレイン電極１５のオーミックコンタクト抵抗を
低減しているが、この熱処理の過程でＧａＡｓ層２３ａ
にドープしたＳｉの拡散などにより超格子構造に損傷を
生じている。That is, as an ohmic contact electrode material, for example, a gold germanium alloy (AuGe
) to a thickness of 20 am, gold (Au) to a thickness of about 280 nm, buttering is performed, and the electrode material and the semiconductor substrate are alloyed by heat treatment at a temperature of 450° C. for about 1 minute to form source and drain electrodes 15. Although the ohmic contact resistance is reduced, during this heat treatment process, the GaAs layer 23a
The superlattice structure is damaged due to diffusion of doped Si.
ＨＥＭＴ等の界面量子化されたキャリアを利用する。Uses interfacial quantized carriers such as HEMT.
半導体装置のキャリア増大は重要な課題であり、その効
果を損なう要因の排除が強く要望されている。Increasing the number of carriers in semiconductor devices is an important issue, and there is a strong desire to eliminate factors that impair its effectiveness.
Ｃ問題点を解決するための手段〕
前記問題点は、ノンドープの砒化ガリウム層と、ドナー
不純物を含む砒化ガリウム層とノンドープの砒化アルミ
ニウム層とからなる超格子構造と、ドナー不純物を含む
砒化インジウムガリウム層とが積層されて、該ノンドー
プの砒化ガリウム層の 。Means for Solving Problem C] The problem is a superlattice structure consisting of a non-doped gallium arsenide layer, a gallium arsenide layer containing donor impurities, and a non-doped aluminum arsenide layer, and an indium gallium arsenide layer containing donor impurities. layers of the non-doped gallium arsenide layer.
該超格子構造との界面近傍に、該超格子構造から遷移す
る電子により２次元電子ガスが形成され、オーミックコ
ンタクト電極が該砒化インジウムガリウム層に接して配
設されてなる本発明による半導体装置により解決される
。In the semiconductor device according to the present invention, a two-dimensional electron gas is formed near the interface with the superlattice structure by electrons transitioning from the superlattice structure, and an ohmic contact electrode is disposed in contact with the indium gallium arsenide layer. resolved.
本発明によれば、ドナー不純物を含むＧａＡｓ層とノン
ドープのＡｌＡｓ層とからな４超格子構造から電子が遷
移して、ノンドープのＧａＡｓ層の該超格子構造との界
面近傍に２次元電子ガスが形成される半導体装置におい
て、そのオーミックコンタクト電極をドナー不純物を含
むＩｎｘＧａ１−ｘ＾Ｓ層に接して配設する。According to the present invention, electrons are transferred from a four-superlattice structure consisting of a GaAs layer containing donor impurities and an undoped AlAs layer, and a two-dimensional electron gas is generated near the interface between the undoped GaAs layer and the superlattice structure. In the semiconductor device to be formed, the ohmic contact electrode is disposed in contact with the InxGa1-x^S layer containing donor impurities.
Ｉｎ、Ｇａ＋−ｘＡｓ混晶はＧａＡｓ結晶よりエネルギ
ーバンドギャップＥｇが狭（、ＧａＡｓのＥｇ″−１，
４２ｅＶに対して例えばＩｎｏ、 ５Ｇａｏ、５Ａｓは
Ｂｇ ＃０．７６ｅＶであり、合金化熱処理を行わない
で低抵抗のオーミックコンタクトを得ることができる。In, Ga+-xAs mixed crystal has a narrower energy bandgap Eg than GaAs crystal (Eg''-1 of GaAs,
For example, Bg #42eV is 0.76eV for Ino, 5Gao, and 5As, and a low resistance ohmic contact can be obtained without performing alloying heat treatment.
この電極材料としては例えばクロム／金（Ｃｒ／Ａｕ）
が適しており、この電極材料でＩｎｘＧａ１−ｇＡｓ混
晶層にオーミックコンタクトするソース、ドレイン電極
と、ＧａＡｓ／ＡｌＡｓ超格子構造にショットキコンタ
クトするゲート電極とを同時に形成することも可能であ
る。Examples of this electrode material include chromium/gold (Cr/Au).
is suitable, and it is possible to simultaneously form source and drain electrodes in ohmic contact with the InxGa1-gAs mixed crystal layer and gate electrodes in Schottky contact with the GaAs/AlAs superlattice structure using this electrode material.
以下本発明を実施例により具体的に説明する。 The present invention will be specifically explained below using examples.
第１図はＨＥＭＴにかかる本発明の実施例を示す模式側
断面図である。FIG. 1 is a schematic side sectional view showing an embodiment of the present invention related to a HEMT.
本実施例の半導体基体は分子線エピタキシャル成長法（
ＭＢ２法）等により、半絶縁性ＧａＡｓ基板１上に、厚
さ例えばＩＪ１１１１程度のノンドープのｉ型ＧａＡｓ
層２、例えば濃度５ＸＩＯ’″ｃｎ＋−’程度にＳｉを
ドープして厚さ５ ｎｍ程度のｎ型ＧａＡｓ層３ａとノ
ンドープで厚さ例えば２ａｍ程度のｉ型ＡｌＡｓ層３ｂ
との７周期からなるＧａＡｓ／ＡｌＡｓ超格子構造３、
例えば厚さ約５゜ｎｍの範囲でＧａＡｓからＩｎｏ、
５Ｇａｏ、ＳＡＳまで次第にインジウム（Ｉｎ）の組成
比を増加し全厚さ１００〜２００ｎｍ程度で、濃度１×
１０１９ＣＩＩ＋弓程度にＳｔをドープしたｎ型ＩｎＧ
ａＡｓ層４を順次成長している。この半導体基体のｉ型
ＧａＡｓ層２のＧａＡｓ／ＡｌＡｓ超格子構造３との界
面近傍に２次元電子ガス２ｅが形成される。 この半導
体基体のゲート形成領域をリセスエッチングし、電極材
料層としてＣｒ約５０１１ｆｆＩ、Ａｕ約３００ｎｍを
積層して、ソース、ドレイン電極５、ゲート電極６を同
時に形成している。なお合金化領域を形成する熱処理は
実施しない。The semiconductor substrate of this example was grown using the molecular beam epitaxial growth method (
MB2 method) etc., a non-doped i-type GaAs with a thickness of about IJ1111, for example, is deposited on the semi-insulating GaAs substrate 1.
Layer 2, for example, an n-type GaAs layer 3a doped with Si to a concentration of about 5XIO'''cn+-' and having a thickness of about 5 nm, and an undoped i-type AlAs layer 3b having a thickness of about 2 am, for example.
GaAs/AlAs superlattice structure 3 consisting of 7 periods of
For example, in a thickness range of approximately 5 nm, from GaAs to Ino,
The composition ratio of indium (In) was gradually increased up to 5Gao and SAS, and the total thickness was about 100 to 200 nm, and the concentration was 1×.
1019CII + n-type InG doped with St to a bow level
The aAs layer 4 is grown sequentially. A two-dimensional electron gas 2e is formed near the interface between the i-type GaAs layer 2 and the GaAs/AlAs superlattice structure 3 of the semiconductor substrate. The gate formation region of this semiconductor substrate is recess-etched, and about 5011 ffI of Cr and about 300 nm of Au are laminated as an electrode material layer to simultaneously form a source electrode, a drain electrode 5, and a gate electrode 6. Note that heat treatment for forming alloyed regions is not performed.
本実施例では、エピタキシャル成長直後に例えば温度７
７Ｋにおいて電子移動度μａ ’ｑ ｌ Ｘ １０’ｃ
ｍ”／Ｖ、３％ ２次元電子ガス面密度Ｎｓ ’ ３．
ＯＸ １０” ｃｒａ−”程度である半導体基体を用い
て、ＨＢＭＴ素子完成後に同温度において有意差のない
２次元電子ガス面密度Ｎｓが得られ、同一半導体基体に
オーミック電極材料としてＡｕＧｅ／Ａｕを用い、温度
４５０℃、１分間程度の合金化熱処理を実施した比較試
料が、２次元電子ガス面密度Ｎ５＝１．２ｘｌＯ”ｃｍ
−”程度であるのに比較して本発明の効果が実証されて
いる。In this embodiment, for example, the temperature is 7
At 7K, electron mobility μa 'q l X 10'c
m''/V, 3% Two-dimensional electron gas surface density Ns' 3.
By using a semiconductor substrate of approximately OX 10"cra-", a two-dimensional electron gas areal density Ns with no significant difference was obtained at the same temperature after completion of the HBMT element, and by using the same semiconductor substrate with AuGe/Au as the ohmic electrode material. , a comparison sample subjected to alloying heat treatment at a temperature of 450°C for about 1 minute has a two-dimensional electron gas areal density N5 = 1.2xlO"cm
The effect of the present invention has been demonstrated compared to that of "-".
なお本発明は）ＩＥＭＴにその適用を限られるものでは
なく、例えばホットエレクトロントランジスタ、共鳴ホ
ットエレクトロントランジスタの高速化のためにそのベ
ース層に２次元電子ガスを用いる際に本発明を適用して
ベース抵抗を低減するなど、空間分離ドーピングと界面
量子化による高移動度のキャリアを用いる半導体装置全
般に適用することが可能である。Note that the present invention is not limited to application to IEMTs; for example, the present invention can be applied to the base layer of hot electron transistors and resonant hot electron transistors when a two-dimensional electron gas is used in their base layer to speed up the operation. It can be applied to all semiconductor devices that use high-mobility carriers through space separation doping and interface quantization, such as reducing resistance.
以上説明した如く本発明によれば、空間分離ドーピング
と界面量子化による高移動度のキャリアを利用するＲＥ
ＮＴ等の半導体装置において、ＧａＡｓ／ＡｌＡｓ超格
子構造の電子供給層に、２次元電子ガス面密度の低下、
シート抵抗の増大などの劣化をもたらす熱損傷を製造工
程中に与えることなく、良好な特性の半導体装置が実現
される。As explained above, according to the present invention, RE using high mobility carriers by spatially separated doping and interface quantization is achieved.
In semiconductor devices such as NTs, the electron supply layer of the GaAs/AlAs superlattice structure has a decrease in the two-dimensional electron gas surface density,
A semiconductor device with good characteristics can be realized without causing thermal damage that causes deterioration such as an increase in sheet resistance during the manufacturing process.
【図面の簡単な説明】
第１図はＨＥＭＴにかかる本発明の実施例の模式側断面
図、
第２図はＨＥＭＴの従来例の模式側断面図である。
図において、
１は半絶縁性ＧａＡｓ基板、
２はノンドープのＧａＡｓ層、
２ｅは２次元電子ガス、
３はＧａＡｓ／ＡｌＡｓ超格子構造、
３ａはｎ型ＧａＡｓ層、
３ｂはノンドープのＡｌＡｓ層、
４はｎ型ＩｎｘＧａ＋−Ｊｓ層、
５はＣｒ／Ａｕソース、ドレイン電極、６はＣｒ／Ａｕ
ゲート電極を示す。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic side sectional view of an embodiment of the present invention related to a HEMT, and FIG. 2 is a schematic side sectional view of a conventional HEMT. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a non-doped GaAs layer, 2e is a two-dimensional electron gas, 3 is a GaAs/AlAs superlattice structure, 3a is an n-type GaAs layer, 3b is a non-doped AlAs layer, 4 is a non-doped AlAs layer. n-type InxGa+-Js layer, 5 Cr/Au source, drain electrode, 6 Cr/Au
The gate electrode is shown.
Claims (1)
む砒化ガリウム層とノンドープの砒化アルミニウム層と
からなる超格子構造と、ドナー不純物を含む砒化インジ
ウムガリウム層とが積層されて、該ノンドープの砒化ガ
リウム層の該超格子構造との界面近傍に、該超格子構造
から遷移する電子により２次元電子ガスが形成され、 オーミックコンタクト電極が該砒化インジウムガリウム
層に接して配設されてなることを特徴とする半導体装置
。 ２）前記２次元電子ガスを制御するゲート電極が前記超
格子構造に接して配設され、かつ前記オーミックコンタ
クト電極と該ゲート電極とが共に半導体基体上にクロム
を被着し、該クロム層上に金を被着して形成されてなる
ことを特徴とする特許請求の範囲第１項記載の半導体装
置。[Scope of Claims] 1) A superlattice structure consisting of a non-doped gallium arsenide layer, a gallium arsenide layer containing donor impurities and a non-doped aluminum arsenide layer, and an indium gallium arsenide layer containing donor impurities are laminated, A two-dimensional electron gas is formed near the interface between the non-doped gallium arsenide layer and the superlattice structure by electrons transitioning from the superlattice structure, and an ohmic contact electrode is disposed in contact with the indium gallium arsenide layer. A semiconductor device characterized by: 2) A gate electrode for controlling the two-dimensional electron gas is disposed in contact with the superlattice structure, and both the ohmic contact electrode and the gate electrode deposit chromium on the semiconductor substrate, and the chromium layer is coated on the chromium layer. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed by depositing gold on the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5732686A JP2538872B2 (en) | 1986-03-14 | 1986-03-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5732686A JP2538872B2 (en) | 1986-03-14 | 1986-03-14 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62213279A true JPS62213279A (en) | 1987-09-19 |
| JP2538872B2 JP2538872B2 (en) | 1996-10-02 |
Family
ID=13052448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5732686A Expired - Lifetime JP2538872B2 (en) | 1986-03-14 | 1986-03-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2538872B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0349242A (en) * | 1989-07-17 | 1991-03-04 | Agency Of Ind Science & Technol | Field effect transistor and its manufacture |
| US5932890A (en) * | 1992-05-08 | 1999-08-03 | The Furukawa Electric Co., Ltd. | Field effect transistor loaded with multiquantum barrier |
| US6262444B1 (en) | 1997-04-23 | 2001-07-17 | Nec Corporation | Field-effect semiconductor device with a recess profile |
| JP2003060300A (en) * | 2001-08-14 | 2003-02-28 | Furukawa Electric Co Ltd:The | Surface emitting laser and array thereof |
| US7692298B2 (en) * | 2004-09-30 | 2010-04-06 | Sanken Electric Co., Ltd. | III-V nitride semiconductor device comprising a concave shottky contact and an ohmic contact |
| CN114005866A (en) * | 2021-09-13 | 2022-02-01 | 西安电子科技大学广州研究院 | GaN high-electron-mobility heterojunction structure, preparation method, diode and transistor |
-
1986
- 1986-03-14 JP JP5732686A patent/JP2538872B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0349242A (en) * | 1989-07-17 | 1991-03-04 | Agency Of Ind Science & Technol | Field effect transistor and its manufacture |
| US5932890A (en) * | 1992-05-08 | 1999-08-03 | The Furukawa Electric Co., Ltd. | Field effect transistor loaded with multiquantum barrier |
| US6262444B1 (en) | 1997-04-23 | 2001-07-17 | Nec Corporation | Field-effect semiconductor device with a recess profile |
| JP2003060300A (en) * | 2001-08-14 | 2003-02-28 | Furukawa Electric Co Ltd:The | Surface emitting laser and array thereof |
| US7692298B2 (en) * | 2004-09-30 | 2010-04-06 | Sanken Electric Co., Ltd. | III-V nitride semiconductor device comprising a concave shottky contact and an ohmic contact |
| CN114005866A (en) * | 2021-09-13 | 2022-02-01 | 西安电子科技大学广州研究院 | GaN high-electron-mobility heterojunction structure, preparation method, diode and transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2538872B2 (en) | 1996-10-02 |
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