JP2538872B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2538872B2
JP2538872B2 JP5732686A JP5732686A JP2538872B2 JP 2538872 B2 JP2538872 B2 JP 2538872B2 JP 5732686 A JP5732686 A JP 5732686A JP 5732686 A JP5732686 A JP 5732686A JP 2538872 B2 JP2538872 B2 JP 2538872B2
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JP
Japan
Prior art keywords
layer
electrode
gaas
semiconductor device
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP5732686A
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Japanese (ja)
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JPS62213279A (en
Inventor
健一 今村
和明 石井
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Fujitsu Ltd
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Fujitsu Ltd
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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/452Ohmic electrodes on AIII-BV compounds

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 〔概要〕 この発明は、砒化ガリウム/砒化アルミニウム超格子
構造から供給される2次元電子ガスをチャネルとする半
導体装置にかかり、 オーミックコンタクト電極を砒化インジウムガリウム
層に接して配設することにより、 合金化熱処理を行うことなく良好なコンタクトを得
て、電子密度の低下等の熱劣化を防止するものである。
The present invention relates to a semiconductor device having a channel of a two-dimensional electron gas supplied from a gallium arsenide / aluminum arsenide superlattice structure, in which an ohmic contact electrode is in contact with an indium gallium arsenide layer. By arranging them, good contact can be obtained without performing alloying heat treatment, and thermal deterioration such as decrease in electron density can be prevented.

〔産業上の利用分野〕[Industrial applications]

本発明は半導体装置、特に空間分離ドーピングと界面
量子化による高移動度のキャリアをチャネルとする例え
ば高電子移動度電界効果トランジスタ(HEMT)等の半導
体装置の改善に関する。
The present invention relates to a semiconductor device, and more particularly, to improvement of a semiconductor device such as a high electron mobility field effect transistor (HEMT) which uses a carrier having high mobility by space separation doping and interface quantization as a channel.

例えばHEMTは、ノンドープの砒化ガリウム(GaAs)層
とn型砒化アルミニウムガリウム(AlGaAs)層等のヘテ
ロ接合界面近傍に2次元状態の電子を形成し、不純物を
ドーピングする領域とキヤリアが移動する領域とを空間
的に分離してキヤリア移動度を増大し、高速デバイスと
して強い期待が寄せられている。
For example, HEMT forms two-dimensional electrons in the vicinity of a heterojunction interface such as a non-doped gallium arsenide (GaAs) layer and an n-type aluminum gallium arsenide (AlGaAs) layer, and an impurity doping region and a carrier moving region are formed. These are spatially separated to increase carrier mobility, and high expectations are placed on them as high-speed devices.

〔従来の技術〕[Conventional technology]

空間分離ドーピングのキャリアの界面量子化により高
移動度を実現している半導体装置の例として、HEMTの一
例の模式側断面図を第2図(a)、(b)に示す。
2A and 2B are schematic side sectional views of an example of a HEMT as an example of a semiconductor device that realizes high mobility by interfacial quantization of carriers in space separation doping.

同図(a)に示すHEMTの従来例では、半絶縁性GaAs基
板11上にノンドープのi形GaAs層12と、これより電子親
和力が小さく例えば濃度2×1018cm-3程度のドナー不純
物がドープされたn型AlxGa1-xAs層13と、これと同程度
以上にドナー不純物がドープされたn型GaAs層14とが設
けられ、n型AlGaAs層13からi形GaAs層12へ遷移した電
子によってヘテロ接合界面近傍に2次元電子ガス12eが
形成される。この2次元電子ガス12eは不純物散乱によ
る移動度低下が殆どなく、格子散乱が低下する例えば77
K程度以下の低温において最も高い移動度が得られる。
In the conventional HEMT example shown in FIG. 1A, a non-doped i-type GaAs layer 12 and a donor impurity having a lower electron affinity, for example, a concentration of about 2 × 10 18 cm −3 are provided on a semi-insulating GaAs substrate 11. A doped n-type Al x Ga 1-x As layer 13 and an n-type GaAs layer 14 doped with a donor impurity to the same extent or more are provided to convert the n-type AlGaAs layer 13 to the i-type GaAs layer 12. A two-dimensional electron gas 12e is formed near the heterojunction interface by the transitioned electrons. This two-dimensional electron gas 12e has almost no mobility decrease due to impurity scattering, and lattice scattering decreases, for example, 77
Highest mobility is obtained at low temperature below K.

この半導体基板のn型GaAs層14上にソース、ドレイン
電極15を例えば金ゲルマニウム/金(AuGe/Au)を用
い、n型AlGaAs電子供給層13上にゲート電極16を例えば
チタン/白金/金(Ti/Pt/Au)を用いて設け、ゲート電
極16によるショットキ空乏層で2次元電子ガス12eの面
密度を制御してトランジスタ動作が行われる。なお15A
はソース、ドレイン電極15と半導体基体との間に形成さ
れた合金化領域である。
For example, gold germanium / gold (AuGe / Au) is used as the source / drain electrode 15 on the n-type GaAs layer 14 of this semiconductor substrate, and the gate electrode 16 is made of, for example, titanium / platinum / gold (AuGe / Au) on the n-type AlGaAs electron supply layer 13. Ti / Pt / Au) is used, and the Schottky depletion layer by the gate electrode 16 controls the areal density of the two-dimensional electron gas 12e to perform the transistor operation. 15A
Is an alloyed region formed between the source / drain electrodes 15 and the semiconductor substrate.

この構造のn型AlxGa1-xAs電子供給料13とi型GaAsチ
ャネル層12との伝導帯のエネルギー準位差が少ない場合
には2次元電子ガス12eの面密度Nsが小さくなるため
に、通常伝導帯の準位差を0.25eV程度以上、従ってn型
AlxGa1-xAs電子供給層13のAl組成比xを0.3程度以上と
することが望ましい。
If the energy level difference of the conduction band between the n-type Al x Ga 1-x As electron supply material 13 and the i-type GaAs channel layer 12 of this structure is small, the surface density Ns of the two-dimensional electron gas 12e becomes small. The normal conduction band level difference is about 0.25 eV,
It is preferable that the Al composition ratio x of the Al x Ga 1-x As electron supply layer 13 is about 0.3 or more.

しかしながら他方において、AlxGa1-xAs混晶のAl組成
比xが0.25程度より大きいときには、ドープしたシリコ
ン(Si)等のドナー準位が急激に深くなる。この深いド
ナー準位は、200K程度以下で赤外線が入射すれば電子が
伝導帯に励起され、光照射を停止しても伝導電子がドナ
ー準位に落ちないPPC(persistent photo conductivit
y)等の現象を示してDXセンターと呼ばれるが、これに
より、ドーピング量を増加しても高いキャリア濃度が得
られず、特に低温における2次元電子ガス面密度Nsの低
下、従って伝達コンダクタンスgmの低下を招いている。
また光が入射したり、ホットエレクトロンがチャネルか
らAlGaAs層に飛び込むことにより、2次元電子ガス面密
度Ns、電子移動度μ及び閾値電圧Vth等が変動する現
象が現れ、低周波雑音の原因ともなっている。
On the other hand, however, when the Al composition ratio x of the Al x Ga 1-x As mixed crystal is larger than about 0.25, the donor level of doped silicon (Si) or the like suddenly deepens. In this deep donor level, electrons are excited to the conduction band when infrared rays are incident at about 200 K or less, and conduction electrons do not fall to the donor level even if light irradiation is stopped. PPC (persistent photo conductivit)
y) and other phenomena are called DX centers, but due to this, even if the doping amount is increased, a high carrier concentration cannot be obtained, and in particular, the two-dimensional electron gas areal density Ns decreases at low temperatures, and therefore the transfer conductance g m Has caused a decline in.
In addition, when light enters or hot electrons jump from the channel into the AlGaAs layer, the phenomenon that the two-dimensional electron gas surface density Ns, electron mobility μ n, threshold voltage V th, etc. fluctuates appears, causing low frequency noise. It is also accompanied.

このAlGaAs混晶内の深いドナー準位に起因する問題に
対処するものとして第2図(b)に示す従来例がある。
本従来例では前記従来例のn型AlxGa1-xAs層13に代え
て、電子供給層をGaAs層23aとAlAs層23bとからなる格子
構造23とし、GaAs層23aに例えば濃度5×1018cm-3程度
にドナー不純物をドーピングし、AlAs層23bはノンドー
プとしている。
There is a conventional example shown in FIG. 2 (b) for dealing with the problem caused by the deep donor level in the AlGaAs mixed crystal.
In this conventional example, instead of the n-type Al x Ga 1-x As layer 13 of the conventional example, the electron supply layer has a lattice structure 23 composed of a GaAs layer 23a and an AlAs layer 23b, and the GaAs layer 23a has, for example, a concentration of 5 ×. The donor impurity is doped to about 10 18 cm −3 , and the AlAs layer 23b is undoped.

この改善により、AlGaAs混晶層を電子供給層とするHE
MTが、例えば温度77Kにおいて電子移動度μ≒1×105
cm2/V.s、2次元電子ガス面密度Ns≒1.2×1011cm-2程度
であるのに対して、GaAs/AlAs超格子構造を電子供給層
とする同等のHEMTは、2次元電子ガス面密度Ns≒3.0×1
011cm-2程度が同等の電子移動度μで得られ、閾値電
圧Vthの変動等の問題も改善されると報告されている。
With this improvement, HE that uses AlGaAs mixed crystal layer as electron supply layer
MT has an electron mobility μ n ≈1 × 10 5 at a temperature of 77 K, for example.
cm 2 / Vs, two-dimensional electron gas areal density Ns ≈ 1.2 × 10 11 cm -2 , while the equivalent HEMT using a GaAs / AlAs superlattice structure as an electron supply layer has a two-dimensional electron gas surface Density Ns≈3.0 × 1
It is reported that about 0 11 cm -2 is obtained with an equivalent electron mobility μ n , and problems such as fluctuations in the threshold voltage V th are improved.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上述の如くGaAs/AlAs超格子構造によりAlGaAs混晶に
おける深いドナー準位に起因する問題が改善されるが、
HEMT素子を実際に完成した状態では、エピタキシャル成
長直後の半導体基体に比較して、2次元電子ガス面密度
Nsの低下、従ってシート抵抗の増大などの劣化を屡生ず
る。
As mentioned above, the GaAs / AlAs superlattice structure improves the problem caused by the deep donor level in the AlGaAs mixed crystal.
When the HEMT device is actually completed, the two-dimensional electron gas areal density is higher than that of the semiconductor substrate immediately after epitaxial growth.
Deterioration such as a decrease in Ns and therefore an increase in sheet resistance often occurs.

製造プロセス中のこの劣化の最大要因は熱処理であ
る。すなわちn型GaAs層14上にオーミックコンタクト電
極材料として、例えば金ゲルマニウム合金(AuGe)を厚
さ20mm、金(Au)を厚さ280mm程度積層被着、パターニ
ングし、温度450℃、1分間程度の熱処理により電極材
料と半導体基体とを合金化して、ソース、ドレイン電極
15のオーミックコンタクト抵抗を低減しているが、この
熱処理の過程でGaAs層23aにドープしたSiの拡散などに
より超格子構造に損傷を生じている。
The largest contributor to this degradation during the manufacturing process is heat treatment. That is, as the ohmic contact electrode material, for example, gold germanium alloy (AuGe) with a thickness of 20 mm and gold (Au) with a thickness of 280 mm are laminated and deposited on the n-type GaAs layer 14 and patterned, and the temperature is 450 ° C. for about 1 minute. Source and drain electrodes are formed by alloying the electrode material and semiconductor substrate by heat treatment.
Although the ohmic contact resistance of 15 is reduced, the superlattice structure is damaged by the diffusion of Si doped in the GaAs layer 23a during the heat treatment.

HEMT等の界面量子化されたキャリアを利用する半導体
装置のキャリア増大は重要な課題であり、その効果を損
なう要因の排除が強く要望されている。
Increasing the number of carriers in a semiconductor device that uses interface quantized carriers such as HEMT is an important issue, and elimination of factors that impair its effect is strongly desired.

〔問題点を解決するための手段〕[Means for solving problems]

前記問題点は、砒化ガリウム層からなるチャネル層
と、該チャネル層上に形成された、ノンドープの砒化ア
ルミニウム層とn型砒化ガリウム層とが交互に積層され
た超格子構造を有する電子供給層と、該電子供給層上に
設けられたゲート電極と、該ゲート電極の両側において
該電子供給層上に、n型砒化インジウムガリウム層を介
してそれぞれ設けられたソース及びドレイン電極とを有
し、該ソース電極、ドレイン電極及びゲート電極は同一
工程によりノンアロイで形成された同一電極材料からな
る本発明による半導体装置により解決される。
The problem is that a channel layer made of a gallium arsenide layer and an electron supply layer having a superlattice structure in which a non-doped aluminum arsenide layer and an n-type gallium arsenide layer formed alternately are formed on the channel layer. A gate electrode provided on the electron supply layer, and source and drain electrodes provided on both sides of the gate electrode on the electron supply layer via an n-type indium gallium arsenide layer, respectively. The source electrode, the drain electrode and the gate electrode can be solved by the semiconductor device according to the present invention, which is made of the same electrode material and formed of non-alloy in the same process.

〔作 用〕[Work]

本発明によれば、ドナー不純物を含むGaAs層とノンド
ープのAlAs層とからなる超格子構造から電子が遷移し
て、ノンドープのGaAs層の該超格子構造との界面近傍に
2次元電子ガスが形成される半導体装置において、その
オーミックコンタクト電極をドナー不純物を含むInxGa
1-xAs層に接して配設する。
According to the present invention, electrons transition from a superlattice structure composed of a GaAs layer containing a donor impurity and a non-doped AlAs layer, and a two-dimensional electron gas is formed in the vicinity of the interface between the non-doped GaAs layer and the superlattice structure. In a semiconductor device to be used, its ohmic contact electrode is made of In x Ga containing a donor impurity.
It is placed in contact with the 1-x As layer.

InxGa1-xAs混晶はGaAs結晶よりエネルギーバンドギャ
ップEgが狭く、GaAsのEg≒1.42eVに対して例えばIn0.5G
a0.5AsはEg≒0.76eVであり、合金化熱処理を行わないで
低抵抗のオーミックコンタクトを得ることができる。
The energy band gap Eg of In x Ga 1-x As mixed crystal is narrower than that of GaAs crystal, and for example, In 0.5 G for Eg ≈ 1.42 eV.
Since a 0.5 As is Eg≈0.76 eV, a low resistance ohmic contact can be obtained without performing alloying heat treatment.

この電極材料としては例えばクロム/金(Cr/Au)が
適しており、この電極材料でInxGa1-xAs混晶層にオーミ
ックコンタクトするソース、ドレイン電極と、GaAs/AlA
s超格子構造にショットキコンタクトするゲート電極と
を同時に形成することも可能である。
Chromium / gold (Cr / Au), for example, is suitable as this electrode material. With this electrode material, the source and drain electrodes that make ohmic contact with the In x Ga 1-x As mixed crystal layer, and GaAs / AlA
s It is also possible to simultaneously form a gate electrode that is in Schottky contact with the superlattice structure.

〔実施例〕〔Example〕

以下本発明を実施例により具体的に説明する。 Hereinafter, the present invention will be described specifically with reference to Examples.

第1図はHEMTにかかる本発明の実施例を示す模式側断
面図である。
FIG. 1 is a schematic side sectional view showing an embodiment of the present invention related to HEMT.

本実施例の半導体基体は分子線エピタキシャル成長法
(MBE法)等により、半絶縁性GaAs基板1上に、厚さ例
えば1μm程度のノンドープのi型GaAs層2、例えば濃
度5×1018cm-3程度にSiをドープして厚さ5mm程度のn
型GaAs層3aとトンドープで厚さ例えば2mm程度のi型AlA
s層3bとの7周期からなるGaAs/AlAs超格子構造3、例え
ば厚さ約5nmの範囲でGaAsからIn0.5Ga0.5Asまで次第に
インジウム(In)の組成比を増加し全厚さ100〜200nm程
度で、濃度1×1019cm-3程度にSiをドープしたn型InGa
As層4を順次成長している。この半導体基体のi型GaAs
層2のGaAs/AlAs超格子構造3との界面近傍に2次元電
子ガス2eが形成される。この半導体基体のゲート形成領
域をリセスエッチングし、電極材料層としてCr約50m、A
u約300nmを積層して、ソース、ドレイン電極5、ゲート
電極6を同時に形成している。なお合金化領域を形成す
る熱処理は実施しない。
The semiconductor substrate of this embodiment is formed by a molecular beam epitaxial growth method (MBE method) or the like on a semi-insulating GaAs substrate 1, a non-doped i-type GaAs layer 2 having a thickness of, for example, about 1 μm, for example, a concentration of 5 × 10 18 cm −3. N with a thickness of about 5 mm after being doped with Si
I-type AlA with a thickness of, for example, about 2 mm, which is doped with the ton-type GaAs layer 3a
GaAs / AlAs superlattice structure 3 consisting of 7 cycles with s layer 3b, for example, the composition ratio of indium (In) is gradually increased from GaAs to In 0.5 Ga 0.5 As in the thickness range of about 5 nm, and the total thickness is 100 to 200 nm. N-type InGa doped with Si at a concentration of about 1 × 10 19 cm -3
As layer 4 is growing in sequence. I-type GaAs of this semiconductor substrate
A two-dimensional electron gas 2e is formed near the interface of the layer 2 with the GaAs / AlAs superlattice structure 3. The gate formation region of this semiconductor substrate was recess-etched to form an electrode material layer of about 50 m Cr, A
A source / drain electrode 5 and a gate electrode 6 are simultaneously formed by laminating about 300 nm. The heat treatment for forming the alloyed region is not performed.

本実施例では、エピタキシャル成長直後に例えば温度
77Kにおいて電子移動度μ≒1×105cm2/V.s、2次元
電子ガス面密度Ns≒3.0×1011cm-2程度である半導体基
体を用いて、HEMT素子完成後に同温度において有意差の
ない2次元電子ガス面密度Nsが得られ、同一半導体基体
にオーミック電極材料としてAuGe/Auを用い、温度450
℃、1分間程度の合金化熱処理を実施した比較試料が、
2次元電子ガス面密度Ns≒1.2×1011cm-2程度であるの
に比較して本発明の効果が実証されている。
In this example, immediately after the epitaxial growth, for example, the temperature
At 77 K, electron mobility μ n ≈ 1 × 10 5 cm 2 / Vs, using a semiconductor substrate with a two-dimensional electron gas surface density Ns ≈ 3.0 × 10 11 cm -2 , there is a significant difference at the same temperature after the HEMT device is completed. A two-dimensional electron gas areal density Ns is obtained, and AuGe / Au is used as the ohmic electrode material on the same semiconductor substrate at a temperature of 450
The comparative sample, which has been subjected to alloying heat treatment at about 1 ° C for 1 minute,
The effect of the present invention is proved in comparison with the two-dimensional electron gas areal density Ns≈1.2 × 10 11 cm −2 .

なお本発明はHEMTにその適用を限られるものではな
く、例えばホットエレクトロントランジスタ、共鳴ホッ
トエレクトロントランジスタの高速化のためにそのベー
ス層に2次元電子ガスを用いる際に本発明を適用してベ
ース抵抗を低減するなど、空間分離ドーピングと界面量
子化による高移動度のキャリアを用いる半導体装置全般
に適用することが可能である。
The application of the present invention is not limited to HEMTs. For example, when a two-dimensional electron gas is used for the base layer of a hot electron transistor or a resonant hot electron transistor to increase the speed, the present invention is applied to the base resistance. The present invention can be applied to all semiconductor devices using high mobility carriers due to space separation doping and interface quantization.

〔発明の効果〕〔The invention's effect〕

以上説明した如く本発明によれば、空間分離ドーピン
グと界面量子化による高移動度のキャリアを利用するHE
MT等の半導体装置において、GaAs/AlAs超格子構造の電
子供給層に、2次元電子ガス面密度の低下、シート抵抗
の増大などの劣化をもたらす熱損傷を製造工程中に与え
ることなく、良好な特性の半導体装置が実現される。
As described above, according to the present invention, HE that utilizes high mobility carriers by space separation doping and interface quantization
In a semiconductor device such as MT, the electron supply layer of the GaAs / AlAs superlattice structure is provided with good heat resistance during the manufacturing process without causing thermal damage that causes deterioration such as a decrease in two-dimensional electron gas surface density and an increase in sheet resistance. A characteristic semiconductor device is realized.

【図面の簡単な説明】[Brief description of drawings]

第1図はHEMTにかかる本発明の実施例の模式側断面図、 第2図はHEMTの従来例の模式側断面図である。 図において、 1は半絶縁性GaAs基板、 2はノンドープのGaAs層、 2eは2次元電子ガス、 3はGaAs/AlAs超格子構造、 3aはn型GaAs層、 3bはノンドープのAlAs層、 4はn型InxGa1-xAs層、 5はCr/Auソース、ドレイン電極、 6はCr/Auゲート電極を示す。FIG. 1 is a schematic side sectional view of an embodiment of the present invention related to HEMT, and FIG. 2 is a schematic side sectional view of a conventional example of HEMT. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a non-doped GaAs layer, 2e is a two-dimensional electron gas, 3 is a GaAs / AlAs superlattice structure, 3a is an n-type GaAs layer, 3b is a non-doped AlAs layer, and 4 is n-type In x Ga 1-x As layer, 5 is a Cr / Au source / drain electrode, and 6 is a Cr / Au gate electrode.

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】砒化ガリウム層からなるチャネル層と、 該チャネル層上に形成された、ノンドープの砒化アルミ
ニウム層とn型砒化ガリウム層とが交互に積層された超
格子構造を有する電子供給層と、 該電子供給層上に設けられたゲート電極と、 該ゲート電極の両側において該電子供給層上に、n型砒
化インジウムガリウム層を介してそれぞれ設けられたソ
ース及びドレイン電極とを有し、 該ソース電極、ドレイン電極及びゲート電極は同一工程
によりノンアロイで形成された同一電極材料からなるこ
とを特徴とする半導体装置。
1. A channel layer made of a gallium arsenide layer, and an electron supply layer having a superlattice structure formed on the channel layer, in which a non-doped aluminum arsenide layer and an n-type gallium arsenide layer are alternately laminated. A gate electrode provided on the electron supply layer, and source and drain electrodes provided on both sides of the gate electrode on the electron supply layer via an n-type indium gallium arsenide layer, respectively. A semiconductor device, wherein the source electrode, the drain electrode, and the gate electrode are made of the same electrode material formed in a non-alloy by the same process.
【請求項2】前記ソース電極、ドレイン電極及びゲート
電極は、クロム及び金からなることを特徴とする特許請
求の範囲第1項記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the source electrode, the drain electrode and the gate electrode are made of chromium and gold.
JP5732686A 1986-03-14 1986-03-14 Semiconductor device Expired - Lifetime JP2538872B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5732686A JP2538872B2 (en) 1986-03-14 1986-03-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5732686A JP2538872B2 (en) 1986-03-14 1986-03-14 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS62213279A JPS62213279A (en) 1987-09-19
JP2538872B2 true JP2538872B2 (en) 1996-10-02

Family

ID=13052448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5732686A Expired - Lifetime JP2538872B2 (en) 1986-03-14 1986-03-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2538872B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2548801B2 (en) * 1989-07-17 1996-10-30 工業技術院長 Field effect transistor and method of manufacturing the same
US5932890A (en) * 1992-05-08 1999-08-03 The Furukawa Electric Co., Ltd. Field effect transistor loaded with multiquantum barrier
US6262444B1 (en) 1997-04-23 2001-07-17 Nec Corporation Field-effect semiconductor device with a recess profile
JP2003060300A (en) * 2001-08-14 2003-02-28 Furukawa Electric Co Ltd:The Surface emitting laser and array thereof
US7692298B2 (en) * 2004-09-30 2010-04-06 Sanken Electric Co., Ltd. III-V nitride semiconductor device comprising a concave shottky contact and an ohmic contact
CN114005866A (en) * 2021-09-13 2022-02-01 西安电子科技大学广州研究院 GaN high-electron-mobility heterojunction structure, preparation method, diode and transistor

Also Published As

Publication number Publication date
JPS62213279A (en) 1987-09-19

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