JPS6221326A - Phase control circuit - Google Patents

Abstract

PURPOSE:To attain phase control independently of a pulse width of a comparison signal by providing a circuit keeping phase information relating to a reference signal and the comparison signal during the control period. CONSTITUTION:A comparison signal NCK formed from a 1/N frequency divider 18 is inputted to a D-FF 15 as a clock and a reference signal (f) is inputted to a D-FF 15 as a data. An output Q of the D-FF 15 is the phase information between the reference signal (f) and the comparison signal NCK and inputted to a NAND gate 16. On the other hand, a differentiation circuit 14 differentiates the leading of the reference signal (f) to generate a differentiation pulse, which is inputted to the NAND gate 16 and the pulse is ANDed with the phase information from the D-FF 15, the result is inputted to an AND gate 17 as the phase control signal to apply phase control. Thus, the phase control is attained independently of the pulse width of the comparison signal NCK.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This is a digital phase control circuit that makes it possible to supply phase information between a reference signal and a comparison signal regardless of the pulse width of the comparison signal.

[Industrial application field]

The present invention relates to a digital phase control circuit, and particularly to a phase control method for matching the phases of a reference signal and a comparison signal regardless of the pulse width of the comparison signal.

[Conventional technology]

In a system consisting of a master station and multiple slave stations connected by a transmission line, the system must operate in synchronization with all clocks output from the master station. When sending data from a master station to, for example, a first slave station, only the data is sent without sending a clock. At that time, data is received at the slave station, but the phase may shift due to disturbances in the transmission path.

When the data rate is, for example, 64K112, the slave station has an oscillator that creates a 64KHz clock for data sampling, and samples the data in the middle. Even if 64KHz data is transmitted and this oscillator creates a 64KHz clock, it will not be possible to create a clock with exactly the same frequency due to the accuracy of the oscillator. Therefore, by using the pinch when the data rises from 0 to 1 and detecting the rising pitch, in other words, by detecting the phase change point and converting the 64Kt (z clock to the data clock) generated by itself. Match.

A digital phase control circuit is a circuit that performs such phase control.

An example of the prior art is shown in the circuit diagram of FIG.
The phase change of f) is detected by rising differentiation, the phase position of the comparison signal (NCK) at this time is treated as phase information, and phase control is performed based on the differential pulse and this phase information.The time chart is as follows. It is shown in FIG.

In FIG. 3, 31 is an oscillator, 32 is a 0-phase and π-phase generation circuit, 33 is a selector, 34 is an AND gate, 35 is a rising differentiation circuit, 36 is a flip-flop, and 37 is an N
ANO gate, 38 indicates a 1/N frequency divider, selector 33
Then, the rising edge of the reference signal of the input signal (data) is differentiated and detected, and 0 and 1 signals are output.

In the time chart of Figure 4, the 0 phase clock (CK
) and π-phase rofuku are just 180 degrees out of phase, but the frequencies are the same. A differentiation circuit detects the rise of the reference signal f and oscillates a d/dt differential pulse, and when the comparison signal (NCK) is leading, a solid line pulse is obtained, and when it is lagging, a dotted line pulse is obtained. In that case, the selector output becomes one with one tooth added as shown in the figure, and NANDA
In the case of ND output NCR lead, the solid line becomes the dotted line pulse in the case of NCR delay, and the AND output delays the phase in the case of NC lead, and advances the phase in the case of NCR delay.

[Problem that the invention seeks to solve]

The method shown in FIG. 3 has the disadvantage that there is a limit to the pulse width of the comparison signal in order to obtain a phase relationship with the comparison signal when the reference signal (f) changes phase. Referring to the time chart in Fig. 5, if the pulse width of the comparison signal NC is small, the inhibit signal shown by the dotted line is not created even though the comparison signal NCR is in an advanced state due to the NAND output, and the AND output is in phase. There is a problem with controlling the progress of the process.

The present invention was created in view of the above points, and an object of the present invention is to provide a digital phase control circuit that can supply phase information between a reference signal and a comparison signal regardless of the pulse width of the comparison signal. shall be.

[Means for solving problems]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a time chart of the embodiment of FIG.

In a digital phase control circuit that synchronizes a reference signal f and a comparison signal NC shown in FIG. 1, a circuit 1 that holds phase information of a reference signal f and a comparison signal NCK during a control period.
5 is provided, and the comparison signal NCK generated by the frequency divider 18
A phase control circuit that can perform phase control regardless of the pulse width is obtained.

[Effect]

The present invention utilizes the data holding function of a flip-flop (D-FF) to generate phase information by operating the flip-flop using the reference signal f as data and the comparison signal NCK as a clock. .

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows a time chart of the embodiment.

The configuration of the circuit shown in FIG.
Circuit 12 that creates phase-shifted 0-phase and π-phase clocks
, a selector 13 that repeatedly selects these two clocks based on the rising edge information of the reference signal, a differentiation circuit 14 that differentiates the rising edge of the reference signal f, and a comparison circuit 14 that differentiates the rising edge of the reference signal f from the phase information of the reference signal f at the rising edge of the signal. It consists of a flip-flop (D-FF) 15, a NAND gate 16, and an AND gate 17.

The comparison signal NCK created by the 1/N frequency divider 18 is D
-The reference signal f is input as a clock to the FF 15, and the reference signal f is input as data to the D-FF 15. The Q output of the D-FF 15 is phase information of the reference signal f and the comparison signal NCK, and is input to the NAND gate 16. On the other hand, differentiator circuit 1
Step 4 differentiates the rising edge of the reference signal f, creates a differential pulse, inputs it to the NANO gate 16, performs an AND with the phase information from the D-FF 15, and manually inputs this to the AND gate 17 as a phase control signal. , performs phase control. In addition,
The D-FF 15a is the same as the flip-flop 36 of the conventional example.

According to an embodiment of the present invention, the phase information signal is created using the pulse width of the comparison signal NCH (the comparison signal NCK is used as the clock of D-Fl'15, and the reference signal f is used as the data). This has the effect that phase control can be performed regardless of the pulse width of the comparison signal NCH.

FIG. 2 is a time chart of the embodiment shown in FIG. 1, and even when the pulse width of the comparison signal NCH is small, the rising edge is N
It appears in the AND output as shown in the figure, and the advance state of the comparison signal NCK is judged by the output of Q of the D-FF 15, and control is in effect to delay the phase by skipping one clock at the NO output as shown by the dotted line. Show that. In this way,
Since the phase of the comparison signal NCK is controlled in each slave station, even if data enters the slave station, it will not be detected (slip), and synchronization of the entire system (network synchronization) will be achieved.

〔Effect of the invention〕

As described above, according to the present invention, phase control can be performed without limiting the pulse width of the comparison signal, so it is effective as a general-purpose digital phase control.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an embodiment of the present invention.
Fig. 3 is a circuit diagram of the conventional synchronous circuit, Fig. 4 is a time chart of the circuit of Fig. 3, and Fig. 5 is a circuit diagram of the conventional synchronous circuit.
3 is a time chart showing a problem in the example shown in the figure. In Fig. 1, 11 is an oscillator, 12 is a 0-phase and π-phase generation circuit, 13 is a selector, 14 is a rising differential circuit, 15 and 15a are 7 resop flops (D-FF), 16 is a NAND gate, and 17 is an AND Gate 18 is a 1/N frequency divider. Uninvented literary materials Figure 1 Owa C and CK
-1 "l Ipponkin IIM Sarayashu I f'J's Fuimuna Y-'r-4 [Toi FIJ Iya 211]j
Tsukasa Ibu 1 time S45・O phase CK v#1c to Tani [Made 11th Time Naya F Fig. 4 Conventional 4F bow! ,"+4 ,!," is not T9 imsa ↑-to Figure 5

Claims (1)

[Claims] In a digital phase control circuit that synchronizes a reference signal and a comparison signal, a circuit (15) is provided that holds phase information of the reference signal (f) and comparison signal (NCK) during a control period, and Circulator (18)
1. A phase control circuit characterized in that phase control can be executed regardless of the pulse width of a comparison signal (NCK) generated from.