JPS62211746A - Memory reading system - Google Patents

Abstract

PURPOSE:To speed up memory reading by constituting all registers excepting an address register as shift buses and renewing the content of the address register at every completion of reading of unit word. CONSTITUTION:At the time of reading all data in a scratch-pad memory 3, SM signals 107 are outputted from a service processor 10, and all registers in a CPU 1 become shift mode, and the contents of all registers are read out to the processor 10. After this, 0 is written in an address register 4 and a selector 8 connects all registers excepting the address register 4 with a shift bus, and loads the content of 0 address of the memory 3 in a read register, and the acontent is read out successively to the processor 10. In the meantime, the content of the address register 4 is renewed to 1, and the content of the memory 3 is read out to the processor 10 next. Thereafter, the operation is repeated.

Description

[Detailed description of the invention] Aoi! BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory read method, and particularly to a memory read method for reading the internal state of a data processing device to an external device when an error occurs.

Traditionally, when an error occurs in a data processing device, processing such as command retry is performed after immediately stopping data processing and reading the internal state to an external device (for example, a service processor). .

Broadly speaking, there are two methods for reading out the internal state to an external device.

One is to provide a one or more byte memory read-only data bus, and read out the memory contents sequentially by appropriately switching data using a selector. In this method, since multiple bits of data are read at a time, it is possible to read data at high speed, but it has disadvantages such as an increase in hardware and complexity of control.

Another method is to connect all the registers inside the data processing device in series (hereinafter, this connection bus will be referred to as a shift bus), and operate these registers as a shift register during reading. The internal state is read out one bit at a time every clock. Although the reading speed is slightly lower in this method, the amount of hardware does not increase significantly and the control is relatively simple. On the other hand, in this method, in order to read the contents of a storage element that does not have a shift bus, such as a memory element, the contents must be read into the -H register and then read using the shift bus. Before reading, the memory address must first be set in the address register using a shift bus.

Therefore, in order to read the contents of memory using the shift bus, it is necessary to set the address using the shift bus and read the contents of the memory at least as many times as the number of words in the memory. The disadvantage is that it takes much more time.

An object of the present invention is to configure all registers except the address register as a shift bus, update the contents of the address register every time a unit word is read by the shift bus, and transfer the address to the address register. It is an object of the present invention to provide a memory read method that automatically performs settings and speeds up memory read time.

According to the present invention, a memory, a read register for setting read contents of the memory, an address register for holding the address of the memory, and other registers including the read register are connected in series. A memory read method in a data processing device, wherein the data processing device has a data shift bus, and reads data set in the read register to the outside by operating a register constituting the data shift bus as a shift register. mode command means for commanding a memory read mode for reading out the memory and a shift mode for shifting data on the data shift bus; a specific value is added to the memory, and the contents of the address specified by the address register of the memory are set in the read register, and in the memory read mode and the shift mode,
and a control means for controlling all registers other than the address register to be connected in series to shift data as the data shift path, and by repeatedly reading out the contents of the read register using the data shift bus, the memory contents can be changed. A memory read method is obtained which is characterized in that the data is read out to the outside.

Kl1 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a data processing device showing an embodiment of the present invention. In FIG. 1, a CPU 1 includes an arithmetic processing unit 2 that executes instructions, a scratchpad memory 3 that stores data and control information used by this arithmetic processing unit 2, and holds read and write addresses of the scratchpad memory 3. Address register 4, read register 5 for setting read data of scratch pad memory 3, adder 6 for adding 1 to the contents of address register 4, selector 7 for switching input data of address register 4, shift buses 101 and 102 It is composed of a selector 8 for switching the data, and a control circuit 9 for reading out the scratch pad memory 3 at high speed.

The service processor 10 is a device that performs CPU diagnostic control, reading internal information, clock supply, and the like. Between the service processor 10 and the CPU 1 are shift paths 101 and 105, a shift mode signal 107 that instructs to perform a shift operation, and a memory read mode signal 108 that instructs the service processor 10 to read the contents of the scratchpad memory 3. , a clock 106 and other interface signals not shown.

A keyboard 11 and a printer 12 are connected to the service processor 10, and the operator can use these to issue instructions to read the internal state of the CPU 1, display read data, and the like.

FIG. 2 is a circuit example of the control circuit 9, and the read register 5
The write instruction (microinstruction) 114 of the inverter 13
Through this, ANDGATE 14 is a one-man operation. The write instruction (microinstruction) 113 of the address register 4 is handled by the Nantes gate 15, and the shift mode (SM>107 and memory mode 10B) from the service processor 10 is input to the gates 18 and 19, respectively. The positive output and the inverted output of the gates 18 and 19 become the two outputs of the AND gate 20, and its output 112 becomes the shift mode input of the address register 4.

The inverted output and the positive output of the gates 18 and 19 become the two-man power of the Nantes gate 16, and the output becomes the one-man power of the AND gate 17. Also, the inverted output of gate 19 is
4 becomes the power of others, and it becomes the power of others of Nantes Gate 15. The output 109 of the gate 14 becomes the hold (HLD) input of the read register 5, and the output 109 of the gate 14 becomes the hold (HLD) input of the read register 5.
The re-output will be done by two people using AND gate 17. The output 110 of this gate 17 becomes the hold input of the address register 4. The positive output 111 of the gate 19 serves as a switching input for the selectors 7 and 8.

With the control circuit 9 having such a configuration, each of the read register 5, the AND register 4, and the selector 7.8 performs the logical operation as shown in FIG. The operations of the read register 5 and the AND register 4 in FIG. 3 are performed in synchronization with the clock (CLK) 106 when it is output.

Figure 4 shows the input/output bin types of all registers used in CPU 1, where SI is shift data input, SO is shift data output, CLK is clock, and SM
is the shift mode, HLD is the hold (save) terminal, ()i, zi (i indicates a bit, 1 = 0 to n
-1) indicates input/output data.

Fig. 5 is a diagram showing the relationship between the signal state of each bin shown in Fig. 4 and logical operation. Indicates the contents of a register, and - indicates that it can take any value. As is clear from the truth table in Figure 5, when 1 is applied to the shift mode (SM) input, the contents of the register are shifted upward by one bit in synchronization with the clock (CLK). It has become. The internal registers of CPU1 are shift paths 101, 102, 103.
, 104, and 105, the shift mode signal 107 is set to 1 and the clock 106 is set to C.
By supplying the same number of bits as the internal registers of the PU 1, it is possible to set all the information in the internal registers to the service processor 10.

With this configuration, all data in the scratch pad memory 3 is read out according to the procedure shown in the flowchart of FIG.

First, in step 1, a shift mode (SM>signal 107 is output from the service processor 10 and the CPU 1
All registers in the service processor 10 enter shift mode, and the current contents of all registers are read out to the service processor 10 in synchronization with the clock signal 106 (step 2). At this time, since the memory read mode signal 108 is not output, the shift mode signal 112 from the control circuit 9 is at logic 1, so it is clear that the address register 4 is also in the shift mode.

After the current contents of all registers have been read in this way, 0 is written into the address register 4 using a shift pass in step 3. This is a preparatory step for sequentially reading out all data in the scratch pad memory 3 starting from the data at address 0. In step 4, the memory read mode signal 108 is set to logic 1, and the shift mode and memory read mode are entered for the first time. Therefore, the selector 8 is the shift bus 101
is selected and all other registers except address register 4 are connected via a shift bus, and address register 4 is in hold mode and stores address 0.

In step 5, when the shift mode is reset and the clock 106 is output, the read register 5 is loaded with the data at address 0 of the scratch pad memory 3 at 1 o'clock, and the address register 4 is loaded with the adder 6. 1 is added at , and the next address is designated. After that, the shift mode is set in step 7, and the contents of the read register 5 are sequentially transferred to the service processor 1 bit by bit in synchronization with the clock using the shift bus.
0 (step 8). During this time, the contents of address register 4 are in a preserved state.

Next, in order to read the data at address 1 of the scratch pad memory 3 to the read register 5, the shift mode is reset (step 5), and the data at address 1 is written to the read register 5 in response to the clock output timing. At the same time, the contents of address register 4 are incremented by 1 to indicate address 2. The data at address 1 loaded into the read register 5 is read bit by bit to the service processor using the shift bus in shift mode.

When all the contents of the scratch pad memory 3 are read out, the shift mode is reset in step 9, and the memory read mode is further reset in step 10 to return to the initial state.

In the conventional method, before outputting the clock in step 6 of FIG. 6, it is necessary to set a read address in the address register 4 and to set an appropriate value in the control flip-flop for inputting data to the read register 5. Yes,
These operations were performed using a shift bus, but according to this embodiment, the above operations are performed by hardware using the clock output in step 6, so there is no need to use a shift bus, and the scratch pad memory 3 is The read time is approximately 1/2.

As explained above, according to the present invention, in the memory read mode and not in the shift mode, when the clock is delayed, a specific value is added to the contents of the address register, and the contents of the memory are When read to the read register and in memory read mode and shift mode,
By configuring the structure so that the contents of the address register are saved and the shift bus that connects the internal registers other than the address register operates, the memory read time can be reduced to about half the speed of the conventional method. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a specific example of the control circuit in FIG. 1, FIG. 3 is a diagram showing the operation mode of each part of the circuit in FIG. 1, and FIG. 5 is a diagram showing the form of the input/output bins of the register, FIG. 5 is a diagram showing the truth value relationship of the input/output bins of the register, and FIG. 6 is a flowchart showing the operation of the blocks in FIG. 1. Explanation of symbols of main parts 1...CPU 3...Scratch pad memory 4...
Address register 5... Read register 6... Adder 7.8... Selector 9... Control circuit

Claims (1)

[Claims] The data shift path includes a memory, a read register for setting read contents of the memory, an address register for holding an address of the memory, and a series connection of other registers including the read register; A memory read method in a data processing device in which data set in the read register is read out to the outside by operating registers constituting a data shift path as a shift register, the memory read method for reading the memory. mode command means for commanding a shift mode for shifting data in the data shift path; The content of the address specified by the address register of is set in the read register, and in the case of the memory read mode and the shift mode, all registers other than the address register are connected in series as the data shift path. a control means for controlling data shifting, and the memory contents are read out to the outside by repeatedly reading out the contents of the read register using the data shift path.