JPS62208672A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To protect an electrode formed on a protective film by forming a film which has tapers on the side walls of both the ends of a gate electrode formed on a semiconductor substrate. CONSTITUTION:A spacer film 14A for introducing an impurity atom such as a phospho-silicate glass film having gentle tapers on both end ends of a gate electrode 12 is formed. The impurity atom is ion-implanted from the spacer film 14A including the gate electrode 12 and source and drain regions 15B, 16B wherein the P-N junction against an Si substrate 13 extends from both the ends of the gate electrode 12 by forming a gentle taper are formed. Further, the spacer film on both the ends of the gate electrode 12 is reflowed, a reflow film 14B which has a gentle taper is formed and the content of phosphorus in the phospho-silicate glass film (protective film) 17 formed on the reflow film for the protective film is made minimum. This prevents the Al electrode formed on the protective film 17 from being affected by phosphorus atoms.

Description

[Detailed Description of the Invention] [Summary] An MO3 type semiconductor device and a method for manufacturing the same, comprising:
The side walls at both ends of the gate electrode are made of phosphosilicate glass film or C which has a gentle taper and serves as a mask for ion implantation.
A 5i02 film is formed by the VD method, and in this state, impurity atoms are ion-implanted into the source and drain regions to form a gently tapered P layer below both ends of the electrode.
Source and drain regions having -N junctions are provided.

In this way, concentration of the electric field at the P-N junction between the source and drain regions and the substrate is avoided, no hot electrons are generated, and there is no reduction in current drive capability.
In addition, both ends of the gate electrode have a gentle taper, so that the phosphosilicate glass film of the protective film covering the gate electrode can be flattened with a low concentration of phosphorus.
This prevents the master electrode formed on it from being attacked by phosphorus.

[Industrial application field]

The present invention relates to a semiconductor device, particularly an MO3 type semiconductor device,
In particular, the shape of the P-N junction between the source and drain regions under both ends of the gate electrode and the substrate is made to have a gentle taper shape to avoid concentration of electric field at the P-N junction portion. The present invention relates to a method for manufacturing a semiconductor device.

MO3 type ICs, including MO3 type transistors, are required to be formed with higher density and finer details.
It is also required that type transistors be formed finely.

Even when an MO3 type transistor is formed into a fine structure in this way, it has a structure that avoids concentration of electric fields at the P-N junction formed between the source region and the drain region and the substrate. Therefore, there is a need for a method of manufacturing an MO8 type semiconductor device in which the dark voltage vth of the semiconductor device to be formed does not vary due to hot electrons introduced from the substrate toward the gate electrode.

[Conventional technology]

Conventionally, an MO3 type semiconductor device with an Ljghtly-Doped-Drain (hereinafter referred to as LDD) structure has been developed as a structure to avoid concentration of electric field at the P-N junction between the source fi region and the drain region and the substrate. has been done.

In order to manufacture an MO5 type semiconductor having such an LDD structure, as shown in FIG. 6, after forming a gate oxide film 3 on a P-type Si substrate 2 defined by an oxide film 1 for isolation, A gate electrode 4 made of polySt is formed in a predetermined pattern on a substrate.

Next, using the gate electrode 4 as a mask, phosphorus atoms (P+
) as indicated by arrows, ions are implanted with low acceleration energy to form low concentration N- regions 5A and N- regions 68.

Furthermore, as shown in FIG. 7, 5i was deposited on the substrate by CVD method.
After forming the 5i02 film 7, the 5i02 film 7 is anisotropically etched using reactive ion etching (RIE) to form 5i02 spacers on both ends of the gate electrode 4, as shown in FIG. A film 7A is formed.

As shown in FIG. 9, the S+02 film 7 of this spacer
Using the gate electrode 4 having A as a mask, arsenic (As) atoms are ion-implanted from above the substrate 2 to form a highly concentrated N+ region 5B.
, and a high concentration N4 region 6B.

The source region 5 is formed using the low concentration region 5A and the high concentration region 5B, and the drain region 6 is formed using the low concentration region 68 and the high concentration region 6B.

In this way, the concentration change at the end A of the source region 5 and the end B of the drain region 6 under both ends of the gate electrode 4 with respect to the substrate 2 is prevented from becoming steep, and the electric field in those parts is reduced. I was trying to ease my concentration.

[Problem that the invention seeks to solve]

However, in such an LDD structure, when controlling the current flowing between the source and drain by changing the voltage applied to the gate voltage of the MOS transistor formed in this way, In order to eliminate the amount of change in current between the source and drain, that is, the current driving ability is insufficient, and the electric field concentration phenomenon at the end A of the source region 5 and the end B of the drain region 6 described above, There is only one.

This means that the source region 5 is formed of the low concentration region 58 and the high concentration region 5B, and the drain region 6 is formed of the low concentration region 58 and the high concentration region 5B.
8 and the high concentration region 6B, concentration of the electric field can be avoided when the concentration of the low concentration regions 5A and 6A is low, but the current driving ability is not sufficient and the low concentration region 5
There is a problem in that it is difficult to control the concentration of the mutual regions Δ, 6A and the high concentration regions 5B, 6B.

Furthermore, since the shape of the PN junction at the end A of the source region @5 and the end B of the drain region 6 is steep, it is inevitable that the electric field will be concentrated in these parts.

After forming the gate electrode in this way, a phosphosilicate glass film is coated on the substrate as a protective film,
There is a flattening process in which the wafer is melted on the shoulder part of the gate electrode so as not to create a level difference. It is necessary to increase the concentration of phosphorus in the phosphosilicate glass.

However, when the concentration of phosphorus is increased to form a phosphosilicate glass film as a protective film, this phosphorus reacts with moisture in the atmosphere to form phosphoric acid, and this phosphoric acid and the aluminum formed on it react. A problem arises in which the electrodes are attacked.

Therefore, it is desirable to reduce the phosphorus content in the phosphosilicate glass film of the protective film as much as possible.

The present invention solves the above-mentioned problems by creating a shape that prevents electric field concentration from occurring at the P-N junction between the source region and the drain region and the substrate, and also by creating a gentle taper between the gate electrode and the substrate. This makes it easier to flatten the protective film formed on the gate electrode, eliminating the need to add phosphorus to the phosphosilicate glass film at a high concentration, and making it easier for the M electrode formed on it to flatten. The purpose of this invention is to provide a method for manufacturing a semiconductor device in which the protective film is not attacked by phosphorus.

Means for Solving Problem C] As shown in FIG. 1, the semiconductor device of the present invention includes a phosphosilicate glass film having a gently tapered shape at both ends of a gate electrode 12 formed on a semiconductor substrate 13. , or CVD
A reflow film 14B made of a SiO2 film is formed by a method.

The method for manufacturing a semiconductor device of the present invention includes forming a masking film 14 on a substrate 13 on which a gate oxidation 1*11 and a gate electrode 12 are formed, as explained from FIGS. 2 to 5. a step of anisotropically etching the mask film 14 formed on the substrate 13 to form a spacer film 148 on the side walls of both ends of the gate electrode 120; A step of reflowing the provided spacer film 14^ to form a reflow film 14B having a gradual taper shape laterally from both ends of the Gecoto electrode 12, and impurity atoms are removed from above the substrate 13 through the reflow film 14B. Introducing source and drain regions 15B.

16B.

[Effect]

In the semiconductor device of the present invention, a spacer film 14A for introducing impurity atoms, such as a phosphosilicate glass film having a gentle taper, is formed at both ends of the gate electrode 12.
Impurity atoms are ion-implanted from above the spacer layer t4A including the electrode 12, and the source and drain regions 158.16+ have a PN junction with the substrate 13 extending from below both ends of the gate electrode 120 forming a gentle taper.
1 is formed, source and drain regions 15B,
Avoid concentration of electric field at the PN junction between 16B and the substrate 13.

Furthermore, the spacer films at both ends of the gate electrode 12 are reflowed to form a gently tapered or flow film 14B, and a phosphorus-containing glass phosphorus silicate glass H ¥17 is formed as a protective film thereon. The amount is made small so that the AQ electrode to be formed on the protective film 17 in a later step is not attacked by the phosphorus atoms of the phosphosilicate glass film.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

As shown in FIG. 1, the semiconductor device of the present invention has a substrate 13
A reflow film 14B made of a phosphosilicate glass film or the like having a gently tapered shape at both ends of the upper gate electrode 12.
is formed, and impurity atoms are introduced using the reflow film 1.4B as a mask to form a tapered P that gently extends from below both ends of the gate electrode 12 in the lateral direction of the substrate.
A source region 15B and a drain region 16B having an N junction are formed.

Further, a protective film 17 made of a phosphosilicate glass film is formed on the substrate 13'.

When manufacturing such a semiconductor device, first, as shown in FIG.
At a low acceleration voltage of KeV, P+ atoms are
The low concentration N- region 15 is formed by ion implantation at a dose of
8 and a low concentration N- region 168 are formed.

Next, a phosphosilicate glass film 14 is formed to cover the substrate 13 by the CVD method.

Next, as shown in FIG. 3, using reactive ion etching (RIE), which is anisotropic etching,
The phosphosilicate glass film 14 is anisotropically etched. In this anisotropic etching, the vertical etching speed of the phosphosilicate glass film 14 is faster than the horizontal etching speed, so when the phosphosilicate glass film 14 on the gate electrode 12 is etched, both sides of the gate electrode 12 are etched. The phosphosilicate glass film remains on the side wall of the end portion as a spacer film 14A.

Next, as shown in FIG. 4, the spacer film 148 made of a phosphosilicate glass film attached to this side wall is reflowed to form a reflow HJ], 4B.

This reflow temperature can be as low as 1000° C. or less because the spacer film 14A itself is thin.

Next, as shown in FIG. 5, arsenic atoms (As+) are added at 150 KeV from above the substrate 13 using the reflow film 14B and the gate electrode 12 as masks, which extend from both ends of the gate electrode 12 with a gentle taper to the left and right. A source region 1511 and a drain region 16B are formed by implanting ions at a voltage of 1/2 and a 1° dose of 10°.

The source region 15B and the drain region 16B are formed with a gentle curve in the P-N junction with the substrate from below both ends of the gate electrode 12 in the lateral direction. No concentration of electric field is seen at the P-N junction between the two.

In addition, the protective film 17 formed on the substrate extends horizontally from both ends of the lower gate electrode 12 to the phosphosilicate glass film 1.
4^ is formed with a gentle taper, so that there is no step difference on the shoulder C of the gate electrode 12, and it is formed with a gentle taper, unlike the conventional phosphosilicate glass film 1.
7 does not require a reflow process.

Furthermore, even if a reflow process is required, since the protective film 17 is formed with a gentle taper, the concentration of phosphorus contained in the phosphosilicate glass film 17 can be reduced, so that The electrode is made of phosphosilicate glass film 1.
It is not attacked by phosphorus of 7.

In this embodiment, as shown in FIG. 2, a low-acceleration ion implantation step was performed, but after forming the source region 15B and drain region 16B by ion implantation, the step of heat-treating the substrate 13 was performed. In some cases, an N-type channel region is formed extending directly under the gate electrode process 2 through this heat treatment process, and in this case, the low acceleration ion implantation process shown in FIG. 2 may not be performed.

〔Effect of the invention〕

As described above, according to the semiconductor device of the present invention and its manufacturing method, ion implantation is performed using a gate electrode and a phosphosilicate glass film extending laterally with a gentle taper from both ends of the gate electrode as a mask. Since the formed P-N junctions of the source and drain regions with the substrate are formed with a gentle taper below both ends of the gate electrode, the P-N junction between the source and drain regions and the substrate
The concentration of electric field is no longer observed at the -N junction, and therefore the generation of hot electrons is suppressed.

Also, since there is no low concentration diffusion region like the LDD structure,
The resistance of the source and drain regions can be reduced, which has the effect of not deteriorating the current drive ability.

In addition, since the concentration of phosphorus contained in the phosphosilicate glass film, which causes the protective I odor on the gate electrode I box, can be reduced to a low concentration, the electrodes will not be attacked by the phosphorus atoms of the phosphosilicate glass film. This has the effect of providing a highly reliable semiconductor device.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the structure of the semiconductor device of the present invention; FIG. FIG. 3 is a cross-sectional view showing a method for manufacturing a semiconductor device in order of steps. In the figure, 11 is a gate oxide film, 12 is a gate electrode, 3 is an St substrate, 14 is a phosphosilicate glass film, 148 is a spacer film, 14
B beam flow film, 158 and 16A are N- regions, 15B is a source V4 region, and 16B is a drain region. Healing device - 7F ke ribs @ 1 Fig.
Figure 2
Ball 11-fu FSG! f) Mi fshaa' 工jYrBFigure 3Figure 6

Claims (4)

[Claims] (1) Source region (15B), drain region (16B)
, a semiconductor device comprising a gate electrode (12), characterized in that a tapered coating (14B) is formed on the side walls of both end portions of the gate electrode (12). (2) Gate oxide film (11) and gate electrode (12)
) forming a masking film (14) for introducing impurity atoms on the silicon substrate (13) on which the masking film (14) formed on the substrate (13) is anisotropically etched; a step of forming a spacer film (14A) on the side walls of both ends of the gate electrode (12); a step of forming a spacer film (14A) on the side walls of both ends of the gate electrode (12);
14A) is reflowed to form a reflow film (
14B), and forming a source region (15B) and a drain region (16B) by ion-implanting impurity atoms from above the substrate through a reflow film (14B). Production method. (3) The method for manufacturing a semiconductor device according to claim 2, wherein the mask film (14) is a phosphosilicate glass film or a silicon dioxide film formed by chemical vapor deposition. (4) After forming a mask film (14) on the substrate (13) and prior to anisotropically etching the film (14), impurity atoms are introduced into the substrate (13) to reduce the concentration of the mask film (14). 4. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of forming source and drain regions.