JPS62208156A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To effectively utilize an input/output device by coupling plural micro- processors with an internal bus coupled with memories and the I/O device through plural bus interfaces and operating the microprocessors successively and asynchronously. CONSTITUTION:Respective emulator CPUs 11-1n are coupled with the body CPU internal bus 10 through bus interfaces 1-(n) and a ROM 41, a RAM 42, a DMA 43, a video RAM 44, and the I/O device group 45 are connected to the bus 10. The device group 45 is shared by all the CPUs 11-1n, bus a CPU for executing I/O access is fixed only one of the CPUs 11-1n and sequentially and asynchronously operated. When an I/O access request is generated in a program in executing, a slave CPU is replaced by a master CPU and the I/O access is executed by the master CPU. Thus, the sharing use of the I/O device group 45 between the CPUs having different structure each other can be attained independently of the transmission/reception of an instruction and response data.

Description

DETAILED DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION In general, all human outputs such as console input/output, disk human output, and relay human output are controlled only by the CPU provided to control those I10 devices. . The machine language code of a program can only be executed by a dedicated processor, so when you want to run a program written in other machine language code, the conventional method is to
Use a CPU board equipped with a CPU for machine language code! However, this goal has been achieved by installing it in the expansion slot of the main computer system and operating it in parallel with the main computer system. An example of this is shown in FIG.

Below, with reference to FIG. 2, the conventional multiprocessor and I
The interface method between 10 will be explained.

In FIG. 2, 40 is a CPU as a general-purpose processor.
, 41 is a read-only memory (hereinafter referred to as R, OM) 42 in which initialization programs, monitor programs, etc. are stored.
is a random access memory (hereinafter referred to as AM) that stores data from the ROM 41, the external storage device 46, and the I10 device 47, 48, 10 is an internal bus dedicated to the CPU 40, and 43 is the entire memory content of the ROM 41, RAM 42, etc. Direct memory access, 4
4 is the bidet number 1 N'A M'1.50 is the general purpose processor C
The main body of the computer system is mainly composed of the PU 40, 31 is an in-circuit OS emulator connected as an expansion board for exchanging data with the main body of the computer system, 11 is a CPU with a structure that is the target of OS emulation, and 60 is an OS emulator. ROM having an initialization program, 61 is a RAM for storing data from the computer system main body 50, 62
is the internal bus dedicated to CPU11, 21 is the CPU40 and CP
This is a data buffer provided in the parallel port of the OS emulator 31 for communication between U11.

The operation of the above configuration will be explained below.

When the power is turned on, the 0PU 40 and cpull each start operating, and the CPU 40 of the computer system body 50 brings the program to be executed by itself and the program to be executed by the CI'U 11 from the external storage device 46 to the R, AM 42. By executing its own program, the CPU 40 transfers the program of the CPU 11 to the RAM 61, and then transfers control to the CPU IG. cpul 1 uses C! by running its own program. PU40
will be placed under the control of 0PUII. In the end, the in-circuit OS emulator 31 and the computer system main body 50
The entire system consisting of the following appears to be a machine with 11 CPUs. The OS emulator 31 and the computer system main body 50 exchange data by handshaking using the buffer 21 of the parallel port. As the I10 port of the OS emulator 31, there is only a parallel port with the computer system main body 16.

The OS emulator 31 is the computer system main body 1
Input/output is performed using the I10 device group 45 of 6. That is, the CPU 11 sends command data for Ilo to the computer system main body 50, which is received by the 0PU 40, which interprets the data, and the CPU 40 controls the I10 device group 45. The resulting data is sent from the 0PU 40 to the OS emulator 31 as response data. In this way, in the in-circuit type, control (1) from the OS emulator 31 is achieved indirectly using the data communication method.

Problems to be Solved by the Invention However, in the above configuration, the I10 device 46.
47. The command to 48 is main body C! Since it relies on handshaking with the PU 40, arbitration between the CPUs is required, which becomes more difficult in proportion to the number of boards.

The present invention solves the above-mentioned problems of the prior art, and aims to enable the CPU 11 of the emulator 31 to directly access the I10 devices 47 and 48 of the main body.

Means for Solving the Problems In order to achieve the above object, the present invention connects a plurality of CPUs directly to the CPU internal bus on the main body side via a bus interface, and determines whether the operating CPU needs I10 access or not. It is designed to switch sequentially.

According to the above-mentioned configuration, the present invention fixes any one of the plurality of CPUs to be subjected to I10 access, and when an access request occurs to the operating CPU, By switching to a CPU with a different structure, a common I10 device can be effectively used even among processors with different structures.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a heterogeneous multiprocessor system according to an embodiment of the present invention.

In Fig. 1, 11.12, . It is fixedly determined as one of the following. Below is the CP asked for this I10 access.
U is called a main CPU, and the other CPUs are called sub-CPUs. 41
rtOM stores the initialization program and monitor program for the entire system; 42 is I1 of the external storage device 46, etc.
0 stores data from the device group; 10 is a CPU internal bus; 45 is an I1 that follows the structure of the internal bus 10;
0 device group, external storage device 46, I10 device 4
It consists of 7.48, etc. 1.2,...n is the main C
ROM4 connected to the internal bus 10 on the main body side of the PU structure
This is a bus interface that allows the sub CPU to directly access the AM42 and AM42. 43 is a direct memory access, and 44 is a video RAM.

The I10 device group 45 is shared by all the 0PUIs 1 to In, but the CPU to which the I10 is accessed is fixedly determined to be one of them.

Furthermore, only one CPU is running at any given time when the system is running, and multiple CPUs do not run in parallel. When an I10 access request is generated on a program being executed, the secondary CPU takes over operation from the main CPU and executes the I10 access by the main CPU. Main CP
While U is in operation, the sub CPU is in a halt state and has no effect on the internal bus IOG. When the I10 access processing is completed, the operation is returned to the sub CPU, and the main CPU returns to the Halt state. When an I10 access request occurs on a program being executed by the main CPU, the main CPU directly enters I10 access processing.

Since the CPU to be accessed by I10 is fixedly determined, there is no need to specify the other party when switching operations, and the internal logic of the bus interfaces 1.2, . I can do it. Therefore, I1
0 access requires 1 communication between the CPUs.

As is clear from the above description, according to this embodiment, each of the emulator CPUs 11 to 1n is connected to the bus interface 1.
By connecting directly to the main body CPU internal bus 10 by ~n, I10 device group 4 can be connected between CPUs of different types and structures.
5 can be shared without relying on the transmission and reception of commands and response data.

Effects of the Invention As described above, the present invention allows the programs of the other CPU, which has a different structure, to coexist and execute on the memory belonging to one CPU.
Even if a processor is not fully equipped with I, if it is connected to a general-purpose processor system as an emulator CPU, programs and other databases that could only be used on a general-purpose processor can be used from the emulator CPU. The effect is great.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a heterogeneous structure multiprocessor system according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional heterogeneous structure multiprocessor system. 1~n...Bus interface, 11~1n1
40...Processor, 41...Read-only memory, 42...Random access memory, 45...Name of I10 device group agent Satoshi Nakao, patent attorney 1 male person 1st
figure

Claims (2)

[Claims] (1) comprising a plurality of microprocessors, a plurality of bus interfaces coupling the plurality of microprocessors and an internal bus, and a memory and an input/output device coupled to the internal bus; A multiprocessor system characterized by asynchronous operation. (2) The multiprocessor system according to claim 1, wherein the plurality of microprocessors are incompatible.