JPS62205645A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid undesirable effects of pinholes and contained hydrogen, by depositing and forming an etching stopper layer comprising, e.g., SiNx on or beneath a wiring pattern having step parts at the side parts so that the thickness is limited. CONSTITUTION:An Al wiring pattern 3 is formed on an SiO2 layer 2. An SiNx film 6 is deposited on the pattern 3. The film 6 is deposited to a thickness of about 1,000Angstrom at a processing temperature of 300-400 deg.C with silane and ammonia as raw material by a low temperature plasma CVD method. An SiO2 layer 4 is continuously deposited. RIE is performed. SiO2 is made to remain on the side surface of the Al layer. Then an SiO2 layer 5 is deposited, and a gentle surface is implemented. When the thickness of the SiNx film has this value, pinholes are not penetrated between the upper and lower surfaces. Therefore, the function as an etching stopper is sufficient. The amount of contained hydrogen increases in proportion to the thickness of the film. At this value, however, the effect on the characteristics of the element is slight.

Description

[Detailed Description of the Invention] [Summary] In an integrated circuit with multilayer wiring, in order to avoid breakage of upper layer wiring due to steep steps on the substrate surface, a thick silicon dioxide layer is deposited and reactive ion etching ( (hereinafter abbreviated as RIE)
to make the step part a gentle slope. A thin silicon nitride film is laid down under this thick silicon dioxide layer as an etching stopper, but its thickness is limited to avoid undesirable effects of pinholes and hydrogen content.

[Industrial application field]

The present invention relates to prevention of disconnection in semiconductor integrated circuits having multilayer wiring, and particularly to a stopper for anisotropic dry etching for step coverage.

In the manufacture of integrated circuits, conductive patterns are formed in multiple layers through insulating layers, but if the upper conductive film is deposited with steep steps on the surface, discontinuities occur at the stepped portions. There is a risk of it becoming.

In order to avoid this, upper layer wiring is formed after filling the recessed part of the step and changing it to a gentle slope. This filling part is sometimes called a sidewall.

Various methods of this type of technology are known, such as methods using spin-on glass. For example, there is a technology in which an inorganic compound of silicon dissolved in a solvent such as alcohol is spin-coated and converted into silicon dioxide by heating. Taking advantage of the anisotropy of RIE, that is, the property that etching progresses only in the direction perpendicular to the substrate, it has become common practice to leave a filler material such as silicon dioxide in the recessed portion of the step to form a gentle slope. Ta.

[Conventional technology]

FIG. 3 (al to tel are cross-sectional views showing an example of the prior art) is formed, and its side surfaces are vertical.

When the Sing layer 4 is deposited on this layer, a step is generated as shown in FIG.

Here, when the SiOz film 2 is etched by that thickness by RIE, since etching mainly proceeds in the direction perpendicular to the substrate in RIE, SiO2 remains on the sides of the A1 layer as shown in the figure (bl). and a sloped surface is created.

The same figure (C1
Since a smooth surface is obtained, there is no risk of disconnection even if AI wiring is formed here.

The above is the surface planarization technology using conventional RIE, but with this method, it is difficult to determine the end point of R[E, and if the etching becomes excessive, even the underlying layer SiO□N2 is etched, so it is difficult to planarize the surface. It may also lead to results that are contrary to the purpose.

In addition, as a conventional technique, in order to prevent unnecessary etching progress, for example, in the case of opening a through hole,
Utilizing the differences in etching characteristics of different materials,
It is known to automatically stop etching, and for this purpose interposing a dissimilar material film, RIB
It is also known that by selecting the conditions, Sing and SiN can have different etching rates.

[Problem that the invention seeks to solve]

However, in surface planarization by RrE, S
The iN* film is not normally used as an etching bath, and there are still issues to be solved in order to implement it, such as the method of forming the film and its thickness.

That is, although the 5iNX film formed by high-temperature CVD is dense and of good quality, it cannot be deposited on top of the A1 layer 4 because the processing temperature is about 800°C. Furthermore, since the low-temperature plasma CVD method is processed at 300 to 400° C., it can be performed after forming the A1 layer, but the formed SiN film contains a large amount of hydrogen, which may deteriorate the device characteristics.

Furthermore, it is necessary to have an effective thickness as an etching buckwheat, but if it is too thick, it will have undesirable effects such as an increase in forming processing time and residual stress.

An object of the present invention is to provide a method for manufacturing a semiconductor device that solves this problem.

[Means for solving problems]

The above-mentioned problem is solved by the method described in claim 1 of the present application, but to summarize the present invention according to the embodiments, it is possible to An etching buckwheat layer of S i N ll is provided, a filler material such as Sing is applied to the entire surface of the four corners, and the filler is left only in the stepped portions by anisotropic etching such as RrE. Furthermore, when 5iNX is used as an etching bath, it can be deposited to a limited thickness using a low 1cVD.

[For production]

SiN deposited under the Sing layer which is the filler in the four corners
Because the film acts as an etching stopper due to the difference in etching properties during RIE, RIE does not proceed excessively. Furthermore, since the thickness is not more than necessary, the undesirable effects of hydrogen content are kept within acceptable limits.

〔Example〕

FIG. 1 (al-(II)) is a sectional view 1 showing the processing steps of the present invention.

In this first embodiment, S i
AII on top of OzJi 2! To! NiA3 is formed, and the SIN film 6 is deposited on it.As mentioned above, the conditions for forming the film 6 are important.In this example, silane and ammonia are used as raw materials, and the processing temperature is ~4
The layer 4 is deposited successively by a low temperature plasma CVD method at 00° C., and the following steps are identical to the prior art.

As shown in Figure 1 (C1), RYE is performed under the conditions that SiO2 is etched but SiN is not etched, leaving Sing on the side surface of the A7 layer.
A smooth surface is achieved by depositing SiO□N5.

Since the siN11M51 is not etched in this RIB process, the stotN2 below it is also not etched, achieving the purpose of preventing excessive etching.

When the thickness of the SiN film is as above, there is no pinhole communication between the upper and lower surfaces, so the function as an etching stopper is sufficient, and the amount of hydrogen contained is proportional to the thickness of the film. However, if the value is around the above value, the effect on the device characteristics is slight. Furthermore, the influence of residual stress can also be ignored.

In the process of this embodiment, the SiN layer 6 and its upper layer Si
Since OzN 4 is formed continuously by the same equipment, the increase in processing time is small, and furthermore, the A
! Since the surface is coated with SiN, there is also the effect that the surface is not contaminated.

The s+N, tf! which meets the purpose of the present invention! The thickness is as follows.

The lower limit is determined solely by the presence or absence of pinholes. When forming the film by low temperature plasma CVD method, 5
If the thickness is 0.00 mm or more, pinholes will disappear.

In the case of the present invention, the upper limit is determined by the amount of hydrogen contained, but according to the knowledge obtained by the present inventors, when the film is formed by low-temperature plasma CVD method, this value is 3.
000 Å or less, even if contained hydrogen exists, its influence is slight and does not affect the characteristics of the completed integrated circuit device.

FIGS. 2(a) and 2(b) are cross-sectional views showing another processing step of the present invention.

In this second embodiment, S i
An N.sub.X film 6 is previously deposited, and a Si02 layer 4 for planarization treatment is deposited thereon (FIG. 4(a)).

In this case, when forming the 5iNX film, the A1 layer, which does not allow high-temperature treatment, does not yet exist, so it is possible to employ a high-temperature plasma CVD method using dichlorcycine and ammonia as raw materials. The SiN film produced by this method is dense, pinholes disappear with a thinner film thickness, and there is almost no hydrogen content, so the restrictions on film thickness are greatly relaxed.

The following steps are the same as in the first embodiment, and A
SiO□ for planarization is left on the side surface of layer 7, and a new SiOz layer 5 is deposited as an interlayer insulating material (FIG. 2(b)).

Compared to the first embodiment, the method of this embodiment has less restrictions on the film thickness, such as < SiN, as described above.
If a hygroscopic layer such as PSG exists under the iN11 film, it will have the effect of blocking moisture and protecting it, but on the other hand, contamination of the AI layer surface will be the same as in the conventional technology. , A7 wiring is SiN, poly-S under the film
i[-v: There is also the disadvantage that the through-hole opening process for connecting to the diffusion region of the J substrate becomes complicated.

〔Effect of the invention〕

In the present invention, when performing planarization processing by RIE, since the SiN film is provided as a stopper, RIE does not proceed excessively, and depending on the formation position of the SiN film,
A! This also has the effect of preventing contamination of the wiring layer surface.

Furthermore, since the thickness of the SiN coating is limited according to its formation method, undesirable effects can be avoided.

[Brief explanation of drawings]

Figure 1 (al ~ (di is a cross-sectional view showing the processing steps of the present invention, Figure 2 [al, (bl is a cross-sectional view showing another treatment process of the present invention, Figure 3 fat ~ (c + is a sectional view of the prior art) This is a cross-sectional view showing an example. In the figure, ① is the lower layer which is a semiconductor substrate or poly-Si layer, 2 is the lower SiO□ layer, 3 is the wiring pattern, 4.5 is SiOzlM, and 6 is the 5iNX film. . 1st flash attack / 7 separate r5 kari L o L1 show - t + rr side lo activity 2
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Claims (2)

[Claims] (1) A step of depositing an etching stopper layer (6) on a semiconductor substrate having an insulating material layer (2) deposited on at least a portion of the surface; and a step of depositing the etching stopper layer (6). After performing the process of selectively depositing the wiring pattern (3) before or after the process and all of the above processes, a layer of the same material as the insulating material (2) or a material layer (4) having similar etching properties is applied. 1. A method of manufacturing a semiconductor device, comprising a step of depositing the semiconductor material, and a step of non-selectively performing anisotropic dry etching. (2) After the step of selectively depositing the wiring pattern, the etching stopper layer (6) is deposited by low-temperature plasma CVD, and the thickness of the etching stopper layer is 500 Å to 3000 Å. A method for manufacturing a semiconductor device according to claim 1, characterized in that: