JPS62204296A - Display circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a display circuit that displays at least characters, waveforms, etc. by sequentially lighting up display points corresponding to pre-stored data on an electrostatic deflection cathode ray tube. This invention relates to a display circuit that can be used in a readout oscilloscope, etc.

(Problems to be Solved by the Invention) Conventionally, a method has been used in which two D/A converters are used to designate and display one display point on a cathode ray tube. However, in this case, a digital memory or the like may be used to display the scale of the outer frame of the cursor or the limit value of the waveform, etc., superimposed on the main waveform that is mainly desired to be observed. In this case, if the main waveform and the other displays have the same brightness, there is a problem that it becomes difficult to distinguish the main waveform that you want to see.

The present invention has been made in view of the above, and an object of the present invention is to provide a display circuit that solves the above problems.

(Means for Solving the Problems) In order to solve the above problems, the present invention is constructed as follows.

The display point data corresponding to the display points are sequentially read out from the storage means that has been stored in advance, and the read display point data is transferred to the D/
A display circuit that specifies display points by supplying the D/A conversion output to an electrostatic deflection cathode ray tube as a deflection signal and sequentially illuminates the specified display points, the storage means is used as a display point for main display. It is divided into a first storage section in which data is stored and a second storage section in which display point data for auxiliary display is stored. It is equipped with means for switching the number of times of display.

(Function) In the present invention configured as described above, the storage means includes a first storage section in which display point data for the main display (e.g., waveform display) is stored, and a display for the auxiliary display (e.g., scale display). Display point data for point data is divided into a second storage section in which point data is stored, and the number of times of address specification in the first storage section is switched to multiple times the number of times of address specification in the second storage section. done by means.

Therefore, while the display point data stored in the first storage section is read out multiple times, the display point data stored in the second storage section is read out once.

As a result, the main display, such as the waveform display, is displayed darkly, and the auxiliary display, such as the scale display, is displayed thinly, and the main display does not become difficult to distinguish.

(Example of the invention) The present invention will be explained below using examples.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Address data from address counter 1 is supplied to memory 3 via multiplexer 2 to designate an address for memory 3. On the other hand, address data from the microcomputer via the address buffer 4 is sent to the multiplexer 2.
It is supplied to Data read from memory 3 is supplied to data latch circuits 5 and 6 and latched therein. Data from the microcomputer to the memory 3 or vice versa is supplied to the memory 3 via the tristate data bus buffer 8, and the contents of the memory 3 can be written or read by access from the microcomputer. That's how it is.

The latch data of the data latch circuit 5 is supplied to the D/A converter 9, and its analog output is used as an X-axis deflection signal, and the latch data of the data latch circuit 6 is supplied to the D/A converter 10, and its analog output is used as an X-axis deflection signal. The analog output is supplied to the cathode ray tube as a Y-axis deflection signal.

On the other hand, as schematically shown in FIG. 2(a), the memory 3 has two
The memory area is divided into two parts, and one part is allocated to a character data storage area, and the other part is allocated to a waveform data storage area.

Further, as schematically shown in the second figure, X-axis circumferential data and Y-axis circumferential data corresponding to the display point position to be illuminated are stored as a pair, for example, in adjacent addresses.

In addition, 7 is a display number switching circuit, and the ratio of the total number of address designations in the upper half to the total number of address designations in the lower half shown in FIG. 2(a) of the memory 3 is 1/n (n = integer). It is configured so that. An example of the display number switching circuit 7 when n=4 is configured as shown in FIG. , an inverter 78 that inverts this MSB, a D flip-flop 1 circuit 7s that uses the output of the inverter 7 as a signal, and a Q output of the D flip-flop circuit 71 and the D
It consists of an ANDff-) 74 whose input is the inverted output of the Q output of the free-lag flop circuit 73 and whose output is the MOB from the address counter 1.

On the other hand, the timing signal generation circuit 11 supplies the address counter 1 with the first stroke! which receives the check signal and latches the X-axis circumferential data of the memory 3 into the data latch circuit 5. signal Lx, a second step for latching the Y-axis circumferential data of the memory 3 into the data latch circuit 6;
After the settling time of the D/A converter 10 has elapsed following the a-p signal, the signal U is output for a predetermined period. The signal U is generated when the X-axis circumferential data and the corresponding Y-axis circumferential data are read out, and is supplied to the Nordart 15. An example of the timing signal generation circuit 11 is an inverter 1 that inverts a clock signal, as shown in FIG.
11. LSB in address data supplied to memory 3
A D-clip-flop circuit 11 with data input. and D flip-flop f11. D flip-flop circuit 11 capable of outputting, that is, using the second strobe signal as data
It consists of s. The D flip-flop circuit 11s generates a signal U when the X-axis layer data and the Y-axis circumferential data are latched.

Reference numeral 13 denotes a switching circuit that switches the supply and cutoff of a clock signal and the supply and cutoff of a read/book signal (hereinafter referred to as a road reference signal) from the microcomputer using an access signal (high potential) from the microcomputer. , during non-access, that is, while the access signal is at a low potential, the clock signal and substantially the read signal (page signal) are selected. The clock signal outputted via the switching circuit 13 is supplied to the address counter 1 and the timing signal generation circuit 11, and the R/W signal outputted via the switching circuit 13 is supplied to the microcomputer, memory 3, and data bus buffer. 8, and writing and reading are performed using the π/W signal. Furthermore, the access signal is supplied to the multiplexer 2, the data bus buffer 8, and the nordart 15, and the access signal causes the multiplexer 2 to select the output signal from the buffer 4, to make the data bus buffer 8 bidirectionally conductive, and to make the signal U
The output of the Nordart 15 is set to a low potential regardless of the state of the circuit.

Here, the output of the Noah f-) 15 is supplied to a cathode ray tube, which illuminates the display point when at a high potential.

Now, when no access signal is being supplied, the switching circuit 13 outputs a clock signal as shown in FIG. controlled by. At the same time, the count value of address counter 1 is selected by multiplexer 2, and data bus buffer 8 is controlled to a high impedance state.

Therefore, the memory 3 is addressed by the count value of the address counter 1, and data is sequentially read out from the memory 3 according to the address designation. On the other hand, the LSB of the output of the address counter 1 is as shown in FIG. 6(b), and the first strobe signal LX output from the timing signal generation circuit 11 is as shown in FIG. 6(e). , the second strobe signal LY is as shown in FIG. 6(d). As a result, the X-axis layer data (xi) read from the memory 3
is the data latch circuit 5 by the first strobe signal Lx.
The read Y-axis circumferential data (Yl) is latched into the data latch circuit 6 by the second strozo signal LA. The latch output of the latch circuit 5.6 is converted into an analog signal by the A/D converters 9 and 10, and is applied separately as a horizontal deflection signal and a vertical deflection signal to the cathode ray tube to the point to be illuminated. (X,, Y,) is in a defined state.

Further, the output of the Shinoa Kita Dart 15 becomes high potential at the timing shown in FIG. 6(,) due to the signal U from the timing signal generating circuit 11.

Therefore, during the period when the output of the NOR gate 15 is at a high potential as shown in FIG. This operation is performed sequentially, and characters and waveforms corresponding to the character data and waveform data stored in the memory 3 are displayed on the cathode ray tube.

Furthermore, in one embodiment of the present invention, the display switching circuit 7
is provided. Therefore, by setting the signal KBACK to a low potential, the output of the AND/DART 74 will not be at a low potential, and the addressing of the memory 3 will be ``'' Oz z .
.

By setting the signal KBACK to a high potential, the display switching circuit 7 operates in accordance with the MSB data of the address counter 1. That is, if the MSB of the address counter 1 that counts the clock signal is as shown in FIG. ．． The data D is latched at the falling edge of the MSB, and the data D to the D flip-flop 71 is as shown in FIG. 5(b).
The output Q of □ is as shown in FIG. 5(e), and the data D to the D flip-flop 7 is as shown in FIG. 5(d). The output Q of is shown in Figure 5 (,
) as shown. Therefore, the output of the AND gate 74 has a waveform as shown in FIG. 5(f).

As a result, during the high potential period of the waveform shown in FIG. 5(f), the address data becomes "1 z w, , , , z" and the data in the character data area in the memory 3 is read out. During the low potential period, the address data is “” Q x
z,...z'' and the data in the waveform data area in the memory 3 is read out. Therefore,
The character display is 1/4 of the total display period, the waveform display is 3/4 of the total display period, and the waveform display is displayed three times brighter.

Next, when the access signal is supplied, the switching circuit 1
3, the shift/four shift signal is cut off, multiplexer 2 selects the address data from node 4, and data bus buffer 8 is released from the high potential state and becomes bidirectionally connected. At the same time, the output of the Nordart 15 becomes a low potential and the display is stopped. During this time, the contents of the memory 3 can be written or read along with data from the microcomputer.

In this case, since the display is stopped, the display on the cathode ray tube will not be disturbed during writing from the microcomputer.

In the embodiment of the present invention described above, an example is given in which the ratio of data in the waveform data area to data in the character data area is selected to be 1:1. : This ratio does not need to be limited to 1:1, and the display ratio of the display data area does not need to be 174:3h.

In addition, in this embodiment, the MS of the address to the memory 3 is
Although the waveform data area and the character data area are specified by operating B, it is also possible to specify by operating a plurality of pits including the topmost pit.

(Effects of the Invention) As explained above, according to the present invention, on the same cathode ray tube,
When the main display and the auxiliary display are performed, the display ratio of the auxiliary display is made small with respect to the display period of the main display, so that the auxiliary display can be performed while making the main display that is originally desired easy to see.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is an explanatory diagram of memory contents in an embodiment of the present invention. FIG. 3 and FIG. 4 are circuit diagrams showing an example of a display number switching circuit and a timing signal generation circuit in an embodiment of the present invention. 5 and 6 are timing diagrams for explaining the operations of the display count switching circuit and timing signal generation circuit shown in FIGS. 3 and 4. FIG. 1... Address counter, 2... Multiplexer,
3...Memory, 5 and 6...Data latch circuit,
7... Display number switching circuit, 9 and 10... D/A
Converter, 11...timing signal generation circuit. Fig. 4 Fig. 5 Fig. 6 '(a) ゛Yu former'' published lbon ``Goto (e) u-bon-'' L Procedural amendment April 3, 1986 Mr. Michibe Uga, Commissioner of the Patent Office 1. Display of the case Patent Application No. 46288 of 1985 2. Name display circuit of the invention 3. Relationship with the case of the person making the amendment Patent Applicant Address: 2-17-5 Shibuya, Shibuya-ku, Tokyo Name (Name)
359)) Rio Co., Ltd. Representative: Ishizaka-Yoshi 4, Agent: 107 Telephone 498-1587 Address: 5-9-15-7 Minami-Aoyama, Minato-ku, Tokyo Details of the amendment Figure 1 will be amended as attached. . that's all

Claims (1)

[Scope of Claims] Display point data corresponding to display points is sequentially read out from a storage means stored in advance, the read display point data is D/A converted, and the D/A conversion output is used as a deflection signal to an electrostatic deflection cathode ray tube. In the display circuit which specifies the display points by supplying the data as a display point and sequentially illuminates the specified display points, the storage means is connected to a first storage section in which display point data for the main display is stored and display point data for the auxiliary display. and a second storage section in which the address instruction is stored, and further comprising a display number switching means for making the number of address instructions in the first storage section multiple times the number of address instructions in the second storage section. .