JPS62203520U - - Google Patents
Info
- Publication number
- JPS62203520U JPS62203520U JP9268586U JP9268586U JPS62203520U JP S62203520 U JPS62203520 U JP S62203520U JP 9268586 U JP9268586 U JP 9268586U JP 9268586 U JP9268586 U JP 9268586U JP S62203520 U JPS62203520 U JP S62203520U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- output terminal
- power supply
- circuit
- gnd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例を示す回路図、第３
図は本実施例の動作波形、第２図は従来例、第４
図、第５図は従来例の動作波形を示す図である。
ＱＰ１，ＱＰ２，ＱＰ３，ＱＰ４……Ｐチヤン
ネルトランジスタ、ＱＮ１，ＱＮ２，ＱＮ３，Ｑ
Ｎ４……Ｎチヤンネルトランジスタ、ＣＰ１，Ｃ
Ｐ２，ＣＮ１，ＣＮ３……ゲート容量、ＣＯＬ，
ＣＯＨ……容量、Ａ，Ｂ……入力端子、Ｑ，…
…出力端子。
Figure 1 is a circuit diagram showing an embodiment of the present invention;
The figure shows the operating waveforms of this embodiment, the second figure shows the conventional example, and the fourth figure shows the operation waveforms of this embodiment.
5 are diagrams showing operating waveforms of a conventional example. QP 1 , QP 2 , QP 3 , QP 4 ...P channel transistor, QN 1 , QN 2 , QN 3 , Q
N4 ...N channel transistor, CP1 ,C
P 2 , CN 1 , CN 3 ... Gate capacitance, COL,
COH... Capacity, A, B... Input terminal, Q,...
...Output terminal.
Claims (1)
び他方の出力端子とＧＮＤ間に、前記出力端子を
有する各回路の閾値のアンバランスによるゲート
端子と前記電源および前記ＧＮＤへの容量結合を
打消すような容量をそれぞれ接続したことを特徴
とするパワーオンリセツト機能を有するフリツプ
フロツプ回路。 A capacitance is provided between the output terminal of the flip-flop circuit and the power supply and between the other output terminal and GND to cancel the capacitive coupling between the gate terminal and the power supply and the GND due to the unbalance of the threshold values of each circuit having the output terminal. A flip-flop circuit having a power-on reset function characterized in that each of the flip-flop circuits is connected to the other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9268586U JPS62203520U (en) | 1986-06-17 | 1986-06-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9268586U JPS62203520U (en) | 1986-06-17 | 1986-06-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62203520U true JPS62203520U (en) | 1987-12-25 |
Family
ID=30954611
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9268586U Pending JPS62203520U (en) | 1986-06-17 | 1986-06-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62203520U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60114023A (en) * | 1983-11-25 | 1985-06-20 | Nec Corp | Integrated circuit |
-
1986
- 1986-06-17 JP JP9268586U patent/JPS62203520U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60114023A (en) * | 1983-11-25 | 1985-06-20 | Nec Corp | Integrated circuit |
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