JPS62127127U - - Google Patents
Info
- Publication number
- JPS62127127U JPS62127127U JP1280786U JP1280786U JPS62127127U JP S62127127 U JPS62127127 U JP S62127127U JP 1280786 U JP1280786 U JP 1280786U JP 1280786 U JP1280786 U JP 1280786U JP S62127127 U JPS62127127 U JP S62127127U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- capacitor
- schmitt trigger
- input end
- trigger circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 1
Description
第１図は、本考案の一実施例に係るＲ―Ｓ型フ
リツプフロツプの回路図、第２図は、第１図の回
路の回路で用いられるシユミツトトリガ回路の入
出力特性図、第３図は、第１図の回路の各部信号
波形図、第４図は、第１図の回路の各タイミング
における等価回路図、第５図および第６図は、そ
れぞれ本考案の他の実施例を示す回路図である。
Ｑ１，Ｑ２：トランジスタ、Ｒ３，Ｒ４，Ｒ５
，Ｒ６：抵抗、Ｃ：コンデンサ、ＳＷ１，ＳＷ２
：スイツチ、Ｑ３，Ｑ４：トランジスタ（半導体
スイツチ）、ＡＭＰ：演算増幅器、ＩＮＶ：イン
バータ。
FIG. 1 is a circuit diagram of an RS type flip-flop according to an embodiment of the present invention, FIG. 2 is an input/output characteristic diagram of a Schmitt trigger circuit used in the circuit of FIG. 1, and FIG. FIG. 4 is an equivalent circuit diagram at each timing of the circuit in FIG. 1. FIG. 5 and FIG. 6 are circuit diagrams showing other embodiments of the present invention, respectively. It is. Q1 , Q2 : transistor, R3 , R4 , R5
, R 6 : Resistor, C: Capacitor, SW 1 , SW 2
: switch, Q 3 , Q 4 : transistor (semiconductor switch), AMP: operational amplifier, INV: inverter.
Claims (1)
を接続する正帰還回路と、 この入力端を交流的に接地するコンデンサと、
このコンデンサを強制的に充放電するスイツチ回
路と を具備することを特徴とする双安定回路。[Claims for Utility Model Registration] A Schmitt trigger circuit, a positive feedback circuit that connects the output end and the input end of the Schmitt trigger circuit, and a capacitor that grounds the input end in an alternating current manner;
A bistable circuit characterized by comprising a switch circuit that forcibly charges and discharges this capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1280786U JPS62127127U (en) | 1986-01-31 | 1986-01-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1280786U JPS62127127U (en) | 1986-01-31 | 1986-01-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62127127U true JPS62127127U (en) | 1987-08-12 |
Family
ID=30801279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1280786U Pending JPS62127127U (en) | 1986-01-31 | 1986-01-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62127127U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010109571A (en) * | 2008-10-29 | 2010-05-13 | Sanken Electric Co Ltd | Signal processor having latch circuit |
-
1986
- 1986-01-31 JP JP1280786U patent/JPS62127127U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010109571A (en) * | 2008-10-29 | 2010-05-13 | Sanken Electric Co Ltd | Signal processor having latch circuit |