JPS62203360A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62203360A JPS62203360A JP4555186A JP4555186A JPS62203360A JP S62203360 A JPS62203360 A JP S62203360A JP 4555186 A JP4555186 A JP 4555186A JP 4555186 A JP4555186 A JP 4555186A JP S62203360 A JPS62203360 A JP S62203360A
- Authority
- JP
- Japan
- Prior art keywords
- opening
- capacitor
- oxide film
- oxygen
- implanted layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 9
- 239000001301 oxygen Substances 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 5
- -1 oxygen ion Chemical class 0.000 claims abstract description 4
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 abstract description 6
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は高密度の半導体装置の製造方法に関する。[Detailed description of the invention] Industrial applications The present invention relates to a method of manufacturing a high-density semiconductor device.
従来の技術
従来より、溝掘りキャパシタとしているいろな形式のも
のが提案されている。例えば、M、ワダ。BACKGROUND OF THE INVENTION Various types of trenched capacitors have been proposed. For example, M, Wada.
K、ヒエダ、S、ワタナベ、′アフォールデドキャパシ
ターセル(F、C,C0) フォアメガピットDRA
MS’アイイーディーエム(M、Wada、に、Hie
da、S、Watanabe。K, Hieda, S, Watanabe, 'Afolded Capacitor Cell (F, C, C0) Fore Mega Pit DRA
MS'IEDM (M, Wada, Ni, Hie)
da, S, Watanabe.
”A Folded Capacitor Ce1l
(F、C,C,) ForMegabit DRAM
S’ IEDM)p、244 1984などである。”A Folded Capacitor Ce1l
(F, C, C,) ForMegabit DRAM
S'IEDM) p, 244 1984, etc.
これはまず第2図に示すようにシリコン基板11に溝を
掘り、次にボロンイオンを素子分離のために注入し、こ
の溝[CVD法でS 102を埋める。周辺0M03回
路のためにn−wθ11を形成しその後エッチバックし
て必要量の厚さのS i O2膜16を残す。そしてキ
ャパシタ用熱酸化を行ない、ポリシリコン17を埋める
という工程である。As shown in FIG. 2, a groove is first dug in the silicon substrate 11, then boron ions are implanted for element isolation, and the groove [S102] is filled by the CVD method. For the peripheral 0M03 circuit, n-wθ11 is formed and then etched back to leave the SiO2 film 16 of the required thickness. Then, thermal oxidation for the capacitor is performed to fill the polysilicon 17.
発明が解決しようとする問題点
従来例において、エッチパックで得られるS 102の
厚さにばらつきがあり、時に深い溝で形成するのは困難
であった。Problems to be Solved by the Invention In the prior art, the thickness of the S 102 obtained by etch packs varied, and it was sometimes difficult to form deep grooves.
問題点を解決するだめの手段
本発明は上記問題点を解決するために半導体基板に作ら
れた溝底部に酸素イオンを注入し、その後通常通りにキ
ャパシタ用熱酸化膜を形成しボリシリコンを埋め込むこ
とによりキャパシタを作製する。Means to Solve the Problems In order to solve the above problems, the present invention injects oxygen ions into the bottom of a groove formed in a semiconductor substrate, and then forms a thermal oxide film for a capacitor as usual and embeds polysilicon. A capacitor is produced by this.
作 用
キャパシタ底面は酸素イオン注入と熱処理により形成さ
れた酸化層のためこの部分での電界集中がない。また側
壁イオン注入の際にこのイオンが溝底部の基板部分にた
まることが防げる。このことにより信頼性の高いキャパ
シタを作ることができる。The bottom surface of the working capacitor is an oxide layer formed by oxygen ion implantation and heat treatment, so there is no electric field concentration in this area. Furthermore, during sidewall ion implantation, these ions can be prevented from accumulating in the substrate portion at the bottom of the groove. This allows a highly reliable capacitor to be produced.
実施例
第1図は本発明の一実施例を示す工程断面図である。第
1図(a)で1はP型シリコン(100)基板で比抵抗
は〜10Ω・口、2はCVD法で作製したシリコン酸化
膜である。シリコン酸化膜はキャパシタを作製する領域
は覆われていない。このシリコン酸化膜はエツチング、
イオン注入のマスクとして働くものである。第1図(b
)はシリコン酸化膜をマスクとしてシリコン基板をエツ
チングし、開口部3を形成したものである。(c)はチ
ャンネルストッパとして開口部底部にポロンを打ち込ん
だものである。4はイオン注入層である。(C)図は開
口部底部に酸素イオン注入を行ない、5.酸素注入層を
形成する。次に(e)図に示すように炉で熱処理するこ
とにより5.酸素注入層が6.シリコン酸化層になる。Embodiment FIG. 1 is a process sectional view showing an embodiment of the present invention. In FIG. 1(a), numeral 1 is a P-type silicon (100) substrate with a resistivity of about 10 Ω, and numeral 2 is a silicon oxide film produced by the CVD method. The silicon oxide film does not cover the area where the capacitor will be made. This silicon oxide film is etched,
This serves as a mask for ion implantation. Figure 1 (b
), the silicon substrate is etched using a silicon oxide film as a mask to form an opening 3. In (c), a poron was driven into the bottom of the opening as a channel stopper. 4 is an ion implantation layer. (C) The figure shows oxygen ion implantation at the bottom of the opening.5. Form an oxygen implantation layer. 5. Next, heat treatment is performed in a furnace as shown in the figure (e). The oxygen injection layer is 6. It becomes a silicon oxide layer.
(f)図は開口部に斜めイオン注入を行ない側面に注入
層を形成する。次に(q)図に示すように酸化雰囲気中
で酸化することにより8.酸化層を形成する。この厚さ
はキャパシタ容重を決定するが数百オングストローム−
百オングストローム程度である。次に電極である9、ポ
リシリコンを埋めることによりキャパシタが形成される
。In the figure (f), oblique ion implantation is performed into the opening to form an implanted layer on the side surface. Next, (q) 8. is oxidized in an oxidizing atmosphere as shown in the figure. Forms an oxide layer. This thickness, which determines the capacitor capacity, is several hundred angstroms
It is about 100 angstroms. Next, a capacitor is formed by filling the electrode 9 with polysilicon.
発明の効果
本発明によって、従来電界集中し易かっだトレンチキャ
パシタ底部に他の側面より庫い酸化膜が形成されるので
電界集中はおこらない。従って信頼性の高いキャパシタ
が形成できる。また側面注入の際の反射イオンがシリコ
ン酸化層でストップするためにチャンネルストッパ用イ
オンの効果を打ち消すことがない。Effects of the Invention According to the present invention, an oxide film is formed at the bottom of the trench capacitor, where electric field concentration tends to occur in the past, which is stronger than on the other side surfaces, so that electric field concentration does not occur. Therefore, a highly reliable capacitor can be formed. In addition, since reflected ions during side implantation are stopped at the silicon oxide layer, the effect of the channel stopper ions is not negated.
第1図佃暉→は本発明の一実施例における半導体装置の
製造方法を説明するための工程断面図、第2図は従来の
製造方法を説明するだめの工程断面図である。
1・・・・・・P型シリコン基板、2・・・・・・シリ
コン酸化膜、3・・・・・・開口部、4・・・・・・イ
オン注入層、6・・・・・・酸素注入層、6・・・・・
・酸化層、了・・・・・注入層、8・・・・・・酸化膜
、9・・・・・・ポリシリコン。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図
第1図
第2図
13開口坪
17ポソンソコンFIG. 1 is a process sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process sectional view for explaining a conventional manufacturing method. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Silicon oxide film, 3... Opening, 4... Ion implantation layer, 6...・Oxygen injection layer, 6...
・Oxide layer, end...Injection layer, 8...Oxide film, 9...Polysilicon. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1 Figure 2 Figure 2 13 Opening area 17 tsubo
Claims (1)
ける工程と、前記半導体基板をエッチングし溝を作る工
程と、前記半導体基板にチャンネルストッパ用イオンを
注入し、次に酸素イオン注入を行う工程と、前記半導体
基板を熱処理する工程と、酸化雰囲気中で熱処理する工
程と、埋め込み導体層を形成する工程とを含んでなる半
導体装置の製造方法。a step of providing a mask material in a portion of the semiconductor substrate other than the capacitor region; a step of etching the semiconductor substrate to form a groove; a step of implanting channel stopper ions into the semiconductor substrate, and then implanting oxygen ions; A method for manufacturing a semiconductor device, comprising the steps of heat treating the semiconductor substrate, heat treating the semiconductor substrate in an oxidizing atmosphere, and forming a buried conductor layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4555186A JPS62203360A (en) | 1986-03-03 | 1986-03-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4555186A JPS62203360A (en) | 1986-03-03 | 1986-03-03 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62203360A true JPS62203360A (en) | 1987-09-08 |
Family
ID=12722496
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4555186A Pending JPS62203360A (en) | 1986-03-03 | 1986-03-03 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62203360A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04144271A (en) * | 1990-10-05 | 1992-05-18 | Nec Corp | Manufacture of semiconductor device |
-
1986
- 1986-03-03 JP JP4555186A patent/JPS62203360A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04144271A (en) * | 1990-10-05 | 1992-05-18 | Nec Corp | Manufacture of semiconductor device |
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