JPS6220200A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To speed up operation by providing a cut-off MOSFET between a load MOSFET and a drive MOSFET constituting a logic circuit. CONSTITUTION:The cut-off MOSFET Q21 is provided between the drive MOSFET Q22 and the load MOSFET Q23, and the drive MOSFET directly extracts a low-level voltage from the high-level voltage of the input node potential of a level converter circuit to make the extracted voltage an output signal to convert a signal of comparatively low level formed by the logic circuit to the one of high level. Accordingly, the delay time of the propagation of the signal, such as level-extraction through the cut-off MOSFET Q21 does not occur. As a result, the operation is speedified.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, such as an EPROM (Electrically Programmable Circuit Device).
This relates to technology that is effective for use in read-only memory (read-only memory).

[Background technology]

E with FAMO3 (Floating Gate Avalanche Injection MO3) transistor as a memory element
PROM devices are known (for example, Japanese Patent Laid-Open No. 54-15
(See Publication No. 2933).

In addition, the peripheral circuits of the EPROM device are CMO3 (complementary type M
O3) is known to be configured by a circuit (for example,
ISSCCDIGEST OF TECHNICAL PAPERS
CHNICAL PAPER 3) pages 182-183.
(Reference: February 11, 1982).

In this way, the peripheral circuit is constituted by the 0M03 circuit. Word lines (or data lines, etc.) in EPROM devices
As a selection circuit, a circuit as shown in FIG. 3 can be considered. This circuit consists of a P-channel MOSFET type load M
OSFETQ30 and N-channel drive MOSFET
Q31. A decoded output signal is formed by a logic gate circuit composed of Q32, and a cut MO8FE whose gate is constantly supplied with a power supply voltage Vcc.
It is supplied to the input terminal of a word line drive circuit having a level conversion function via TQ33. This word line drive circuit is
P-channel MOSFET Q34 and N-channel MOS
FETQ35, and a P-channel MOS F which is provided between the input terminal of this CMOS inverter circuit and the power supply terminal vpp and operates in response to the output signal of the CMOS inverter circuit.
It is composed of ETQ36. Note that the power supply terminal VPP is supplied with a high write voltage during a write operation, and is supplied with a relatively low internal power supply voltage Vcc during a read operation, by a voltage switching circuit such as that shown in the above-mentioned document, for example. .

In this circuit, during a write operation, a high voltage such as about 12V is supplied to the power supply voltage terminal vpp. In this state, when the decode output signal forms a high level (5■) non-selection signal such as the power supply voltage Vcc, the high level is transmitted to the input terminal of the CMOS inverter circuit via MOSFET Q33. MOSFETQ35 is turned on. In response to this, its output is set to a low level, so that the P-channel MOSFET Q36 is turned on, and the input terminal of the CMOS inverter circuit is brought to a high voltage Vl)P, so that the P-channel MOSFET Q34 is turned off. This turns the cut MOSFET Q33 off. Therefore, the above P-channel MOSFETQ36
This can prevent direct current from flowing from the high voltage Vpp side to the low voltage Vcc side through the capacitor.

Next, when the decode output signal forms a selection signal of low level (0■), MOS FETQ33 is turned on again, pulls out the level of the input terminal of the CMOS inverter circuit to low level, and outputs the P-channel MOSFET.
Turn on ETQ34, turn on N-channel MOSFETQ
35 to the off state. This causes the output signal to be at a high level such as the high voltage vpp. Note that the P-channel MOSFET Q36 is turned off by the high level of the output signal.

In this circuit, since the decoded output signal is transmitted through the transmission gate MOSFET Q33, the signal delay time is increased accordingly, resulting in slower memory access.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device that operates at high speed.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by providing a cut MOSFET between the load MOSFET and the drive MOSFET that make up the logic circuit, the drive MOSFET can directly pull out the input signal of the drive circuit, which has a level conversion function, to a low level and select a high level. It forms a signal.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the memory array section of an EPROM to which the present invention is applicable. In the EPROM device of this embodiment, complementary address signals formed through an address buffer receiving X and Y address signals supplied from external terminals (not shown) are sent to an address decoder D.
Supplied to CR. In the figure, the address buffer and address decoder are in the same circuit block XADB-DCR,
Each is designated as YADB-DCR. The address buffers XADB and YADB form a complementary address signal consisting of an internal address signal in phase with the address signal supplied from an external terminal and an address signal in opposite phase. Address decoder DCR(X) forms a selection signal for word line W of memory array M-ARY according to its complementary address signal. Address decoder DCR(Y) outputs memory array M-AR according to its complementary address signal.
A selection signal for the Y data line is formed.

The memory array M-ARY is composed of a plurality of FAMO3) transistors (non-volatile memory elements: MOS FETQ 1 to Q6) shown as a representative, word lines Wl, W2, and data lines D1 to Dn. has been done. In the memory array M-ARY, F AMOS transistors Q1 to Q3 (
The control gates of the FAMO3I-transistors Q1, Q4-Q3 . Q
The drains of No. 6 are connected to the corresponding data lines D1 to Dn, respectively.
It is connected to the. Although not particularly limited, the common source line C8 of the FAMOS transistors is a depletion type MOSFET QI which receives an internal write signal W1-.
It is grounded via O. Each of the above data lines D1 to Dn
is a column selection switch MOS that receives a selection signal generated by the address decoder DCR(Y).
It is connected to common data line CD via FETs Q7 to Q9.

The common data line CD is connected to an external terminal I10 on one side.
It is connected to the output terminal of a write data input buffer DIB which receives a write signal input from the write data input buffer DIB. The common data line CD has a data output buffer D including a sense amplifier SA on the other side.

Connected to the input terminal of B. This data output buffer D
The output terminal of OB is connected to the external terminal I10.

The control circuit C0NT receives a program signal PGM, an output enable signal OE, and a chip selection signal CE supplied from an external terminal, and forms control signals necessary for the operation of the internal circuit. Note that when the program signal PGM is set to a low level, the write operation mode is set, and, although not particularly limited, the high voltage vpp formed by the internal booster circuit Vpρ-G is switched through a voltage switching circuit included in the control circuit C0NT. The above address decoder
It is supplied to CR, YDCR, and the power supply terminal VPP of the data input buffer DIB. On the other hand, when the program signal PGM is set to high level, the read mode is set, and the address decoder XDCR is controlled by the voltage switching circuit.
, YDCR and the power supply terminal v of the data input buffer DIB
An internal power supply voltage νcc of about 5V is supplied to pp.

FIG. 2 shows a circuit diagram of one embodiment of a word line drive circuit (level conversion circuit) used in the above EPROM device. This embodiment circuit is formed together with the above-mentioned EFROM on a semiconductor substrate such as single crystal silicon by, for example, a known CMO3 semiconductor integrated circuit manufacturing technique.

In the following description, unless otherwise specified, MOSFE
'l' (insulated gate field effect transistor) is an N-channel MOS FET.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
The FET has a source region, a drain region formed on the surface of the semiconductor substrate, and a gate made of polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region with a thin gate insulating film interposed therebetween. Consists of electrodes. The P-channel MOSFET is formed in an N-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOSFETs formed thereon. The N-type well region constitutes the base gate of the P-channel MOSFET formed thereon.

Although the unit selection circuit is not particularly limited, it may be a NAND circuit that receives an output signal from a pre-decoder circuit (not shown).
A gate circuit and a drive circuit (level conversion circuit) that forms a word line drive signal according to the gate circuit's output signal.
Consisted of.

The above Nant gate circuit is 1. is turned on steadily by having its gate coupled to the ground potential of the circuit;
P-channel type load MOSF acting as resistance means
ET, and a series T-channel drive MOSFET Q22.ET that receives the predecode output (not shown). Q
23 and the drive MO3FE'f'Q22 and the load M
The MOSFET Q21 is provided between the OSFET Q21 and is composed of an N-channel cut MOSFET Q21 whose gate is constantly supplied with the power supply voltage Vcc. This Nant gate circuit consists of the drive MOSFET Q22 and the cut MOSFET Q22.
An output signal is formed from the connection point of OSFETQ21.

The word line selection/non-selection signal formed by this Nant gate circuit is supplied to the next word line drive circuit having a level conversion function. In other words, the output signal of the Nandt gate circuit is
channel MOSFET Q25, and is activated by the voltage supplied from the Al source terminal VPP.
It is supplied to the input terminal of the MOS inverter circuit. This C
The output terminal of the MOS impark circuit is connected to the memory array M-
It is coupled to one word line Wl of ARY. The above CMO
A P-channel feedback MOSFET Q36 whose gate is coupled to the output terminal (word line Wl) of the CMOS inverter circuit is provided between the input terminal of the S inverter circuit and its power supply terminal vpp.

Note that the voltage switching circuit supplies the power supply terminal Vl)P with a high writing voltage of about 12V during a write operation, and a relatively low internal power supply voltage of about 5V during a read operation. Vcc is supplied.

In this circuit, during a write operation, a high voltage such as about 12V is supplied to the power supply voltage terminal Vp1). In this state, the decode output signal is connected to the power supply voltage Vcc.
If we form a high-level (5■) non-selected number like
In other words, drive MOSFET Q22 or Q23
When either of the load MOSFETQ20 is in the off state
A high level non-selection signal is transmitted to the input terminal of the CMOS inverter circuit via the cant MOSFET Q21.

As a result, N-channel M of the CMOS inverter circuit
O8FETQ25 is turned on. In response to this, its output is set to low level, so the P-channel MOS
FETQZ6 is turned on and the input terminal of the CMOS inverter circuit is brought to a high voltage Vρρ. The above high voltage vpp
Due to the high level, P-channel MOSFET Q24 of the CMOS inverter circuit is turned off.

Furthermore, as a result of the level of the input terminal of the CMOS inverter circuit being set to the above-mentioned high voltage vpp, the cut MOSFET Q21, which had been turned on, is turned off. Therefore, the above P-channel MOSFETQ2
6, it is possible to prevent direct current from flowing from the high voltage Vpp side to the low voltage Vcc side.

Next, according to the predecode output, drive MOSFETQ2
2 and Q23 are turned on, the low level (Ov
) selection signal is output. This low level output signal causes the N-channel MO of the CMOS inverter circuit to
SFETQ25 is in off state, P-channel MOSFE
TQ24 is switched on. Note that due to the on-state of the P-channel MOSFET Q24, the potential of the word line W1 is raised to a high voltage Vl), so the feedback P-channel MOSFET Q26 is turned off.

In this circuit, when switching the word line W1 from a non-selected state to a selected state, in other words, the CMOS
When pulling the potential of the input terminal of the inverter circuit from the high voltage Vl)P to the ground potential of the circuit, the direct drive M
Since it is performed by OSFETQ22゜Q23,
The potential of the word line can be raised from a non-selected level to a selected level at high speed.

Note that the column switch MOSFET that selects the data line
The circuits that form the selection signals supplied to the gates of Q7 to Q9 and the switching control signals between the high voltage vpp and the power supply voltage Vcc are also constructed by the similar circuits.

〔effect〕

As an output signal for converting a relatively low level signal formed by a +n logic circuit into a high/bell signal,
~10 SFETs for cant are provided between the drive MOSFET and the load MOSFET, and the drive MOSFET
', the potential of the input node of the level conversion circuit is directly pulled from the high level of the high voltage to the low level. This eliminates the signal propagation delay time required to extract the above-mentioned level via the cut MOSFE'I'', thereby achieving the effect of speeding up the operation.

(2) According to (1) above, P-channel MOSFET and N-channel MOSFET in the level conversion circuit
Since switching can be performed at high speed, it is possible to reduce the generation of through current flowing from the high voltage terminal to the ground potential of the circuit.

(3) Since the logic gate circuit forming the decoder circuit and the drive circuit having a level conversion function can be connected by a single signal line, the wiring layout can be simplified. That is, in order to speed up the word line selection operation, for example, in the circuit shown in FIG.
It is also possible to connect to the gate of ETQ35. In this case, the P-channel MO of the CMOS inverter circuit
MOSFETQ3 for cutting is installed at the gate of SFETQ34.
3 through which the output signal will be transmitted. Therefore, it is necessary to connect the logic gate circuit and the word line drive circuit with two wires for each unit selection circuit provided corresponding to the word line of the memory array configured in high density. It becomes complicated.

Although the present invention has been specifically described above based on Examples, it goes without saying that this invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the spirit thereof. For example, in the embodiment of FIG. 2, the load MOS
FET is replaced with P channel MOS FET,
Uses a depletion type N-channel MOS FET or a cut MOSFET as a load MO
It may also be used in common as an SFET. Further, the high voltage vpp, which is higher than the relatively low power supply voltage Vcc, may be formed by an internal circuit or may be supplied from an external terminal.

Furthermore, the memory array M-ARY and other peripheral circuits of the EPROM device to which this invention is applicable can take various embodiments.

[Application field]

In the above explanation, the present invention was mainly applied to EFROM, which is the technical field behind it, but it is not limited to this, and for example, MNOS.
EEPROM (Electrically Erasable Programmable Read Only) with (Metal Nitride Oxide Semiconductor) as a memory element
The present invention can be widely used in various IN semiconductor integrated circuit devices that operate a level conversion circuit that converts an output signal of a circuit operating at a relatively low power supply voltage into a signal at a higher voltage level, such as a memory (memory).

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a main part showing an embodiment of an EPROM device to which the present invention is applied. FIG. 2 is a circuit diagram showing an embodiment of the word line selection circuit. FIG. 2 is a circuit diagram showing an example of a selection circuit considered prior to the invention. XADB-DCR, YADB-DCR...address buffer/address decoder, M-ARY...memory array, DIB...data person cover sofa, DOB...data output cover sofa, C0NT...control circuit, vpp-c...
・Internal boost circuit−〉・ Patent attorney Katsuma Ogawa (1151,゛＼ゝ÷

Claims (1)

[Claims] 1. A cutting MOSFET that is provided between a load means and a drive MOSFET and whose gate is constantly supplied with a power supply voltage.
SFET, MOSFET for this cut, and drive MOSF
A CMOS is supplied with an output signal obtained from a connection point of an ET, and is brought into an operating state by a voltage at a power supply terminal to which a high voltage for writing or a relatively low voltage is selectively supplied depending on its operating mode. An inverter circuit and an output signal of the CMOS inverter circuit are received, and the CMOS
A semiconductor integrated circuit comprising: a level conversion circuit provided between an input terminal of the S inverter circuit and the power supply terminal, and comprising a feedback MOSFET of the same conductivity type as a MOSFET on the power supply voltage side of the CMOS inverter circuit. circuit device. 2. The output signal of the level conversion circuit forms a selection signal for a word line and a data line of a memory array composed of memory cells in which a write operation is electrically performed. A semiconductor integrated circuit device according to scope 1. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the memory cell is a FAMOS transistor.