JPS6148196A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To make an action highly speedy by installing a capacity cut MOSFET and using a control signal seperated from a load circuit of a word wire, etc. CONSTITUTION:When a stage circuit G composing an address decoder XDCR forms a high level non-selecting signal like power source voltage Vcc, an N channel MOSFETQ18 of a CMOS invertor circuit is on. At this time, when an output signal of the gate circuit G is set to a high level like power source voltage Vcc, a cut MOSFETQ16 is off. On the other hand, by a P channel MOSFETQ17 which is still on, gate voltage of a P channel MOSFETQ14 is set to a low level. Thus, since the P channel MOSFETQ14 is on and high voltage Vpp is applied to a gate of a P channel MOSFERQ15, the P channel MOSFETQ15, is set to off and a word wire W is set to a low level non-selecting condition.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to technology effective for use in EPROM (Electrically Programmable Read Only Memory).

[Background technology]

E with FAMO3 (Floating Gate Avalanche Injection MO5) transistor as a memory element
PROM devices are known (for example, Japanese Patent Laid-Open No. 54-15
(See Publication No. 2933).

In addition, the peripheral circuit of the EPROM device is changed to 0MO5 (complementary type M
O3) circuit is known to generate tq (for example, l5SCCDIGEST 0FTECHNICAL
PΔP E RS, Kai 182-183 1982
).

In this way, the peripheral circuit is composed of the 0M03 circuit. As a word line (or data line, etc.) selection circuit in the +4 device, a circuit as shown in FIG. 3 can be considered. Address decoder XVCR receives an address signal from an address decoder (not shown) and forms a word line selection signal. This output signal is generated by a cut MOS whose gate is constantly supplied with the power supply voltage Vcc.
It is supplied to the input terminal of the word line drive circuit via FETQ24. This word line drive circuit is a P-channel MO
It is composed of a CMOS inverter circuit composed of SFETQ21 and N-channel MOSFETQ23. A P-channel MOSFET Q20 that operates upon receiving the output signal is provided between the input terminal of this CMOS impark circuit and the power supply voltage terminal vpp. In addition,
For example, a high voltage for writing is supplied to the power supply terminal PP during a write operation, and a relatively low internal power supply voltage Vcc is supplied during a read operation, by a voltage switching circuit as shown in the above-mentioned document, for example. .

In this circuit, during a write operation, a high voltage such as about 12V is supplied to the power supply voltage terminal (VPI). In this state, is the address decoder XDCR? l!
When a high level (5■) non-selection signal such as the voltage Vcc is formed, the CMOS
Since the signal is transmitted to the input terminal of the inverter circuit, the N-channel MOSFET Q23 is turned on. At this time,
The output signal of the address decoder XDCR is the voltage Vcc.
Cant MOSFETQ when taken to a high level such as
24 is turned off. Therefore, due to the low level of the word line W formed by the ON state of the N-channel MOSFET Q24, the P-channel MOSFET Q24 is turned on.
MOSFET Q20 is turned on and the input signal of the CMOS inverter circuit is set to a high level such as high voltage VPp. As a result, the P-channel MOSFET Q21 constituting the CMOS inverter circuit is turned off. Next, when the Atonenos decoder XDCR forms a low level (OV) selection signal such as the ground potential of the circuit,
Cut MOSFET Q24 is turned on again and CM
The level of the input terminal of the OS inverter circuit is set to low level and the voltage is exceeded. At this time, the P-channel λl03FET Q21 of the CMOS impark circuit is turned on by pulling it to the low level, but since a large number of memory cells are connected to the word line V/, it has a relatively large capacitance value. Has parasitic capacitance. therefore,
Since the rise of the word line to the /f level is delayed, the P-channel MOSFET Q20 remains on during this time, causing a through current to flow between it and the address decoder X0CR. Since the internal booster circuit vpp-c forming the high voltage Vl)I) has a small current supply capability, the generation of the above-described through current causes the voltage level of the high voltage Vl)P to drop. When such a voltage level drop occurs, the memory array M-AR
Since the level of selectors in Y is reduced, the writing efficiency of the memory cell is deteriorated.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device that operates at high speed.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief summary of typical inventions disclosed in this application is as follows.

That is, a capacitor cuff 1 is connected between a power supply voltage side MOSFET that constitutes a CMOS inverter circuit that forms a drive signal according to a selection signal formed by a decoder circuit and a power supply voltage terminal to which a high voltage is supplied in abundance. -MOS
FET is provided, and this MO'5FET and the above CMOS
The MOSFET which supplies the power supply voltage terminal to the input terminal of the CMOS inverter circuit is controlled by the voltage at the connection point with the MOSFET forming the inverter circuit.

〔Example〕

FIG. ff11 shows a circuit diagram of an embodiment of a word line selection circuit and an internal booster circuit used in the semiconductor memory device according to the present invention. This embodiment circuit is not particularly limited, but may be incorporated in an EPROM as described later, for example, a well-known CD, (the above-mentioned EFR is printed on a semiconductor substrate such as single-crystal silicon using the BY manufacturing technology of an OS semiconductor integrated circuit).
Formed together with OM. In the following description, unless otherwise specified, the MOSFET (insulated gate field effect transistor) is an N-channel MO3FET.

In addition, in the figure, the MO9FET with a straight line added between the source and drain is a P-channel type (FIG. 3 also shows a P-channel MO5FET using the same representation method).

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
The FET consists of a source region and a drain region formed on the surface of the semiconductor substrate, and a polysilicon film formed on the semiconductor substrate surface between the source region and the drain region with a thin gate insulating film interposed therebetween. It consists of a gate electrode. The P-channel MO3FET is formed in an N-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MO5FETs formed thereon. The N-type well region constitutes the substrate cage of the P-channel MO5FET formed thereon.

In the internal booster circuit vpp-c, a pulse signal O3C generated by an oscillation circuit (not shown) is supplied to the input of the first CMOS inverter circuit IVI. The output of this inverter circuit IVI is supplied to the input of a second CMOS inverter circuit. As a result, the first. 2nd CMOS
Complementary pulses are formed from the output terminals of inverter circuits IVI and IV2. The output of the second inverter circuit fV2 is a diode-type MOS FET.
It is supplied to one electrode of the capacitor CI via Qll. The output of the first inverter circuit IVI is supplied on one side to the other electrode of the capacitor C1.

The boosted voltage formed by the capacitor C1 is transferred to the capacitor C through a diode-type MOSFET Q12.
is supplied to one electrode of 2. Number 2 above! The output of the inverter circuit IV2 is connected to the capacitor C2 on the other hand.
is supplied to the other 714'Fa. This capacitor C
The boosted voltage formed by 2 is a diode type MOS
The voltage is supplied to the boosted voltage terminal V9p, which is one electrode of the capacitor C3, via the FET Q13. This capacitor C
The other electrode of 3 is coupled to the ground potential point of the circuit.

The outline of the operation of the booster circuit of this embodiment is as follows. The output of inverter circuit IV2 is high level (Vcc)
At the time, the output of the inverter circuit Iv1 is low level (Ov
), and the above-mentioned high-level charge-up operation is performed on the capacitor C1.

Next, the inverter circuit IV2. When the output of IV1 is inverted, the capacitor C
One of the y1 pins of the voltage booster 1 is boosted and transmitted to the capacitor C2. The voltage of this capacitor C2 is further boosted by the bootstrap action when the inverter circuit IV2 is at a high level and is transmitted to the capacitor C3. By repeating such operations, a boosted voltage Vpρ approximately three times the power supply voltage Vcc is applied to the capacitor C3.

Strictly speaking, the MOSFET QI in the diode form is
The threshold voltages at I to Q and 13 appear as level loss.

The boosted voltage VpP thus formed is supplied as a high voltage for writing and as an operating voltage of the next selection circuit. Note that the selection circuit is supplied with the above-mentioned high voltage Vpl during a write operation, and is supplied with the internal power supply voltage Vcc during a read operation. As such a voltage switching circuit, for example, a circuit as shown in the above-mentioned document can be used. In this embodiment, the voltage switching circuit described above is omitted.

The unit selection circuit is not particularly limited, but is composed of a NOR (NOR) gate circuit G that receives an address signal, and a drive circuit that forms a word line drive signal in accordance with the selection signal of this gate circuit G. .

In this embodiment, the word line selection/non-j five selection signal formed by the -F gate circuit G is directly applied to the P-channel MOSFET, TQ17 and the N-channel MOSFET Q.
It is supplied to the input of a CMOS inverter circuit composed of 18 and 18. The output terminal of this CMOS inverter circuit is
It is coupled to one word line W of memory array M-ΔRY.

The P-channel MOSFET Q17 on the power supply voltage side of the CMOS inverter circuit is connected to the power supply voltage terminal ψpp via a P-channel type capacitor MOSFET Q15.
connected to. The input terminals of the CMOS impark circuit are an N-channel MOSFET Q16 whose gate is constantly supplied with a power supply voltage Vcc, a P-channel MOSFET F, (OS
It is connected to the power supply voltage terminal Vpp via FETQ 14. The gate of this P-channel MOSFET QI4 is coupled to the connection point between the MOSFETs Q15 and Q17. The gate of P-channel MOSFET QI5 is coupled to the connection point between MOSFETs Q14 and Q16. Note that the memory array M-ARY will be described in detail later.

The operation of the selection circuit of this embodiment circuit will now be described. In a write operation in which the selection circuit is brought into operation by the high voltage vpp generated by the booster circuit Vpp-G, the gate circuit G forming the address decoder XDCR is
When the output voltage forms a non-selection signal of high level (5■) like the power supply voltage VCC, the N-channel MOSFET Q18 of the CMOS inverter circuit is turned on. At this time, when the output signal of the gate circuit G is set to a high level such as the power supply voltage Vcc, the cut MOSFET QI 6 is turned off. On the other hand, depending on the high level as described above, the P-channel MOSF remains in the on state.
By ETQI 7, P-channel MOSFETQI
The gate voltage of No. 4 is set to low level. This results in
P-channel MOSFET Q14 is turned on and transmits high voltage VPP to the gate of P-channel MOSFET Q15, so that P-channel MOSFET Q15 is turned off. Therefore, the word line W is set to a low level non-selected state.

In this embodiment, the output of the gate circuit G constituting the address decoder To,
A CMOS inverter circuit can be driven without any level loss due to the threshold voltage.

Next, when the gate circuit G constituting the address decoder XDCR forms a selection signal of low level (0), such as the ground potential of the circuit, the input of the CMOS inverter circuit is pulled to the low level.

At this time, the cut MOSFET QI 6 is turned on by the low level of the input signal of the CMOS impark circuit, and the low level due to the pullout operation is turned on by the MOS)'E
'I' is transmitted to the gate of Q15. This turns P-channel MOSFET QI 5 on. Therefore, along with the on-state of P-channel MOSFET Q15, P-channel MOSFET QI 7, which is turned on due to the low level of the input signal, The word line W is charged and amplified to a high voltage level.At this time, M
Since the potential at the connection point between OSFETs Q15 and Q17 has only a small parasitic capacitance, it is quickly raised to a voltage such as high voltage Vpp. This allows P-channel MOSFE
TQI 4 is immediately turned off. by this,
Generation of through current between MOSFET Q14 and gate circuit G forming address decoder XDCR can be substantially prevented.

FIG. 2 shows a circuit diagram of an embodiment of the memory array section of an EPROM to which the present invention is applied. In the EPROM device of this embodiment, complementary address signals formed through an address buffer receiving X and Y address signals supplied from external terminals (not shown) are supplied to an address decoder DCH. Circuit block XADB-D in which the buffer and address decoder are the same
CR, YADB-DCR, respectively. The address buffers XADB and YADB form a complementary address signal consisting of an internal address signal in phase with the address signal supplied from the external terminal and an address signal in opposite phase. Address decoder DCR(X) forms selection number 18 of word line W of memory array M-ARY according to its complementary address signal. address decoder dc
R(Y) forms a selection signal for the data line of memory array M-ARY according to its complementary address signal.

The memory array M-ARY is composed of a plurality of I"AMO5I-ranjisku (non-volatile memory elements...MOSFETQ1 to Q6) shown as a representative, word lines Wl, W2, and data lines D1 to Dn. In the memory array M-ARY, FAMOS transistors Q1 to Q3 (
The control gates of Q4-Q6) are connected to the corresponding word IfAw1 (W2), respectively, and the control gates of the FAMO3) rundisks Ql, Q4-Q3. Q
The drains of No. 6 are connected to the corresponding data lines D1 to pn, respectively.
It is connected to the. Also, the gummy FAMOS transistor Q19. The drains of Q20 are commonly connected. Above F
Although not particularly limited, the common source line CS of the AMOS transistors is grounded via a depletion type MOSFET Q10 that receives an internal write signal we. Each of the data lines D1 to pn is connected to the address decoder D.
Through column selection switch MOSFETs Q7 to Q9 that receive the selection signal formed by CR(Y),
Connected to common data line CD.

The common data line CD is connected to an external terminal I10 on one side.
It is connected to the output terminal of a data manual buffer DIB for writing which receives a write signal input from the input buffer DIB. The common data lJI CD is connected to an input terminal of a data output buffer DOB including a sense amplifier SA on the other hand. The output terminal of this data output buffer DOB is connected to the external terminal 110.

The control circuit C0NT receives a program signal PGM, an output enable signal OE, and a chip selection signal CE supplied from an external terminal, and forms control signals necessary for the operation of the internal circuit. Note that when the program signal PGM is set to low level, the write operation mode is entered, and the high voltage v formed by the internal booster circuit VpI)-G is
pp is supplied to the address decoders XDCR, YDCR and data manual buffer DIH via a voltage switching circuit included in the control circuit C0NT. On the other hand, when the program signal PGM is set to high level, the read mode is set, and the internal power supply voltage Vcc is supplied to the address decoders XDCR, YDCR and data cover DIB by the voltage switching circuit.

〔effect〕

(MOSFET for converting a relatively low level signal formed by the 11 decoder circuit into a high level signal)
As a control signal, a signal is used that is separated from the load circuit side such as a word line by providing a capacitive MOSFET. Thereby, the switching can be performed at high speed, so that it is possible to prevent the generation of through current flowing from the high voltage terminal to the decoder circuit. Therefore, it is possible to prevent the internal boosted voltage from decreasing, and as a result, it is possible to improve the writing efficiency, in other words, to speed up the operation.

(2) By directly supplying the selection signal formed by the decoder circuit to the input of the CMOS inverter circuit serving as the drive circuit, it is possible to achieve the effect of speeding up the switching operation to non-selection.

Although the present invention has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. , in the embodiment of FIG. 1, a cut MOSFE that cuts the high level signal of the address decoder
TQ16 is the address decoder (G) output and CMOS
It may also be provided between the input of the inverter circuit. In addition, the memory array M-ARY and other peripheral circuits are
Various embodiments can be adopted.

[Application field]

In the above explanation, the present invention was mainly applied to EPROM, which is the technical field behind the present invention, but the present invention is not limited to this.For example, MNOS (metallic - It can be widely used in semiconductor storage devices such as EEPROMs (Electrically Erasable Programmable Read Only Memories) that use nitride oxide semiconductors as storage elements.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of an EPROM to which this invention is applied, and FIG. 3 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of a circuit. XADB-DCR, YADB-DCR...Address buffer/address decoder: 5", M-ARY...Memory array, SA...Sense amplifier, DIB...Data input cover sofa, DOB...Data output cover sofa, MA...Main Amplifier, C0NT...control circuit, Vpp-G...internal booster circuit, G...Nor gate circuit, IVl, IV2...
CMOS inverter circuit

Claims (1)

[Claims] 1. A CMOS inverter circuit that forms a drive signal according to a selection signal formed by a decoder circuit;
A first conductivity type MOSFET Q15 provided between the first conductivity type MOSFET on the power supply voltage side constituting the MOS inverter circuit and a power supply voltage terminal to which a high voltage formed by the internal booster circuit is selectively supplied; , the above MOSF
It is controlled by the voltage at the connection point between ETQ15 and the first conductivity type MOSFET constituting the CMOS inverter circuit, and the voltage at the power supply voltage terminal is controlled by the voltage at the connection point of the MOSFET Q15.
and the output terminal of the decoder circuit and the input terminal of the CMOS inverter circuit, or the input terminal of the CMOS inverter circuit and the MOSFET Q14 of the first conductivity type.
Cut MOSF installed between the gate of ETQ15
A semiconductor memory device comprising: ETQ16. 2. Claim 1, characterized in that the decoder circuit constitutes a word line and data line selection circuit of a memory array composed of memory cells to which electrical writing is performed at least. The semiconductor storage device described above. 3. The semiconductor memory device according to claim 1 or 2, wherein the memory cell is a FAMOS transistor.