JPS6145497A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To speed up operation by boosting the operating voltage of a cut MOSFET for transmitting a selection signal formed by a decoder circuit at a reading time to a driving circuit higher than an internal power supply voltage. CONSTITUTION:When the output of an inverter circuit IV2 is in the high level, the charge-up operation of a capacitor C1 is executed, and when the outputs of IV1, IV2 are inverted, one electrode of the C1 is boosted by a bootstrap function and the boosted voltage is transmitted to a C2, so that the voltage of the C2 is boosted moreover and transmitted to a C3. When said operation is repeated, about three times voltage VPP of a power supply voltage VCC is applied to the C3 and the voltage is applied for the operation of a selecting circuit as a writing high voltage. The selecting circuit applies a selection/non-selection signal formed by a gate circuit G to an inverter circuit constituted of FETs Q17, Q18 through a transmission gate 16 and the output of the inverter circuit is supplied to one word line W in a memory array M-ARY.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to technology effective for use in EPROM (Electrically Programmable Read Only Memory).

[Background technology]

An EPR'OM device using a FAMOS (Floating Gate Avalanche Injection MO5) transistor as a memory element is known (for example, Japanese Patent Application Laid-Open No. 1989-1999).
(Refer to Public Request No. 152933).

Furthermore, it is known that the EPROM device (D) peripheral circuit is configured by a CMOS (complementary MOS) circuit (for example, 15SCCDIGEST 0FTECHNICAL
, PAPER 3, pp. 182-183 February 1, 1982
(See day 1).

In this way, the word line (or data line, etc.) in an EPROM device whose peripheral circuit is composed of CMOS circuits
As a selection circuit, a circuit as shown in FIG. 3 can be considered. Address decoder XDCR receives an address signal from an atto-I-nos buffer (not shown) and forms a word line selection signal. This output signal is generated by a MOSFE whose gate is constantly supplied with the power supply voltage cc.
It is supplied to the input terminal of the word line drive circuit via TQ24. This word i spring drive times each is P channel MO
8FE'rQ21 and N channel 7ne)vMO5FETQ23
Between the input terminal of this C,MOS invert circuit and the power supply voltage terminal Vpρ, there is a P channel M which operates in response to its output signal. OS FETQ20
will be provided. Note that the power supply terminal Vpp is connected to, for example, a voltage switching circuit as shown in the above-mentioned document.
A high write voltage is supplied during a write operation, and a relatively low internal power supply voltage Vcc is supplied during a read operation.

In this circuit, during a write operation, a high voltage such as about 12V is supplied to the power supply voltage terminal (Vpl). In this state, address decoder XDCRIJ<'
When a high level (5■) non-selection signal such as the R source voltage Vcc is formed, the C
Since it is transmitted to the input terminal of the MOS impark circuit, N
Channel MOSFET Q23 is turned on. At this time, when the output signal of the address decoder XDCR is set to a high level such as the power supply voltage Vcc, the cut MO5F
ETQ24 is turned off. Therefore, due to the low level of the word line W formed by the ON state of the N-channel MOSFET Q24, the P-channel MOSFET
ETQ20 is turned on and makes the input signal of the CMOS inverter circuit a high level such as a high voltage Vpl). As a result, the P-channel MO5FETQ21 constituting the CMOS impark circuit is turned off. Next, when the address decoder XDCR forms a low level (Ov) selection signal such as the ground potential of the circuit, the cut M
OSFETQ24 is turned on again, and the input terminal of the CMOS inverter circuit is brought to a low level. This allows C
The output of the MOS inverter circuit becomes a high level such as the high voltage Vpp, and the word line becomes high level 1, which is necessary for the write operation.
It is set to 7 bells.

The above-mentioned cut MOsFET Q24 separates the output of the low-voltage address decoder circuit and the input of the high-voltage drive circuit during non-selection operation, thereby making it essential for signal level conversion operation. However, the following problem occurs during the read operation. In other words, during read operation, the above terminal Vl)
Internal power supply voltage Vcc is supplied to p. therefore,
In other words, when the output of the address decoder XDCR switches from low level to high level, word line W
When is changed from a selected state to a non-selected state, the rise of the high level (Vcc) formed by the address decoder XDCR is delayed due to the substantial increase in threshold voltage due to the substrate effect of MOSFET Q24. . This causes a problem in that the switching of the CMOS inverter circuit is delayed, the fall of the word line is delayed, and a relatively large current is generated.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device that operates at high speed.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief summary of typical inventions disclosed in this application is as follows.

That is, the cut MO5FE transmits the selection signal formed by the decoder circuit to the drive circuit during the read operation.
This is to raise the operating voltage of T to a level higher than the internal power supply voltage.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a word line selection circuit and an internal booster circuit used in a semiconductor memory device according to the present invention. Although not particularly limited, the circuit of this embodiment is built in an EPP or OM as described below, and is manufactured on a semiconductor substrate such as single-crystal silicon by, for example, a known CMO54i conductor integrated circuit manufacturing technology.
Formed together with OM. In the following description, unless otherwise specified, MOSFET (insulated gate field effect transistor) is an N-channel MOSFET. In the same figure, the MOSFET with a straight line added between the source and the drain is a P-channel type (FIG. 3 also shows a P-channel MOSFET using the same method of expression). Although not particularly limited, 5. The product circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel M
The OS FET consists of a source region, a drain region, and a polysilicon film formed on the semiconductor substrate surface between the source region and the drain region with a thin gate insulating film interposed therebetween. It consists of a gate electrode. The P-channel MO5FET is formed in an N-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOSFETs formed thereon. The N-type well region constitutes the substrate gate of the P-channel MOSFET formed thereon.

The internal booster circuit Vl)I)-G is a pulse signal ○SC formed by an oscillation circuit (not shown), which is connected to the first CMOS
It is supplied to the input of the inverter circuit IVI. The output of this inverter circuit I1 is supplied to the input of the second CMOS inverter circuit. As a result, the first. Second commercial
Complementary pulses are formed from the output terminals of the OS impark circuits IVI and IV2. The output of the second inverter circuit IV2 is a diode-type MOSFET.
It is supplied to one electrode of the capacitor C1 via Qll. The output of the first inverter circuit IVI is supplied on one side to the other electrode of the capacitor C1.

The boosted voltage formed by the capacitor C1 is transferred to the capacitor C through a diode-type MOSFET Q12.
It is supplied to one of the two iti. The output of the second inverter circuit IV2 is connected to the capacitor C2 on the other hand.
is supplied to the other electrode. The boosted voltage formed by this capacitor C2 is connected to a diode-type MOSFET Q.
13 to the boosted voltage terminal vpp, which is one electrode of the capacitor C3. The other electrode of this capacitor C3 is coupled to the ground potential point of the circuit.

The operation of the booster circuit of this embodiment is briefly described below.

When the output of inverter circuit IV2 is high level (Vcc), the output of inverter circuit IVI is low level (Ov)
Then, the above-mentioned high-level charge amplifier operation is performed on the capacitor C1.

Next, the impark circuit IV2. When the output of IVI is reversed, the capacitor C is
One electrode of C1 is boosted and transmitted to capacitor C2. The voltage of this capacitor C2 is further boosted by the bootstrap action when the inverter circuit IV2 is at a high level and is transmitted to the capacitor C3. By repeating this operation, the voltage of the capacitor C3 is approximately three times the power supply voltage Vcc. The voltage is increased to the boosted voltage vpp.

Strictly speaking, the MOSFET QI in the diode form is
The threshold voltage bone at I-Q13 is what appears as a loss of level In.

The boosted voltage Vpl) thus formed is used as a high voltage for writing (7) and is supplied as an operating voltage for the next selection circuit. The selection circuit is supplied with the high voltage Vpp during a write operation, and is supplied with the internal power supply voltage Vcc during a read operation. Examples of such a voltage switching circuit include the one shown in the above-mentioned document and the like. In this embodiment, the voltage switching circuit described above is omitted.

The unit selection circuit includes, but is not particularly limited to, a NOR gate circuit G that receives an address signal, and a drive circuit that forms a word line drive signal in accordance with the selection signal of this gate circuit G.

In this embodiment, the word line selection/non-selection signal formed by the gate circuit G is transmitted through a transmission gate (MOSFE).
CMO composed of P-channel MOSFETQ17 and N-channel MO5FETQI8 via TQI6
Supplied to the input of the S inverter circuit. The output terminal of this CMOS inverter circuit is coupled to one word line W of memory array M-ARY.

In this embodiment, although not particularly limited, in order to prevent a drop in the level of the boosted voltage VpI during a write operation, a P-channel capacitance cut MOSFET QI 5 is installed in the P-channel MOSFET QI 7 on the power supply voltage side of the CMOS inverter circuit. It is connected to the power supply voltage terminal Vpp via. The input terminal of the CMOS inverter circuit is connected to the power supply voltage terminal vpp via a P-channel MOSFET QI4. The gate of this P-channel MOSFETQ14 is connected to the gate of the above MOSFETQ.
It is coupled to the connection point between I5 and Ql7. P channel M
The gate of OSFETQ15 is coupled to the input terminal of the CMOS inverter circuit. Note that memory array M-AR
Y will be explained in detail later.

In this embodiment, in order to speed up the operation during the read operation, the gate of the transmission gate MOS FETQ 16 is connected to the MOSFET from the power supply voltage Vcc during the read operation.
A voltage Vcc+Δ■ increased by 67 times the effective threshold voltage of SFET QI 6 is selectively supplied. Such boosted voltage Vcc+ΔV is the voltage boosted by the booster circuit Vpp-
A circuit similar to G can be used. For example, by setting the other electrode of the capacitor C2 in the booster circuit vpp-c to the circuit ground potential, a diode-type MOSF
It is possible to utilize the boosted voltage appearing on one electrode coupled to ETQll.

The operation of the selection circuit of this embodiment circuit will now be described. In a read operation, a low voltage such as the internal power supply voltage Vcc is supplied to the voltage terminal vpp. Further, the gate of the transmission gate MO5FETQI6 is supplied with the boosted voltage Vcc+Δ■ as described above.

In this state, the gate circuit G constituting the address decoder XDCR is at a low level (
Ov) selection signal is formed, P channel MOSFETQ15. Ql 7 is turned on and N channel MOSFET QI 8 is turned off. As a result, the word line W is connected to the MOSFET Q15. Q1
7, the signal is charge-amplified and set to a high-level selected state. At this time, P channel Mo S F ETQ
14 is turned off because a high level voltage such as the voltage Vcc is supplied to the gate when the MOSFET QI 5 is turned on.

Next, the gate circuit G constituting the address decoder
When a non-selection signal is formed, the transmission gate MOSFE
Since the gate voltage of the TQI 6 is the boosted voltage Vcc+ΔV as described above, the high level non-selection signal rises quickly without any level loss. As a result, the N-channel MOSFET QI8 is turned on by a relatively large gate voltage, so that the high level of the selected word line W can be drawn out at high speed, and the P-channel MOSFETs Q15 and Ql
By supplying a high level such as the above-mentioned power supply voltage VCC to the gate of No. 7, it is quickly switched to the off state. Thereby, the word line W in the selected state can be switched to the non-selected state at high speed.

Note that in the write operation, the booster circuit Vpp-
The selection circuit is activated by the high voltage VpIl+ created by G. Address decoder XDCI'?
When the gate circuit G forming the gate circuit G forms a high level (5V) non-selection signal such as the power supply voltage Vcc, unlike the above read operation, the gate circuit G is turned on by supplying a voltage such as the power supply voltage Vcc. Transmission gate MOSFE
Since the above high level is transmitted through TQI 6,
N-channel MOSFETQ of CMOS inverter circuit
I8 is turned on. At this time, the gate circuit G
When the output signal reaches a high level such as the power supply voltage Vcc, the MO5FET QI 6 is turned off because its source and gate are at the same potential.

On the other hand, is it still on depending on the high level mentioned above?
, (because it is at a level lower than Vpp), the gate voltage of P-channel MOSFET QI 4 is set to
It is set to low level by the ON state of ETQ1B. As a result, the P-channel MOSFETQ14 turns on, and the high voltage vpp is transmitted to the input of the CMOS inverter circuit, so the P-channel MOSFETQ15
．． Q17 is turned off. Therefore, the word line W
is set to a low level non-selected state.

Next, when the gate circuit G constituting the address decoder XDCR forms a selection signal of low level (0■) like the ground potential of the circuit,
6 is turned on again and pulls the input of the CMOS inverter circuit to low level. This allows P channel M
OSFETQI5 and Q17 are turned on, and N-channel MOSFETQ18 is turned off. therefore,
Charge up the word line W to a high voltage level.

At this time, since the potential at the connection point between MO5FET QI 5 and Q17 has only a small parasitic capacitance, it is quickly raised to a voltage such as a high voltage vpp. As a result, P-channel MOSFET QI 4 is immediately turned off.

As a result, it is possible to substantially prevent the generation of a through current between MOSFET Q14 and the gate circuit G forming the address decoder XDCR, and the boosted voltage V
J) The decrease in P level can be reduced by a.

FIG. 2 shows a circuit diagram of an embodiment of the memory array section of an EPROM to which the present invention is applied. In the EFROM device of this embodiment, complementary address signals formed through an address buffer receiving X and Y address signals supplied from external terminals (not shown) are sent to an address decoder DC.
Supplied to H. In the figure, the address buffer and address decoder are in the same circuit block XADB-DCR, Y
Each is designated as ADB-DCR. The address buffers XADB and YADB are internal address buffers (
Complementary signal consisting of address signal and address signal of opposite phase
(Forms address signal. Address decoder DC (
R(X) is a memo according to its complementary address signal
1 The selection signal of the word line W of the real array M-ARY is
I will do it. Address decoder DCR (Y) forms a selection signal for the data line of memory array M-AR (Y) according to its complementary address signal.

The memory array M-ARY mentioned above is a representative example.
- multiple FAMOSI-transistors shown (
.

Non-volatile memory element...MOS FET Q 1
~Q6E), word lines Wl, W2, and data lines D1 to D-n. In the memory array M (-ARY, FAMOS transistors Q1 to Q3 (Q4 to
The control gates of the FAMOS transistors Q1, Q4 to Q3 . The drain of Q6 is connected to the corresponding data lines D1 to Dn!
R is connected. The FAMOS transistor D common source line C3 is, but is not particularly limited to, 78 pi: depletion type SFETQ that receives the input signal we.
Grounded via IQ. The above flea line 1] 1~
Dn is a 5 column selection switch M that receives a selection signal formed by the address decoder) CR (Y).
It is connected to the common data line CD via OSFETQ7-19.

The common data line CD has an external end r-I1 on one side.
The light is analyzed at the output terminal of the data person cover sofa DIB for write 4 which receives the write signal input from 0. The common data line CD is connected to the input terminal of a data output buffer D)B including a sense amplifier SA on the other side.

The output terminal of this data output bath sofa DOB is connected to the external terminal 110.

The control circuit C0NT forms a program signal PGM supplied from an external terminal and control signals necessary for the operation of the output enable circuit. Note that the program signal PG
When M is set to low level, the write operation mode is set, and the high voltage vpp formed by the internal booster circuit Vl)PG is applied to the address decoders XDCR, YDC via the voltage switching circuit included in the control circuit C0NT.
R and data input buffer DIB. Also,
A voltage at a level similar to the power supply voltage Vcc is supplied to the gate of the transmission gate MO5FETQI 6 in FIG. 551 above. On the other hand, when the program signal PGM is set to high level, the read mode is set, and the internal power supply voltage vcc is supplied to the address decoders XDCR, YDCR and the data cover I/F DIB by the voltage switching circuit, and the above-mentioned transmission The gate of the gate MOSFET QI 6 is supplied with the boosted voltage Vcc+ΔV.

〔effect〕

By operating the gate of the cut MOSFET for turning off the P-channel MOS FET of the CMOS inverter circuit that constitutes the drive circuit during the write operation with a boosted voltage during the read operation, the CMOS inverter circuit during the read operation can be turned off. The driving voltage of the circuit can be transmitted without level loss. As a result, the rise of the input level (non-selection signal) can be made faster, resulting in the effect that faster operation can be achieved.

Although the present invention has been specifically explained above based on the examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified to various extents without obscuring the gist thereof. [ff1J For example, in the first embodiment, a P-channel MO to achieve high-speed write operation
5FETQ15 may be omitted. In this case, the gate of P-channel MOSFET QI 4 is coupled to the word line W side. Further, the write voltage VPI) may be supplied from an external terminal.

Furthermore, the transmission gate MO5FETQI 6 may be controlled by supplying a decoded output to its gate. In this case, a bootstrap circuit for the address decoder that forms the decoded output may be provided to form the boosted voltage as described above.

Further, the memory array M-ARY and other peripheral circuits can take various embodiments.

[Application field]

In the above explanation, the present invention was mainly applied to EPROM, which is the technical field behind the present invention, but the present invention is not limited to this.For example, MNOS (metallic It can be widely used in semiconductor memory devices such as EEPROM (Electrically Erasable Programmable Read-Only) which uses Nitride Oxide Semiconductor (nitride oxide semiconductor) as a memory element.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of an EPROM to which this invention is applied, and FIG. 3 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of a circuit. XADB-DCR, YADB-DCR...Address buffer/address decoder, M-ARY...Memory array, SA...Sense amplifier, DIB...Data input buffer, DOB...Data output buffer, MA...Main amplifier, C0NT・・Control circuit, Vpp-c・・Internal booster circuit, G・・Nor gate circuit, IVI, rV2−・CM
OS inverter circuit

Claims (1)

[Claims] 1. A CMOS inverter circuit that is put into operation by selectively supplying a high voltage for writing and an internal power supply voltage, and a voltage in which the internal power supply voltage is boosted during a read operation thereof. It operates upon receiving the selection signal and sends the selection signal to the above CMO.
Transmission gate MOSFE that transmits to the input of the S inverter circuit
T is provided between the input terminal of the CMOS inverter circuit and its power supply terminal, is controlled by a voltage signal formed based on the output signal of the CMOS inverter circuit, and is connected to a MOSFET on the power supply voltage side of the CMOS circuit. A semiconductor memory device comprising a MOSFETQ14 of the same conductivity type. 2. MOSF on the power supply voltage side of the above CMOS inverter circuit
The power supply voltage side M is connected between ET and the power supply voltage terminal.
MOSFETQ15 is of the same conductivity type as the OSFET, and the input signal of the CMOS inverter circuit is supplied to the gate.
2. The semiconductor memory device according to claim 1, wherein a control signal is provided from the drain side of the MOSFET Q15 to the gate of the MOSFET Q14. 3. The CMOS inverter circuit forms drive signals for word lines and data lines of a memory array composed of memory cells to which electrical writing is performed at least. Or the semiconductor memory device according to item 2.