JPS6361497A - Fast high voltage decoder with pump type passage gate - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to high voltage decoders used in VLSI semiconductor memory arrays.

(Prior Art and Problems) In memory array devices that require high voltage signals in modes in which data is to be changed, long channel transistors output voltages higher than those output in normal read modes. must be used in the decoder. However, long channel devices limit the speed of the decoder due to the increased load. With the current trend of ever-smaller device sizes and correspondingly higher operating speeds, the need for decoders that are both high-speed and capable of providing high-voltage outputs is becoming increasingly urgent.

It is therefore an object of the present invention to provide an improved high voltage decoder. A further object of the invention is to provide a decoder that is capable of generating high voltages and at the same time operates faster than conventional decoders.

SUMMARY OF THE INVENTION In accordance with the present invention, a decoder for an array of electrically programmable memory cells in a VLSI circuit is provided. A VLST circuit is fabricated based on a predetermined minimum layout rule that includes a plurality of field effect transistors each having a channel length equal to the minimum layout rule and connected to a supply voltage vcc. It includes a logic circuit with A current source is connected between the programming voltage source and the output terminal of the decoder. A pass gate is connected between the output terminal of the logic circuit and the output terminal of the decoder. The output terminal of the decoder passes y ec to the output terminal of the decoder when the logic circuit has a high output in the READ mode, and leads the output terminal of the decoder to ground when the logic circuit has a low output.

Also, in the WRITE mode, the pass gate isolates the output terminal of the logic circuit from the output terminal of the decoder when the logic circuit has a high output, and routes the output terminal of the decoder to ground when the logic circuit has a low output.

Features of the invention that are considered novel are set forth in the claims. However, the invention itself, as well as other features and advantages, will be best understood from the following description of the embodiments, taken in conjunction with the accompanying drawings.

(Example) FIG. 1 will be explained. The decoder circuit 13 consists of a logic circuit 0 whose output is connected to an output line 16 via a pass transistor 12.

Also connected to the output line 16 is a long P-channel transistor 14 which is connected to the programming voltage VPP and has a voltage Vsat applied to its gate sufficient to drive the transistor 14 into the integrated state. The gate of pass transistor 12 is driven by the output of voltage pump 11 which is 2 Vt above the supply voltage Vcc. The illustrated logic circuit 10 is a three-way AND gate, with three P-channel transistors 22, 24 connected in parallel.
．． 26 and three N-channel transistors 28, 30, 32 connected in series, one of the P-channel transistors connected to Vcc and the other to N-channel transistor 28, and an N-channel transistor 32 connected in series.
One side is connected to ground, that is, VSS.

The output of the AND gate is taken from the drain of transistor 28, supplied to a standard inverter consisting of transistors 18 and 20, and then outputted via pass transistor 12. The voltage on line 56 applied to the gate of transistor 12 is ■. , by ensuring that the pass transistor 12 is at least 2y,g more than the total V, on the output line 16. It is possible to pass through. moreover,
Since the high voltage is applied only to the output side of the pass transistor 12, all transistors of the logic circuit can be short-channel devices.

If decoder 13 is not selected, transistor 20 conducts all current through long channel transistor 14 to ground, and since transistor 14 is in saturation, the output on line 16 can be directed to ground.

The illustrated charge pump 11 is a standard designed circuit consisting of a series of transistors 3 connected as diodes.
It consists of 4.36.38 and 40. A voltage Vcc is applied to one end of transistor 34. transistor 3
Each junction between 4 and 36, 36 and 38, and 38 and 40 is connected to a corresponding capacitor 42, 44 and 46, respectively. The output of charge pump 11 is taken from junction 55 and a voltage clamp consisting of a diode-connected transistor 50.52 connected to Vcc is connected to junction 5.
5.

In operation, two non-overlapping clock signals are connected to capacitor 4.
2.44 and 46, φ1 is input to capacitors 42 and 46, while φ2 is input to capacitor 44. Alternatively, the clock inputs may be reversed as shown in parentheses in the figure. First, junction point 35.37.
39 and 55Vcc VT, Vcc2VT, Vc
Charged to c 3Vy and Vcc 4Vt, respectively. For convenience, 1 volt, Vc for each transistor.
Let c be 5 volts. When φ1 becomes high, capacitor 4
Since the voltage across 2 and 46 cannot change instantaneously, junction 35 is raised as is junction 39. Capacitor 44 is charged from junction 35 based on the charge stored in capacitor 42 until the voltage at junction 37 is within 71 of the voltage at junction 35. Similarly, capacitor 48 is charged from junction 39 through resistor 54 and diode 40 until the voltage at junction 55 is within 77 of the voltage at junction 39. φ1 decreases. Then, capacitor 42 is charged back to Vcc-v7 via diode 34, while diode 36 is reverse biased by approximately 5.5 volts at junction 37. capacitor 4
4 begins to discharge through diode 38 into capacitor 46, and the voltage of this capacitor 46 drops due to the discharge into bulk capacitor 48. When φ2 goes high, junction 37 goes high and capacitor 44 becomes diode 38.
and 40 into capacitors 46 and 48.

This charge transfer from junction 35 to 37, 37 to 39, and 39 to 55 continues until the charge at junction 55 rises to Vcc+2Va, at which point both diodes 5
0 and 52 clamp the voltage to Vcc+2Vt.

During the WRITE mode, the voltage on line 56 is switched by switch 59 from junction 55 to Vcc. If P-channel transistor 18 is conducting, junction 19 will be at Vcc, while programming voltage □ will be 12.5 volts. That is, output line 1
6 charges to 12.5 volts, while pass transistor 12 acts as a reverse biased diode and prevents high voltage from being applied to logic circuit 10. Alternatively, if the voltage at junction 19 is at ground level, pass transistor 12 conducts and brings the output line to ground.

In the READ mode, switch 59 connects the gate of transistor 12 to junction 55, which is 2V or approximately 2 volts above Vcc. During this mode, programming voltage VPP is at Vcc. That is, if transistor 18 is conducting and applying Vcc to junction 19, the entire value of this voltage will be passed by transistor 12 to output line 16.

As an example only for the 2 micron layout rule, the short channel transistor polysilicon gate width is 2 microns, while the long channel transistor 14 polysilicon gate width is 3 microns. Due to lateral diffusion of the source and drain under the gate during manufacturing, the source and drain separation in short and long transistors is approximately 1 and 2 microns apart in practice, respectively. As layout rules become smaller, the ratio of long channel transistor length to short channel transistor length increases.

It will be clear that transistors 14 and 18 could be replaced by depletion mode transistors.

Although the invention has been described with reference to illustrative embodiments, the above description is not to be construed as limiting. Various other embodiments of the invention will be apparent to those skilled in the art upon reference to the above description. It is therefore intended that the appended claims cover all such modifications and embodiments that fall within the true scope of the invention.

In connection with the above description, the following items are disclosed.

1. In a decoder for an array of electrically programmable memory cells in a VLS 1 circuit made according to a predetermined minimum layout rule: (a) each with a channel length equal to the minimum layout rule and connected to the supply voltage Vcc; (bl) an output terminal of a decoder; (c) a current source connected between a programming voltage source and an output terminal of said decoder; and (d) an output of said logic circuit. A pass gate connected between a terminal and an output terminal of the decoder, in READ mode, passes Vcc to the output terminal of the decoder when the logic circuit has a high output; When the logic circuit has a high output, the output terminal of the decoder is grounded, and in the WRITE mode, the output of the logic circuit is isolated from the output terminal of the decoder when the logic circuit has a high output; a pass gate that leads the output terminal of the decoder to ground when the logic circuit has a low output;
decoder with.

2. The pass gate is connected to Vcc in write mode and Vcc in read mode.
,. 2. The decoder of claim 1, wherein the decoder is a pass transistor having a gate connected to a voltage source at least V greater than V.

3. The current source is connected between the programming voltage VPP and the output terminal of the decoder, and the current source is connected to the applied v2.
2. A decoder according to claim 1, wherein the decoder is a field effect transistor having a channel length long enough to withstand .

4. The decoder of claim 2, wherein the voltage source at least volts greater than vcc is the output of a charge pump which when pumped is about 2 volts.

5. VL created based on predetermined layout rules
In a decoder for an array of electrically programmable memory cells in a S 1 circuit: (al a logic circuit comprising a plurality of field effect transistors, each with a channel length equal to the minimum layout rule for the circuit and a supply voltage Vcc; (b) a pass-through transistor having a source/drain path connected between the output terminal of the logic circuit and the output terminal of the decoder; (connected between c1 programming voltage source VPP and the output terminal of the decoder; (d) a load transistor having a channel length long enough to withstand said programming voltage; (d) having an output connected to the gate of said pass transistor and, when pumped, V (( Charge pump that becomes voltage;
and (el) If VT is the threshold voltage of the pass transistor, the gate of the pass transistor is read (REA
D) -T-- (7) V cc + 2 VT
A decoder equipped with a switch that reversibly switches from Vcc to Vcc when in write mode.

6. The decoder of claim 5, wherein the load transistor has a gate voltage that places the transistor in the saturation region.

7. The logic circuit has a push-pull output driver;
In the WRITE mode, when the output of the logic circuit is low, the logic circuit connects the output of the decoder to ground, and when the output of the logic circuit is high, the pass transistor connects the output of the decoder to ground. 7. The decoder of claim 6, which is isolated from the logic circuit.

8. The charging pump is ■. Decoder according to clause 5, having an output of +2Vy.

9. The decoder of claim 6, wherein the load transistor is a P-channel transistor.

10. In the method of applying a high voltage to the output of a decoder in the WRITE mode and transferring the entire Vcc to the output of the decoder when the output of the logic circuit of the decoder is high in the READ mode: The output of the circuit is connected to Vcc in WRITE mode and Vcc in READ mode.
passing through a pass transistor having a gate connected to a voltage at least a greater than cc; and a current source at a programming voltage greater than Vcc in WRITE mode and equal to VCC in READ mode; connecting from a source to an output of the decoder.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the present invention. 10...Logic circuit, 11...
Charge pump, 12... Pass gate (transistor), 13... Decoder circuit, 14... Electric source (load transistor), 16.
...Decoder output terminal, 19...Logic circuit output. 22.24.26... Field effect transistor,
57...Switch, V((......
Supply voltage, VPP...Programming voltage source.

Claims (1)

[Claims] V created based on a predetermined minimum layout rule
In a decoder for an array of electrically programmable memory cells in an LSI circuit: (a) a logic circuit having a plurality of field effect transistors each with a channel length equal to a minimum layout rule and connected to a supply voltage Vcc; (b ) an output terminal of a decoder; (c) a current source connected between a programming voltage source and an output terminal of the decoder; and (d) a current source connected between an output terminal of the logic circuit and an output terminal of the decoder. READ at the passing gate
In the WRITE mode, Vcc is passed to the output terminal of the decoder when the logic circuit has a high output, and the output terminal of the decoder is grounded when the logic circuit has a low output, and in the WRITE mode. a pass gate that isolates the output of the logic circuit from the output terminal of the decoder when the logic circuit has a high output and leads the output terminal of the decoder to ground when the logic circuit has a low output; decoder.