JPS62200923A - Power supply synchronization direct spread modulator/ demodulator - Google Patents

Abstract

PURPOSE:To obtain an inexpensive modulator/demodulator with a simple consti tution precluding the possibility of loss of synchronization by allowing a reset means to reset a PN coder and a frequency divider at a period being an integral number of multiple of the AC power supply period. CONSTITUTION:A zero cross detection circuit 16 and an edge detection circuit 17 constitute a reset means. A noise component and a high frequency signal component are eliminated from an AC power supply of a low voltage distribu tion line 3 by a noise filter 16 to form the sinusoidal wave of a power frequency. The sinusoidal wave is formed into a rectangle wave (b) using the zero cross of the sinusoidal wave as a change point by the zero cross detection circuit 16. The edge detection circuit 17 detects the change point to generate a reset pulse having a narrow pulse width at every change point. Since PN code genera tion shift registeres 8, 2 and a frequency divider 19 are reset periodically, the PN code series at the modulation circuit side and the PN code series at the demodulation circuit are synchronized always with the power period fixedly.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention is directed to a power supply frequency that is used for the purpose of transmitting digital signals using a low-voltage distribution line as a transmission line by direct spreading means of a spread spectrum communication system. This invention relates to a modulation/demodulation device that synchronizes spreading code sequences.

(Prior Art) Conventionally, this type of apparatus has been constructed as shown in FIG. That is, the shift register 8 for generating a PN code is shifted by the output clock pulse of the clock pulse generator 9.
The phase of the PN code string outputted from the modulation circuit 1 is switched by the balance table 7 according to the digital signal of the transmission data inputted to the input terminal A of the modulation circuit 1. This two-phase phase modulated signal has harmonic components removed by a low-pass filter 6, is amplified by an amplifier 5, and is injected into the low-voltage distribution line 3 through a coupling circuit 4. The signal injected into the low voltage distribution line 3 reaches a modulation/demodulation device connected to the same low voltage distribution line 3 via the low voltage distribution line 3.

The signal reaching the coupler 4 is passed through a bandpass filter 1o+
Unnecessary noise outside the signal band is removed from i, and the balanced demodulator 1
1 is input. The balanced demodulator 11 despreads the signal using a PN code string synchronized with the PNfTN7 signal, which generates the same PN code string as during modulation. As a result, received data similar to the transmitted data is output to the output terminal B of the demodulation circuit 2.

On the other hand, in the conventional device, P
In order to synchronize the state of the N code generation shift register 12 and to match the clock pulse frequency that controls the shift of the PN code generation shift register 12, an initial synchronization acquisition circuit 13 and a clock tracking circuit 14 are used, When the device is powered on or when the low-voltage distribution line 3 recovers from a disconnection, if the incoming signal is disturbed by excessive noise and synchronization is temporarily lost, synchronization is acquired using the sliding correlation method and a method using a matched filter based on the incoming signal. In order to ensure synchronization, clock tracking is performed using methods such as tau dither method and delay lock loop.

(Problems to be Solved by the Invention) However, in such conventional modulation and demodulation devices, in order to realize a complicated method in the initial synchronization acquisition circuit and the clock tracking circuit, the circuit generally has a modern configuration using a microcomputer. It also becomes expensive. Furthermore, once synchronization is lost, it takes time to recover the synchronization, so there is a problem that data received during that time is lost.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a modulation/demodulation device that is simple in structure, inexpensive, and free from loss of synchronization.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a PN code generator, a pulse generator, and a clock pulse of the PN code generator that divides the frequency of the pulse generated by the pulse generator. It is characterized by comprising a frequency divider that generates a frequency, and a reset means that generates a reset pulse at a cycle that is an integral multiple of the AC power supply cycle and inputs the reset pulse to the PN code generator and the frequency divider.

(Function) Since the reset means resets the PN code generator and frequency divider at a cycle that is an integral multiple of the AC power supply cycle, the P
The N code string and the PN code string on the demodulation circuit side are synchronized with the power cycle.

(Example) Embodiments of the present invention will be described in detail below based on the drawings.

Figure 1 shows a power-synchronized direct spread modulation/demodulation device (
This modem is a block diagram of a low-voltage distribution line 3, a coupling circuit 4, an amplifier 5, a low-pass filter 6, a balanced modulator J3r, 7, a shift register 8 for generating a PN code, and a bandpass Filter 10, balanced demodulator 1
1, PN code generation shift register 12, noise filter 15, zero cross detection circuit 16, edge detection circuit 17
, a PLL circuit 18, and a frequency divider 19.

The zero cross detection circuit 16 and the edge detection circuit 17 constitute a reset means. Noise components and high frequency signal components are removed from the AC power supply of the low voltage distribution line 3 by the noise filter 15, and it becomes a sine wave with a power supply frequency of generally 50H2 or 60H2 as shown in FIG. 2g. This sine wave is converted by the zero cross detection circuit 16 into a rectangular wave whose changing point is the zero cross of the sine wave as shown in FIG.

The edge detection circuit 17 detects these changing points and generates a narrow reset pulse as shown in FIG. 2C at each changing point. A PLL (phase locked loop) circuit 18 receives the rectangular wave as an input and generates a high-speed pulse several hundred times higher than the frequency of the AC power source. This high-speed pulse is divided by a suitable frequency division ratio by the frequency divider 19 as shown in Fig. 2g.
This becomes a lock pulse. This clock pulse is applied to the shift register 8 for generating a PN code for modulation and the PN code for demodulation.
It is supplied to the code generation shift register 12 and determines the generation speed of the PN code string. PN code generation shift register 8
The PN code string generated from 1 and 12 generates an M-sequence code M having a length of 15 bits in this embodiment, as shown in FIGS. 2e and 3g.

Frequency divider 19 and shift register for PN code generation 8°12
is initialized by the reset pulse C at each zero-crossing point of the AC Tri source. Therefore, as shown in the time enlargement in FIG. 4, the time t from the zero-crossing point until the first clock pulse appears is approximately a constant time if the frequency division ratio of the frequency divider 19 is a sufficiently large value. Further, the code string generated from the PN code generation shift register 8.12 also becomes a code string with a constant starting state due to initialization and clock pulses.

In the modulation process, this code string is subjected to two-phase phase modulation by the balanced modulator 7 using the transmission data f. The high frequency component of the signal g whose phase has been cut off is removed by the low-pass filter 6, and the signal g is amplified by the amplifier 5 to become a transmission signal wave as shown in the second diagram. This transmission signal wave is injected into the low-voltage power distribution line 3 via the coupling circuit 4, and becomes a wave multiplied by the AC power as shown in Fig. 2 (i) and transmitted to the receiving side. In the demodulation process on the receiving side, the received signal wave shown in FIG. 3i has an AC power component removed by the coupling circuit 4 and the bandpass filter 10, and becomes the waveform shown in FIG. 3j. This waveform j is despread in a balanced demodulator 11 using the same code string g synchronized with the AC power supply as on the modulation side, and demodulated into received data that is the same as the transmitted data as shown in FIG.

Therefore, in this embodiment, the PN code generation shift register 8,
12 and frequency divider 19 are reset periodically, the PN code string on the modulation circuit side and the PN code string on the demodulation circuit side are always fixedly synchronized with the power supply cycle.

As a result, there is no delay time for acquiring initial synchronization when turning on the device power or recovering from a break in the low-voltage distribution line, there is no loss of synchronization due to speech noise or switching noise of load equipment, and there is less data transmission.

Next, another embodiment will be described based on FIG.

This embodiment uses a high-speed pulse oscillation source using a crystal resonator, a ceramic resonator, etc., regardless of the power frequency, whereas the embodiment shown in FIG. This is an embodiment in which a high-speed pulse is generated by using a pulse generator 20. The accuracy of the power supply frequency is now as accurate as that of a crystal oscillator, so if the clock pulse frequency is selected low enough to be equal to or greater than the jitter of the zero-cross detection circuit 16, the interval between one reset pulse and the next reset pulse can be reduced. The number of clock pulses present in each signal does not vary, and a constant code string can be generated.

Therefore, a high-speed pulse generation function can be realized with a simpler configuration than a PLL circuit.

In both the embodiments shown in Fig. 2 and Fig. 3, one of the 15-pip length M-sequence codes is used as the PN code string, but this is not the case; if the bit length is a PN code, the frequency used can be changed. It can be said that it is preferable that the length be as long as possible within the band and within the range where equipment noise is allowed, in order to take advantage of the feature of increasing the processing gain of spread spectrum communication. Furthermore, it is a matter of fact that the code used for spreading can be used as long as it is not an M-sequence code but has strong autocorrelation characteristics such as a GOLD code and has low cross-correlation. Although the data transmission speed is twice the power cycle in the embodiment, it can be realized at an integer multiple.

Furthermore, the same function can be achieved by replacing the PN code generation shift register with a combination of a pulse counter and a decoder, a pulse counter and a memory, or the like.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a modulation/demodulation device that has a simple configuration, is inexpensive, and has no fear of loss of synchronization.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a device according to an embodiment of the present invention, Fig. 2 is a waveform of each part in the modulation process, Fig. 3 is a waveform of each part in the demodulation process, and Fig. 4 is a combination of Figs. 2 and 3. FIG. 5 is a block diagram of another embodiment of the device of the present invention, and FIG. 6 is a block diagram of a conventional direct sequence modulation/demodulation device for carrying power distribution lines. DESCRIPTION OF SYMBOLS 1... Modulation circuit, 2... Demodulation circuit, 3... Low voltage distribution line, 4... Coupling circuit, 5... Amplifier, 6... Low pass filter, 7... Balanced modulator, 8... Shift register for PN code generation, 9... Clock pulse generator, 10... Band pass filter, 11... Balanced demodulator, 12... Shift register for PN code generation, 13
... Initial synchronization acquisition circuit, 14 ... Clock tracking circuit, 15 ... Noise filter, 16 ... Zero cross detection circuit, 19 ... Frequency divider, 20 ... High speed pulse oscillation source. Figure 1 Figure 2 Figure 3

Claims (1)

[Scope of Claim] A power-synchronized direct spread modulation/demodulation device using a direct spread method in spread spectrum communication that transmits and receives digital information using a power line that supplies AC power as a transmission path, comprising: a PN code generator; a pulse generator; a frequency divider that divides the frequency of the pulse generated by the pulse generator to generate a clock pulse for the PN code generator; and a frequency divider that generates a reset pulse at a cycle that is an integral multiple of the AC power supply cycle and uses this reset pulse to generate the PN code generator. 1. A power-synchronized direct spread modulation/demodulation device, comprising: a frequency divider; and a reset means for inputting an input to the frequency divider.