JPH0312497B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to spread spectrum power line transport that uses power lines as transmission paths, and in particular to power synchronization that uses power supplies to synchronize operations on the transmitter and receiver sides. The present invention relates to a communication method and device.

[Prior art]

Conventionally, when transmitting information signals using power lines, various modulation methods have been used depending on the type of transmission path. For example, in the case of a power transmission line transmission line, a single sideband modulation method is used, and in the case of a distribution line transmission line, a frequency modulation method or a phase modulation method is used. Here, power lines are not laid with signal transmission in mind, so when attempting to transmit information signals, various noises may enter, or the transmission characteristics may change depending on the load situation. It has a problem that varies widely. In other words, the high-frequency characteristics of a power line, regardless of whether it is a power transmission line or a power distribution line, have large corona noise and load noise, and vary greatly depending on the load state of the power line. Therefore, it has been difficult to perform highly reliable signal transmission, and in particular, high-speed data transmission has been impossible.

By the way, research has recently been underway to actively utilize the spread spectrum communication method in various fields, and an explanation of its principles and application fields can be found in the September 1989 issue of the Journal of the Institute of Electronics and Communication Engineers, pages 965 and 10.
It is disclosed on page 1053 of the monthly issue. This spread spectrum communication method is characterized by a wide spectrum, the use of special codes, and correlated signals, and when used to transmit information signals using power lines, it becomes less susceptible to noise and transmission characteristics. Therefore, it becomes possible to perform high-speed data transmission with high reliability. In other words, this spread spectrum communication method transmits a narrowband information signal by spreading its spectrum evenly over a wide band, so the power line is not in a state where zero points occur in the transmission characteristics depending on the load condition. Even if narrowband noise is mixed in, the signal-to-noise ratio is increased because the correlation is taken on the receiving side.

Figure 4 shows the spread spectrum communication method (hereinafter referred to as
This is an overall configuration diagram showing an example of the use of the SS communication method for power line transmission, in which modulation is performed using a pseudo-noise signal called PN spreading or direct spreading, and in particular, as a pseudo-noise signal. M
A series code is used. This M-sequence code is the longest of the linear code sequences generated by a certain number of stages of shift registers and feedback circuits, and the values at each instant within one cycle are distributed in a quasi-noise state. It is set as follows. 1, 2 in the diagram
are a transmitting device and a receiving device connected via the power line 3. In the transmitter 1, 4 is a clock oscillation circuit that generates a clock pulse CP with a frequency of, for example, 250 KHz, and 5 is a zero-cross detection circuit, which detects a zero-cross every time it detects a zero-cross point of the AC power supplied via the power line 3. Generates detection signal Z. Reference numeral 6 denotes an M-sequence code generation circuit for transmission that generates an M-sequence code as a pseudo noise signal, and as shown in FIG. 5, for example, a three-stage shift register 6a and a second
It is composed of an exclusive OR gate 6b that calculates the exclusive OR of the outputs of the first and third stages and returns it to the input side, and the input is determined according to the clock pulse CP supplied from the clock oscillation circuit 4. By sequentially shifting the signals, an M-sequence code with a maximum code length of 2 ⁿ -1 (n is the number of shift stages) is generated from the final stage. Moreover, this transmission M-sequence code generation circuit is
Zero cross detection signal Z from zero cross detection circuit 5
is supplied, the shift register 6 shown in FIG.
Flip-flop circuits FF ₁ to 1 constitute each stage of a.
It is designed to reset all FF ₃ to "1". 7 is a spread spectrum modulation circuit,
The M-sequence code supplied from the transmission M-sequence code generation circuit 6 and the transmission data are multiplicatively modulated (exclusive OR is calculated) to convert the transmission data into a modulated signal subjected to spread spectrum modulation. There is.
8 is a coupling circuit composed of a transformer 9 and capacitors 10a and 10b, which receives the modulated signal supplied from the spread spectrum modulation circuit 7 via a filter for removing low frequency components (not shown) and a transmission amplifier. Output to power line 3.

On the other hand, in the receiving device 2, 10 is the same clock pulse CP as the clock oscillation circuit 4 of the transmitting device 1.
Reference numeral 11 is a zero-cross detection circuit that generates a zero-cross detection signal Z every time a zero-cross of the AC power supplied via the power line 3 is detected. 12 is an M-series code generation circuit for reception, and M-series code generation circuit 6 for transmission.
Similarly, it has the configuration shown in FIG. 1
3 is a coupler for extracting the spread spectrum modulated signal sent from the transmitter side via the power line 3, and includes a transformer 14, a capacitor 15a,
15b. Reference numeral 16 denotes a spread spectrum demodulation circuit, which receives the M-sequence code supplied from the receiving M-sequence code generation circuit 12 and the modulated signal supplied from the combiner 13 via a receiving amplifier (not shown) and a filter for removing low frequency components. By multiplying by , correlation detection is performed and received data is extracted.

In the SS communication device constructed in this manner, when the power switch is turned on, the clock oscillation circuits 4 and 10 provided in the transmitting device 1 and the receiving device 2, respectively, send out clock pulses CP of the same period. Furthermore, the zero-cross detection circuits 5 and 11 provided in the transmitter 1 and the receiver 2 are
A zero-cross detection signal Z is generated every time a zero-cross of the AC power supplied via the power line 3 is detected. And this zero cross detection circuit 5,1
1 performs zero-cross detection for the AC power flowing through the same power line 3, so the zero-cross detection signals Z generated from both circuits are synchronized.

Here, the transmission M-sequence code generation circuit 6 has a fifth
Since the configuration is as shown in the figure, when the zero-cross detection signal Z is generated from the zero-cross detection circuit 5 at time _t1 in FIG. From this, the flip-flop circuit
The outputs of FF ₁ to _{FF 3} are reset to all "1" states as shown in FIGS. 6a, b, and c. Therefore, the output signal of the exclusive OR gate 6b becomes "0" as shown in FIG. 6d. Next, when the clock pulse CP rises as shown at time _t2 in FIG.
By reading and shifting the output signal of b,
The output signals of each flip-flop circuit FF ₁ to FF ₃ are "0", "1", and "1". Next, when the clock pulse CP rises as shown at time _t3 in Figure 6e,
Since the output of the exclusive OR gate 6b continues to be in the "0" state, the shift register 6a takes in this "0" signal and shifts it, so the output signal of each flip-flop circuit _FF1 to _{FF3 becomes} "0". ”, “0”, and “1”. Here, the exclusive OR gate 6b includes flip-flop circuits FF ₂ ,
Since the output of FF ₃ is input, if a mismatch occurs in the output, a "1" signal is output as shown in FIG. 6d. The output signal of this exclusive OR gate 6b is taken into the shift register 6a at the next rising edge of the clock pulse CP. By sequentially performing such operations, an M-sequence code having a period _T1 between time points _t2 and _t9 is obtained from the final stage flip-flop circuit _FF3 , as shown in FIG. 6c. Since this M-sequence code is generated while being reset by the zero-crossing detection signal Z, it is synchronized with the AC power flowing through the power line 3.

In this way, the M-sequence code generated in synchronization with the AC power supply is multiplicatively modulated with the transmission data synchronized with the high-frequency clock pulse CP in the spread spectrum modulation circuit 7, thereby transmitting the narrowband transmission data. is output as a modulated signal whose spectrum is uniformly spread over a wide band. After removing low frequency components from the modulated signal in a filter (not shown), the modulated signal is amplified to a predetermined level in a transmission amplifier, and is sent to the power line 3 by being supplied to the coupler 8.

On the other hand, in the receiving device 2 as well, based on the clock pulse CP output from the clock pulse oscillation circuit 10, the receiving M-sequence code generating circuit 12 generates an M-sequence code having the same configuration as the transmitting M-sequence code generating circuit 6. It has occurred. The reception M-sequence code generation circuit 12 is a zero-cross detection circuit 1 that detects zero-cross of AC power flowing through the power line 3.
1, the generated M-sequence code is synchronized with the AC power supply, that is, synchronized with the M-sequence code output from the transmission M-sequence code generation circuit 6. It has been taken. The coupler 13 takes out the modulated signal sent from the transmitter 1 via the power line 3, and after this modulated signal is amplified in a receiving amplifier (not shown), low frequency components are removed in a filter. and is supplied to the spectrum despread demodulation circuit 16. The spectrum despread demodulation circuit 16 extracts received data by multiplying the M-sequence code supplied from the receiving M-sequence code generation circuit 12 by the received modulated signal that is spread spectrum and sent. .

[Problem that the invention seeks to solve]

However, in the SS communication method described above, the M-sequence code generation circuit for transmission and the M-series code generation circuit for reception generate M-sequence codes based on the zero-crossing point of the AC power flowing through the power line used as the transmission path. Therefore, I am trying to synchronize the two, but the following problems occur.

For example, when the clock pulse frequency is 250KHz, the width of one chip of the M-sequence code is 1/250=
It becomes 4μsec. On the other hand, with the M-sequence codes used for modulation and demodulation in the transmitter/receiver, normal communication cannot be performed unless the mutual phase shift is at least within ±0.5 chips. However, due to the characteristics of the zero-crossing detection circuit, the timing at which zero-crossing is detected is shifted by about 10 μsec, so the generated M-sequence code also has a phase shift of about 10 μsec, making it impossible to perform normal communication. In addition, the clock pulses generated in each transmitter and receiver are asynchronous, and even if there is no shift in the timing of zero-cross detection, a phase shift of up to one clock occurs, resulting in a phase shift of the M-sequence code. ±
If the chip is off by one chip, normal communication will no longer be possible. Furthermore, when the M-sequence code is generated in synchronization with the zero-crossing point, since the M-series period and the AC power supply period do not match, the M-sequence code generation operation is forced when the zero-crossing point is detected. It is reset and interrupted, and as a result, normal communication cannot be performed in the periodic part of the M-sequence code that includes this zero-crossing detection point. In addition, in cases where the transmitting side and the receiving side are relatively far apart, a phase difference may occur in the AC power source between the transmitter and the receiver depending on load fluctuations on the power line 3. Since the M-sequence code generated in synchronization with the zero-crossing point of the transmitter and receiver is shifted from each other during transmission and reception, there is a problem in that normal communication cannot be performed.

[Means for solving problems]

In order to solve such problems, the power synchronization communication method and device for spread spectrum power line carrier according to the present invention provides an arbitrary integer K when generating M-sequence codes from M-sequence code generation circuits on the transmitting side and the receiving side. and when the maximum cycle length of the generated M-sequence code is N, synchronized with the phase of the AC power flowing through the power line used as a transmission path,
and a power supply synchronized clock generation circuit that generates a first clock pulse having a frequency KN times as high as the frequency, and a second clock pulse synchronized with the AC power supply and having a frequency K/2 times the frequency of the first clock pulse, The M-sequence code generation circuits on the transmitting side and the receiving side use the first clock pulse as a basic clock and generate an M-sequence code whose phase is synchronized with the second clock pulse to modulate the transmitted information and demodulate the received modulated signal. It is something to do.

[Effect]

Therefore, when an M-series code is generated in this way, the cycle of the M-series code is always synchronized with the AC power flowing through the power line used as an electric transmission line, so The generated M-sequence codes on the transmitting side and on the receiving side will completely match. In this case, generation of the M-sequence code synchronized with the AC power supply is not done by forcibly adding a reset process to synchronize when the zero cross point of the AC power supply is detected, as is the case in the past, but by using a phase lock. A first clock signal as a basic clock synchronized with an AC power source and a second clock signal having a period of 1/2N with respect to this first clock signal are generated by a loop, and this first clock signal is synchronized with an AC power supply. Since the generation period of the M-sequence code by the signal is synchronized with the second clock signal, once the synchronization is established, it is controlled so that the state is maintained continuously, and the disturbance of the M-sequence code that is generated is controlled. is to be prevented.

〔Example〕

FIG. 1 is an overall configuration diagram showing an embodiment of a power synchronization communication method and device in spread spectrum power line carrier according to the present invention, and the same parts as in FIG. 4 are given the same symbols and detailed explanation thereof is omitted. There is. In the figure, 17 is a power synchronized clock generation circuit, which is synchronized with the AC power supplied via the power line 3, and the maximum period length of the M-sequence code used is N, and an arbitrary integer is K. The clock pulse CP 1 is configured to generate a clock pulse CP ₁ having a frequency K/2×2N times as high as the AC power supply frequency, and a clock pulse CP ₂ that is synchronized with the AC power supply and has a frequency 2N times as high as that frequency. has been done. 18 is a transmitting M-sequence code generation circuit that generates an M-sequence code using the clock pulse CP ₁ outputted from the power supply synchronous clock generation circuit 17 as a basic clock; 19 is a spread spectrum modulation signal outputted from the spread spectrum modulation circuit 7; transmission amplifiers 20 and 21 that amplify and supply the amplified signal to the coupling circuit 8;
are a power synchronized clock generation circuit and a reception M-series code generation circuit provided in the receiving device 2, which are the same as the power synchronized clock generation circuit 17 and the transmission M-series code generation circuit 18 provided in the transmitting device 1. It consists of: 22 is a receiving amplifier that amplifies the modulated signal output from the coupler 13 and supplies it to the spectrum despread demodulation circuit 16.

FIG. 2 is a circuit diagram showing a specific example of the power supply synchronous clock generation circuits 17, 20 and the transmitting/receiving M-series code generation circuits 18, 21 shown in FIG. In the figure, 23 is a phase that compares the phase of the AC power (AC100V) supplied via the power line 3 and the output signal of the frequency divider 27, which will be described later, and outputs a signal with a level corresponding to the phase difference. A comparator 24 is a low-pass filter 2 that smoothes the output of the phase comparator 23.
5 is a voltage-controlled variable frequency oscillator (hereinafter referred to as VCO) whose control input is the output of the low-pass filter 24;
and generates a clock pulse _CP1 . 26
is a frequency divider, and when the maximum period length of the M-sequence code generated from the transmitting/receiving M-sequence code generation circuits 18 and 21 is N, the clock pulse CP ₁ is divided into 1/2N.
Generates a clock pulse CP ₂ whose frequency is divided into 2. 27
is the clock pulse CP ₂ output from the frequency divider 26
This is a frequency divider that divides the frequency into 2/K (K is an arbitrary integer) and supplies the frequency to the phase comparator 23. And these phase comparator 23, low pass filter 24,
By configuring a phase lock loop (PLL) circuit, the VCO 25 and frequency dividers 26 and 27 synchronize with the AC power supply and the clock pulse CP ₁ , which has a frequency N×K times the frequency of the AC power supply. Moreover, a clock pulse CP ₂ that is 2N times that frequency is generated. Next, the transmitting/receiving M-sequence code generating circuits 18 and 21 are constructed using a shift register 6a in which flip-flop circuits FF ₁ to FF ₃ are connected in series, and flip-flop circuits FF ₁ , FF as described in FIG. When the number of stages of the shift register 6a is n, the exclusive OR game 6b calculates the exclusive OR for the output signal ^of ₃ and returns it to the input side. A series code is generated.
28 is an AND gate for determining the coincidence of all stage outputs of the shift register 6a; 29 is an AND gate 2;
8 is a frequency divider that divides the output of frequency divider 29 into 1/2, 30 is an exclusive OR gate that determines the mismatch between the output signal of frequency divider 29 and clock pulse CP ₂ , and 31 is an output signal of exclusive OR gate 30. and clock pulse _CP1 , and its output signal is supplied to the clock input terminal CK of the shift register 6a. These AND gate 28, frequency divider 29, exclusive OR gate 30, and OR gate 31 are connected to the M
Synchronization control is performed to synchronize the series code with the AC power supply.

In the spread spectrum power line carrier communication system configured in this way, when power is supplied to the transmitting device 1 and the receiving device 2, the power synchronized clock generation circuits 17 and 21 first activate the AC power ( Generate clock pulses CP ₁ to _{CP 2} synchronized with AC100V). That is, in FIG. 2, the clock pulse _CP1 generated from the VCO 25 is sequentially frequency-divided by the frequency dividers 26 and 27 and then supplied to the phase comparator 23. The phase comparator 23 compares the phase of the output signal of the frequency divider 27 and the AC power supply (AC100V), and outputs a control signal that expresses the direction of the phase difference by a polarity and expresses the phase difference by a level. . This control signal is smoothed in the low-pass filter 24 and then supplied to the control signal input terminal of the VCO 25, thereby controlling the value of the control signal output from the phase comparator 23 to be small. By repeating such control, that is, by performing phase lock loop (PLL) control, the phase of the clock pulse CP ₁ shown in FIG. 3b output from the VCO 25 changes to the AC power supply shown in FIG. 3a. It will be locked to the phase of AC100V.
In this case, the clock pulse CP ₁
Since the frequency dividers 26 and 27 are provided in the phase lock loop, the frequency of the AC power source has a frequency NK times as high as the product of the frequency division values of both frequency dividers. Further, the frequency divider 26 outputs a clock pulse CP ₂ obtained by dividing the clock pulse CP ₁ by 1/2N as shown in FIG. 3f. Since this clock pulse CP ₂ is created based on the clock pulse CP ₁ , it is synchronized with the AC power supply (AC 100V), and since the frequency division value of the frequency divider 26 is 2N,
One of the M-sequence codes used in this system
A signal that inverts to "H" and "L" for each period that matches the period length, that is, as shown in Figure 3 f, is synchronized with the AC power supply (AC 100 V) shown in Figure 3 a, and has twice the frequency. It becomes a signal.

The clock pulses CP ₁ and CP ₂ generated from the power supply synchronized clock generation circuit 17 in this manner are supplied to the transmission M-sequence code generation circuit 18 . In Figure 2, clock pulse CP ₁ is OR gate 31.
to the clock input terminal of shift register 6a via
Since it is supplied to CK, the shift register 6a
sequentially shifts the output signal of the exclusive OR gate 6b, and the output of each flip-flop FF ₁ to FF ₃ becomes as shown in FIG _. is output as an M-sequence code having a pattern determined by the input conditions of the exclusive OR gate 6b.

Here, when the shift register 6a is cleared at the time t2 shown in FIG. ₃ during initialization when the power is turned on or in the reset mode, the output signals of the flip-flops _FF1 to _FF3 are All are set to "1" as shown in Figures c to e. And this flip-flop
Every time the outputs of FF ₁ to _{FF 3} become all "1", the output signal A of the AND gate 28 becomes "H" as shown in FIG. It is supplied to exclusive OR gate 30 as output signal B shown in FIG. 3g. In other words, divider 2
The signal B output from 9 is normally M
This is a signal that inverts between "H" and "L" every cycle of the sequence code. Output signal B generated in this way
is compared with the clock pulse _CP2 in the exclusive OR gate 30, and if they match, it means that the generated M-sequence code is synchronized with the AC power supply (AC100V). However, when the clock pulse _CP2 is inverted from "H" to "L" at time _t3 , the output signal B of the frequency divider 29 and the clock pulse
Since CP ₂ does not match, the output signal of the exclusive OR gate 30 becomes “H” as shown in FIG. 3h.
becomes. Here, when the output signal C becomes "H",
OR gate 31 fixes its output signal D to "H" as shown in FIG. 3i, even though clock pulse _CP1 is supplied. In other words, the frequency dividing circuit 2 indicates the period of the M-sequence code actually generated.
During the period of mismatch between the output signal B of 9 and the clock pulse _CP2 indicating the generation cycle of the M-sequence code synchronized with the AC power source, the signal C shown in FIG. 3h output from the exclusive OR gate 30 is Since it becomes “H”, the “H” portion of this signal C becomes the OR gate 3.
By fixing the clock pulse CP 1 passing through CP ₁ to the "H" state, the clock pulse CP 1 is cut. Therefore, as shown in FIG. 3i, the shift register 6a remains supplied with the clock pulse D indicated by . Next, at time _t4 , when the clock pulse _CP2 is inverted to "H", the output signal B of the frequency divider 29 shown in FIG. 3g and the output signal B shown in FIG.
Since the clock pulses _CP1 shown in FIG. 3 coincide, the output signal C of the exclusive OR gate 30 becomes "L" as shown in FIG. 3h. As a result, the clock pulse _CP1 is again supplied from the OR gate 31 to the shift register 6a as the clock pulse D shown in FIG. 3i. Then, Fig. 3 shows the time point i.
After the clock pulse D shown at _t5 is generated, when the clock pulse D shown at time _t6 rises, the flip-flops _FF1 to _FF3
Since the outputs of are all "H" as shown in FIG. 3c to e, the output signal A of the AND gate 28 is inverted to "H" at time _t6 as shown in FIG. 3j. . Since this inversion of the output signal A to "H" is the second time from time _t2 , the output signal B of the frequency divider 29 is inverted to "L" accordingly. When output signal B becomes “L”, clock pulse CP ₂
Since there is a mismatch between the two, the output signal C of the exclusive OR gate 30 becomes "H" and the supply of the clock pulse D to the shift register 6a is blocked.

Next, at time _t7 , when the clock pulse _CP2 is inverted to "L", the output signal C of the exclusive OR gate 30 is also inverted to "L", so that the clock pulse D is output from the OR gate 31. Third, at time points t ₈ , t ₉ , t ₁₀ . . . , the signals are output as shown as . . . and supplied to the shift register 6a. Then, after this time _t8 , the numbers shown in _FIG . The clock pulse CP ₁ generated in synchronization with the AC power supply AC100V is repeatedly counted for each maximum code length of the M-sequence code from the zero cross point of the AC power supply as shown in Figure _3b .
The numbers 2, 3, 4, etc. will match.
In other words, the output signal B of the frequency divider 29, which is inverted to "H" and "L" every cycle of the M-sequence code generated from the shift register 6a, generates the M-sequence code in synchronization with the AC power supply AC100V. The clock pulse D supplied to the shift register _6a is thinned out so as to be synchronized with the clock pulse CP2 (which is inverted to "H" and "L" every cycle) indicating the period in this case. In this way, the M-sequence code generated from the shift register 6a is
Once synchronized with AC100V, this state is locked, and from then on, the power supply synchronized clock generation circuit 17 generates clock pulses completely synchronized with the AC power supply AC100V.
Since CP ₁ and CP ₂ continue to be generated, even if the phase of the AC power source fluctuates somewhat for some reason, the generated M-sequence code will always be synchronized with the AC power source. This operation is instantaneously performed when the power is turned on.

In this way, the transmission M-series code generation circuit 18
The M-sequence code synchronized with the AC power source generated by the transmitter is multiplicatively modulated with the transmission data in the spread spectrum modulation circuit 7, so that the narrowband transmission data is spread spectrum uniformly over a wide band. is output as a modulated signal. The modulated signal generated in this manner is amplified in the transmission amplifier 19 and then sent out to the power line 3 via the coupler 8.

On the other hand, the power synchronization clock generation circuit 20 and the receiving M-series code generation circuit 21 in the receiving device 2
has the same configuration as the power synchronization clock generation circuit 17 and the transmission M-series code generation circuit 18 in the receiving device 1, as shown in FIG.
As in the case of the transmitting device 1 described above, the clock pulses CP ₁ and CP ₂ synchronized with the AC power supply are generated instantaneously from the time the power switch is turned on, and the M-sequence code synchronized with the AC power supply is generated. is generated from the reception M-sequence code generation circuit 21. The coupler 13 extracts only the spread spectrum modulated signal supplied from the transmitter 1 via the power line 3. This modulated signal is amplified in a reception amplifier 22 and then supplied to a spectrum despread demodulation circuit 16.
The M-sequence code supplied from 1 and the modulation signal supplied from the receiving amplifier 22 are multiplied and demodulated to output received data.

Here, since the M-sequence code outputted from the transmitting M-sequence code generation circuit 18 and the M-sequence code outputted from the receiving M-sequence code generation circuit 21 are generated in synchronization with the common AC power supply, The two will be completely synchronized. Therefore, since the spectrum despread demodulation circuit 16 performs product demodulation of the received modulated signal using the same M-sequence code as used during modulation, it is possible to reliably extract received data that is the same as transmitted data. Furthermore, even if the phase of the AC power source fluctuates somewhat for some reason, the phases of the clock pulses CP ₁ and CP ₂ will change accordingly, so that the M generated in the transmitter 1 and the receiver 2 will change. The series code is always synchronized with the AC power source.

〔Effect of the invention〕

As explained above, the power synchronization communication method and device for spread spectrum power line carrier according to the present invention generates a spread spectrum modulated signal by product demodulating the M-sequence code generated on the transmitting side and the transmitted data. In spread spectrum power line transmission, the received data is extracted by multiplying and demodulating the received modulated signal on the receiving side using the same M-sequence code as at the time of transmission. The maximum period length is N,
When K is an arbitrary integer, the phase of the first clock pulse is synchronized with the AC power supply flowing through the power line used as a transmission path, and the first clock pulse having a frequency K.N times that of the AC power supply, and the phase of the first clock pulse is synchronized with the AC power supply, and Its K/2
A second clock pulse having twice the frequency is generated on the transmitting side and the receiving side respectively, and the M-sequence code is generated by synchronizing the phase with the second clock pulse using the first clock pulse as a basic clock. , this M-sequence code is used to perform spectrum modulation and spectrum despread demodulation of transmission data. For this,
Since the M-sequence codes used on the transmitting side and the receiving side are always synchronized with the AC power flowing through the power line, the two always match and reliable demodulation can be performed. In addition, in this invention, synchronization is not obtained by forcibly resetting at the zero cross point of the AC power supply as in the past, but by using a first clock pulse whose phase is synchronized with the AC power supply and a phase synchronization with the AC power supply. Since the M-sequence code is synchronized and the second clock pulse indicating each cycle of the generated M-sequence code is used to generate the M-sequence code, there is no reset during the generation of the M-sequence code as in the conventional method. This solves the problem of not being able to communicate due to the addition and interruption. Furthermore, even if the phase of the AC power flowing through the power line shifts slightly between transmission and reception for some reason, the period of the M-sequence code generated will be varied accordingly, so it will always be It has various excellent effects such as being able to reliably demodulate the received modulated signal and extract the received data.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram for explaining an embodiment of a power synchronization communication method and device in spread spectrum power line transmission according to the present invention, and FIG.
A circuit diagram showing a specific example of the power supply synchronized clock generation circuit and the transmitting/receiving M-sequence generating circuit shown in the figure, Part 3.
Figures a to j are operation waveform diagrams of each part to explain the operation of the circuit shown in Figure 2, Figure 4 is a block diagram showing an example of a conventional spread spectrum power line transmission communication system, and Figure 5 is the same as Figure 4. A circuit diagram showing an example of an M-series code generation circuit for transmission and reception shown in FIGS. 6a to 6f.
5 is an operational waveform diagram of each part of the circuit shown in FIG. 5. FIG. DESCRIPTION OF SYMBOLS 1... Transmitting device, 2... Receiving device, 3... Power line, 6a... Shift register, 6b... Exclusive OR gate, 7... Spread spectrum modulation circuit,
8, 13...Coupler, 16...Spectrum despread demodulation circuit, 17, 20...Power synchronization clock generation circuit, 18...M-series code generation circuit for transmission, 1
9... Transmission amplifier, 21... M-series code generation circuit for reception, 22... Receiving amplifier, 23... Phase comparator, 24... Low pass filter, 25... Voltage controlled variable frequency oscillator (VCO), 26 , 27... Frequency divider, 28... AND gate, 29... Frequency divider,
30...Exclusive OR gate, 31...OR gate.

Claims (1)

[Claims] 1. A modulated signal in which the transmitted data is spread spectrum is generated by product modulating the M-sequence code generated on the transmitting side and the transmitted data, and the signal is supplied to the power line and sent to the receiving side. In this case, the same M as when sending
In a spread spectrum power line carrier communication method in which received data is multiplied and demodulated using a sequence code and a modulated signal received via a power line, when the maximum period of the M sequence code is N and an arbitrary integer is K, the transmission A first clock pulse that is synchronized in phase with the AC power supply flowing through the power line used as a power line and has a frequency K/N times that of the AC power supply, and a first clock pulse that is synchronized in phase with the AC power supply and has a frequency K/2 times that of the AC power supply. A second clock pulse is generated on the transmitting side and the receiving side, and the first clock pulse is used as a basic clock, and the generation period thereof coincides with the "H" and "L" periods of the second clock pulse, respectively. 1. A power source synchronized communication method in spread spectrum power line transmission, characterized in that a code is generated and an M-sequence code synchronized with the power source is used to perform spread spectrum modulation of transmission data and despread spectrum demodulation of a received modulated signal. 2 The phase is synchronized with the AC power flowing through the power line used as a transmission line, and when the maximum cycle length of the M-sequence code used is N and an arbitrary integer is K, the frequency is NK times the frequency of the AC power supply. phase synchronized with the first clock pulse having an AC power supply;
and a power-synchronized clock generation circuit that generates a second clock pulse indicating the generation period of the M-sequence code by changing it to "H" or "L"; An M-sequence code generation circuit that generates an M-series code whose generation cycle is synchronized with “H” and “L” changes;
A spread spectrum modulation circuit outputs a modulated signal in which the transmission data is spread spectrum over a wide band by multiply modulating the transmission data using the M-sequence code generated from the sequence code generation circuit, and from the spread spectrum modulation circuit. a coupling circuit for supplying an output modulated signal to the power line, a transmitting device is configured, a power synchronized clock generating circuit and an M-sequence code generating circuit having the same configuration as those provided in the transmitting device; A coupling circuit extracts a modulated signal sent from the transmitter via a power line, and a spectrum despread demodulates the modulated signal output from the coupling circuit using the M-sequence code output from the M-sequence code generation circuit. 1. A power supply synchronized communication device in spread spectrum power line transmission, characterized in that the receiving device includes a spectrum despread demodulation circuit that extracts received data by performing the following steps. 3. The power-synchronized clock generation circuits on the transmitting and receiving sides are equipped with a voltage-controlled variable frequency oscillator that generates a first clock pulse, and a second clock pulse that generates a second clock pulse by frequency-dividing the first clock pulse by 1/2N. a frequency divider of 1 and a second frequency divider that divides the second clock pulse by 2/K;
a phase comparator that compares the phase of the second frequency divider output and the AC power flowing through the power line and generates an output according to the phase difference; and a phase comparator that smooths the output signal of this phase comparator to vary the voltage control. 3. A power synchronization communication device for spread spectrum power line transport according to claim 2, characterized in that it is constituted by a low pass filter that supplies a control signal to a frequency oscillator. 4. The M-sequence code generation circuits on the transmitting and receiving sides generate the M-sequence code by calculating the exclusive OR of the shift register and the outputs of multiple stages of the shift register and returning the output to the input end of the shift register. an exclusive OR gate to generate;
an AND gate for determining the coincidence of outputs of all stages of the shift register; a frequency divider for dividing the output signal of the AND gate by two; and a frequency divider for dividing the output signal of the AND gate by two; The output signal of this exclusive OR gate and the first clock pulse supplied from the power supply synchronized clock generation circuit are input to an exclusive OR gate, and the output signal is used as the basic clock. 3. The power supply synchronization communication device in spread spectrum power line transport according to claim 2, characterized in that the communication device comprises: an OR gate that supplies the shift register to the shift register;